1*9fe640a5SBin Meng /* 2*9fe640a5SBin Meng * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface 3*9fe640a5SBin Meng * 4*9fe640a5SBin Meng * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 5*9fe640a5SBin Meng * 6*9fe640a5SBin Meng * This program is free software; you can redistribute it and/or modify it 7*9fe640a5SBin Meng * under the terms and conditions of the GNU General Public License, 8*9fe640a5SBin Meng * version 2 or later, as published by the Free Software Foundation. 9*9fe640a5SBin Meng * 10*9fe640a5SBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 11*9fe640a5SBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12*9fe640a5SBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13*9fe640a5SBin Meng * more details. 14*9fe640a5SBin Meng * 15*9fe640a5SBin Meng * You should have received a copy of the GNU General Public License along with 16*9fe640a5SBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 17*9fe640a5SBin Meng */ 18*9fe640a5SBin Meng 19*9fe640a5SBin Meng #ifndef HW_SIFIVE_U_PRCI_H 20*9fe640a5SBin Meng #define HW_SIFIVE_U_PRCI_H 21*9fe640a5SBin Meng 22*9fe640a5SBin Meng #define SIFIVE_U_PRCI_HFXOSCCFG 0x00 23*9fe640a5SBin Meng #define SIFIVE_U_PRCI_COREPLLCFG0 0x04 24*9fe640a5SBin Meng #define SIFIVE_U_PRCI_DDRPLLCFG0 0x0C 25*9fe640a5SBin Meng #define SIFIVE_U_PRCI_DDRPLLCFG1 0x10 26*9fe640a5SBin Meng #define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C 27*9fe640a5SBin Meng #define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20 28*9fe640a5SBin Meng #define SIFIVE_U_PRCI_CORECLKSEL 0x24 29*9fe640a5SBin Meng #define SIFIVE_U_PRCI_DEVICESRESET 0x28 30*9fe640a5SBin Meng #define SIFIVE_U_PRCI_CLKMUXSTATUS 0x2C 31*9fe640a5SBin Meng 32*9fe640a5SBin Meng /* 33*9fe640a5SBin Meng * Current FU540-C000 manual says ready bit is at bit 29, but 34*9fe640a5SBin Meng * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31. 35*9fe640a5SBin Meng * We have to trust the actual code that works. 36*9fe640a5SBin Meng * 37*9fe640a5SBin Meng * see https://github.com/sifive/freedom-u540-c000-bootloader 38*9fe640a5SBin Meng */ 39*9fe640a5SBin Meng 40*9fe640a5SBin Meng #define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30) 41*9fe640a5SBin Meng #define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31) 42*9fe640a5SBin Meng 43*9fe640a5SBin Meng /* xxxPLLCFG0 register bits */ 44*9fe640a5SBin Meng #define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0) 45*9fe640a5SBin Meng #define SIFIVE_U_PRCI_PLLCFG0_DIVF (31 << 6) 46*9fe640a5SBin Meng #define SIFIVE_U_PRCI_PLLCFG0_DIVQ (3 << 15) 47*9fe640a5SBin Meng #define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25) 48*9fe640a5SBin Meng #define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31) 49*9fe640a5SBin Meng 50*9fe640a5SBin Meng /* xxxPLLCFG1 register bits */ 51*9fe640a5SBin Meng #define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24) 52*9fe640a5SBin Meng 53*9fe640a5SBin Meng /* coreclksel register bits */ 54*9fe640a5SBin Meng #define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0) 55*9fe640a5SBin Meng 56*9fe640a5SBin Meng 57*9fe640a5SBin Meng #define SIFIVE_U_PRCI_REG_SIZE 0x1000 58*9fe640a5SBin Meng 59*9fe640a5SBin Meng #define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci" 60*9fe640a5SBin Meng 61*9fe640a5SBin Meng #define SIFIVE_U_PRCI(obj) \ 62*9fe640a5SBin Meng OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI) 63*9fe640a5SBin Meng 64*9fe640a5SBin Meng typedef struct SiFiveUPRCIState { 65*9fe640a5SBin Meng /*< private >*/ 66*9fe640a5SBin Meng SysBusDevice parent_obj; 67*9fe640a5SBin Meng 68*9fe640a5SBin Meng /*< public >*/ 69*9fe640a5SBin Meng MemoryRegion mmio; 70*9fe640a5SBin Meng uint32_t hfxosccfg; 71*9fe640a5SBin Meng uint32_t corepllcfg0; 72*9fe640a5SBin Meng uint32_t ddrpllcfg0; 73*9fe640a5SBin Meng uint32_t ddrpllcfg1; 74*9fe640a5SBin Meng uint32_t gemgxlpllcfg0; 75*9fe640a5SBin Meng uint32_t gemgxlpllcfg1; 76*9fe640a5SBin Meng uint32_t coreclksel; 77*9fe640a5SBin Meng uint32_t devicesreset; 78*9fe640a5SBin Meng uint32_t clkmuxstatus; 79*9fe640a5SBin Meng } SiFiveUPRCIState; 80*9fe640a5SBin Meng 81*9fe640a5SBin Meng /* 82*9fe640a5SBin Meng * Clock indexes for use by Device Tree data and the PRCI driver. 83*9fe640a5SBin Meng * 84*9fe640a5SBin Meng * These values are from sifive-fu540-prci.h in the Linux kernel. 85*9fe640a5SBin Meng */ 86*9fe640a5SBin Meng #define PRCI_CLK_COREPLL 0 87*9fe640a5SBin Meng #define PRCI_CLK_DDRPLL 1 88*9fe640a5SBin Meng #define PRCI_CLK_GEMGXLPLL 2 89*9fe640a5SBin Meng #define PRCI_CLK_TLCLK 3 90*9fe640a5SBin Meng 91*9fe640a5SBin Meng #endif /* HW_SIFIVE_U_PRCI_H */ 92