1506af233SHao Wu /* 2d9ffb75fSHao Wu * Nuvoton NPCM7xx/8xx System Global Control Registers. 3506af233SHao Wu * 4506af233SHao Wu * Copyright 2020 Google LLC 5506af233SHao Wu * 6506af233SHao Wu * This program is free software; you can redistribute it and/or modify it 7506af233SHao Wu * under the terms of the GNU General Public License as published by the 8506af233SHao Wu * Free Software Foundation; either version 2 of the License, or 9506af233SHao Wu * (at your option) any later version. 10506af233SHao Wu * 11506af233SHao Wu * This program is distributed in the hope that it will be useful, but WITHOUT 12506af233SHao Wu * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13506af233SHao Wu * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14506af233SHao Wu * for more details. 15506af233SHao Wu */ 16506af233SHao Wu #ifndef NPCM_GCR_H 17506af233SHao Wu #define NPCM_GCR_H 18506af233SHao Wu 19506af233SHao Wu #include "exec/memory.h" 20506af233SHao Wu #include "hw/sysbus.h" 218ca2021bSHao Wu #include "qom/object.h" 22506af233SHao Wu 23506af233SHao Wu /* 24506af233SHao Wu * NPCM7XX PWRON STRAP bit fields 25506af233SHao Wu * 12: SPI0 powered by VSBV3 at 1.8V 26506af233SHao Wu * 11: System flash attached to BMC 27506af233SHao Wu * 10: BSP alternative pins. 28506af233SHao Wu * 9:8: Flash UART command route enabled. 29506af233SHao Wu * 7: Security enabled. 30506af233SHao Wu * 6: HI-Z state control. 31506af233SHao Wu * 5: ECC disabled. 32506af233SHao Wu * 4: Reserved 33506af233SHao Wu * 3: JTAG2 enabled. 34506af233SHao Wu * 2:0: CPU and DRAM clock frequency. 35506af233SHao Wu */ 36506af233SHao Wu #define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12) 37506af233SHao Wu #define NPCM7XX_PWRON_STRAP_SFAB BIT(11) 38506af233SHao Wu #define NPCM7XX_PWRON_STRAP_BSPA BIT(10) 39506af233SHao Wu #define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8) 40506af233SHao Wu #define FUP_NORM_UART2 3 41506af233SHao Wu #define FUP_PROG_UART3 2 42506af233SHao Wu #define FUP_PROG_UART2 1 43506af233SHao Wu #define FUP_NORM_UART3 0 44506af233SHao Wu #define NPCM7XX_PWRON_STRAP_SECEN BIT(7) 45506af233SHao Wu #define NPCM7XX_PWRON_STRAP_HIZ BIT(6) 46506af233SHao Wu #define NPCM7XX_PWRON_STRAP_ECC BIT(5) 47506af233SHao Wu #define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4) 48506af233SHao Wu #define NPCM7XX_PWRON_STRAP_J2EN BIT(3) 49506af233SHao Wu #define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x) 50506af233SHao Wu #define CKFRQ_SKIPINIT 0x000 51506af233SHao Wu #define CKFRQ_DEFAULT 0x111 52506af233SHao Wu 53506af233SHao Wu /* 54506af233SHao Wu * Number of registers in our device state structure. Don't change this without 55506af233SHao Wu * incrementing the version_id in the vmstate. 56506af233SHao Wu */ 57d9ffb75fSHao Wu #define NPCM_GCR_MAX_NR_REGS NPCM8XX_GCR_NR_REGS 58506af233SHao Wu #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t)) 59d9ffb75fSHao Wu #define NPCM8XX_GCR_NR_REGS (0xf80 / sizeof(uint32_t)) 60506af233SHao Wu 61c99064e6SHao Wu typedef struct NPCMGCRState { 62506af233SHao Wu SysBusDevice parent; 63506af233SHao Wu 64506af233SHao Wu MemoryRegion iomem; 65506af233SHao Wu 668ca2021bSHao Wu uint32_t regs[NPCM_GCR_MAX_NR_REGS]; 67506af233SHao Wu 68506af233SHao Wu uint32_t reset_pwron; 69506af233SHao Wu uint32_t reset_mdlr; 70506af233SHao Wu uint32_t reset_intcr3; 71*0ad46bbbSHao Wu uint32_t reset_scrpad_b; 72c99064e6SHao Wu } NPCMGCRState; 73506af233SHao Wu 748ca2021bSHao Wu typedef struct NPCMGCRClass { 758ca2021bSHao Wu SysBusDeviceClass parent; 768ca2021bSHao Wu 778ca2021bSHao Wu size_t nr_regs; 788ca2021bSHao Wu const uint32_t *cold_reset_values; 798ca2021bSHao Wu } NPCMGCRClass; 808ca2021bSHao Wu 81c99064e6SHao Wu #define TYPE_NPCM_GCR "npcm-gcr" 82506af233SHao Wu #define TYPE_NPCM7XX_GCR "npcm7xx-gcr" 83d9ffb75fSHao Wu #define TYPE_NPCM8XX_GCR "npcm8xx-gcr" 848ca2021bSHao Wu OBJECT_DECLARE_TYPE(NPCMGCRState, NPCMGCRClass, NPCM_GCR) 85506af233SHao Wu 86506af233SHao Wu #endif /* NPCM_GCR_H */ 87