1c2da8a8bSCédric Le Goater /* 2c2da8a8bSCédric Le Goater * ASPEED SDRAM Memory Controller 3c2da8a8bSCédric Le Goater * 4c2da8a8bSCédric Le Goater * Copyright (C) 2016 IBM Corp. 5c2da8a8bSCédric Le Goater * 6c2da8a8bSCédric Le Goater * This code is licensed under the GPL version 2 or later. See the 7c2da8a8bSCédric Le Goater * COPYING file in the top-level directory. 8c2da8a8bSCédric Le Goater */ 9c2da8a8bSCédric Le Goater #ifndef ASPEED_SDMC_H 10c2da8a8bSCédric Le Goater #define ASPEED_SDMC_H 11c2da8a8bSCédric Le Goater 12c2da8a8bSCédric Le Goater #include "hw/sysbus.h" 13db1015e9SEduardo Habkost #include "qom/object.h" 14c2da8a8bSCédric Le Goater 15c2da8a8bSCédric Le Goater #define TYPE_ASPEED_SDMC "aspeed.sdmc" 16a489d195SEduardo Habkost OBJECT_DECLARE_TYPE(AspeedSDMCState, AspeedSDMCClass, ASPEED_SDMC) 178e00d1a9SCédric Le Goater #define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400" 188e00d1a9SCédric Le Goater #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500" 191550d726SJoel Stanley #define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600" 20*3347b9a1SJamin Lin #define TYPE_ASPEED_2700_SDMC TYPE_ASPEED_SDMC "-ast2700" 21c2da8a8bSCédric Le Goater 2214c17954SJoel Stanley /* 2314c17954SJoel Stanley * SDMC has 174 documented registers. In addition the u-boot device tree 2414c17954SJoel Stanley * describes the following regions: 2514c17954SJoel Stanley * - PHY status regs at offset 0x400, length 0x200 2614c17954SJoel Stanley * - PHY setting regs at offset 0x100, length 0x300 2714c17954SJoel Stanley * 2814c17954SJoel Stanley * There are two sets of MRS (Mode Registers) configuration in ast2600 memory 2914c17954SJoel Stanley * system: one is in the SDRAM MC (memory controller) which is used in run 3014c17954SJoel Stanley * time, and the other is in the DDR-PHY IP which is used during DDR-PHY 3114c17954SJoel Stanley * training. 3214c17954SJoel Stanley */ 33*3347b9a1SJamin Lin #define ASPEED_SDMC_NR_REGS (0x1000 >> 2) 34c2da8a8bSCédric Le Goater 35db1015e9SEduardo Habkost struct AspeedSDMCState { 36c2da8a8bSCédric Le Goater /*< private >*/ 37c2da8a8bSCédric Le Goater SysBusDevice parent_obj; 38c2da8a8bSCédric Le Goater 39c2da8a8bSCédric Le Goater /*< public >*/ 40c2da8a8bSCédric Le Goater MemoryRegion iomem; 41c2da8a8bSCédric Le Goater 42c2da8a8bSCédric Le Goater uint32_t regs[ASPEED_SDMC_NR_REGS]; 43c6c7cfb0SCédric Le Goater uint64_t ram_size; 44ebe31c0aSCédric Le Goater uint64_t max_ram_size; 45*3347b9a1SJamin Lin bool unlocked; 46db1015e9SEduardo Habkost }; 47c2da8a8bSCédric Le Goater 488e00d1a9SCédric Le Goater 49db1015e9SEduardo Habkost struct AspeedSDMCClass { 508e00d1a9SCédric Le Goater SysBusDeviceClass parent_class; 518e00d1a9SCédric Le Goater 528e00d1a9SCédric Le Goater uint64_t max_ram_size; 53533eb415SIgor Mammedov const uint64_t *valid_ram_sizes; 548e00d1a9SCédric Le Goater uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data); 558e00d1a9SCédric Le Goater void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data); 56*3347b9a1SJamin Lin bool is_bus64bit; 57db1015e9SEduardo Habkost }; 588e00d1a9SCédric Le Goater 59c2da8a8bSCédric Le Goater #endif /* ASPEED_SDMC_H */ 60