1*edd3a59dSStrahinja Jankovic /* 2*edd3a59dSStrahinja Jankovic * Allwinner A10 DRAM Controller emulation 3*edd3a59dSStrahinja Jankovic * 4*edd3a59dSStrahinja Jankovic * Copyright (C) 2022 Strahinja Jankovic <strahinja.p.jankovic@gmail.com> 5*edd3a59dSStrahinja Jankovic * 6*edd3a59dSStrahinja Jankovic * This file is derived from Allwinner H3 DRAMC, 7*edd3a59dSStrahinja Jankovic * by Niek Linnenbank. 8*edd3a59dSStrahinja Jankovic * 9*edd3a59dSStrahinja Jankovic * This program is free software: you can redistribute it and/or modify 10*edd3a59dSStrahinja Jankovic * it under the terms of the GNU General Public License as published by 11*edd3a59dSStrahinja Jankovic * the Free Software Foundation, either version 2 of the License, or 12*edd3a59dSStrahinja Jankovic * (at your option) any later version. 13*edd3a59dSStrahinja Jankovic * 14*edd3a59dSStrahinja Jankovic * This program is distributed in the hope that it will be useful, 15*edd3a59dSStrahinja Jankovic * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*edd3a59dSStrahinja Jankovic * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*edd3a59dSStrahinja Jankovic * GNU General Public License for more details. 18*edd3a59dSStrahinja Jankovic * 19*edd3a59dSStrahinja Jankovic * You should have received a copy of the GNU General Public License 20*edd3a59dSStrahinja Jankovic * along with this program. If not, see <http://www.gnu.org/licenses/>. 21*edd3a59dSStrahinja Jankovic */ 22*edd3a59dSStrahinja Jankovic 23*edd3a59dSStrahinja Jankovic #ifndef HW_MISC_ALLWINNER_A10_DRAMC_H 24*edd3a59dSStrahinja Jankovic #define HW_MISC_ALLWINNER_A10_DRAMC_H 25*edd3a59dSStrahinja Jankovic 26*edd3a59dSStrahinja Jankovic #include "qom/object.h" 27*edd3a59dSStrahinja Jankovic #include "hw/sysbus.h" 28*edd3a59dSStrahinja Jankovic #include "hw/register.h" 29*edd3a59dSStrahinja Jankovic 30*edd3a59dSStrahinja Jankovic /** 31*edd3a59dSStrahinja Jankovic * @name Constants 32*edd3a59dSStrahinja Jankovic * @{ 33*edd3a59dSStrahinja Jankovic */ 34*edd3a59dSStrahinja Jankovic 35*edd3a59dSStrahinja Jankovic /** Size of register I/O address space used by DRAMC device */ 36*edd3a59dSStrahinja Jankovic #define AW_A10_DRAMC_IOSIZE (0x1000) 37*edd3a59dSStrahinja Jankovic 38*edd3a59dSStrahinja Jankovic /** Total number of known registers */ 39*edd3a59dSStrahinja Jankovic #define AW_A10_DRAMC_REGS_NUM (AW_A10_DRAMC_IOSIZE / sizeof(uint32_t)) 40*edd3a59dSStrahinja Jankovic 41*edd3a59dSStrahinja Jankovic /** @} */ 42*edd3a59dSStrahinja Jankovic 43*edd3a59dSStrahinja Jankovic /** 44*edd3a59dSStrahinja Jankovic * @name Object model 45*edd3a59dSStrahinja Jankovic * @{ 46*edd3a59dSStrahinja Jankovic */ 47*edd3a59dSStrahinja Jankovic 48*edd3a59dSStrahinja Jankovic #define TYPE_AW_A10_DRAMC "allwinner-a10-dramc" 49*edd3a59dSStrahinja Jankovic OBJECT_DECLARE_SIMPLE_TYPE(AwA10DramControllerState, AW_A10_DRAMC) 50*edd3a59dSStrahinja Jankovic 51*edd3a59dSStrahinja Jankovic /** @} */ 52*edd3a59dSStrahinja Jankovic 53*edd3a59dSStrahinja Jankovic /** 54*edd3a59dSStrahinja Jankovic * Allwinner A10 DRAMC object instance state. 55*edd3a59dSStrahinja Jankovic */ 56*edd3a59dSStrahinja Jankovic struct AwA10DramControllerState { 57*edd3a59dSStrahinja Jankovic /*< private >*/ 58*edd3a59dSStrahinja Jankovic SysBusDevice parent_obj; 59*edd3a59dSStrahinja Jankovic /*< public >*/ 60*edd3a59dSStrahinja Jankovic 61*edd3a59dSStrahinja Jankovic /** Maps I/O registers in physical memory */ 62*edd3a59dSStrahinja Jankovic MemoryRegion iomem; 63*edd3a59dSStrahinja Jankovic 64*edd3a59dSStrahinja Jankovic /** Array of hardware registers */ 65*edd3a59dSStrahinja Jankovic uint32_t regs[AW_A10_DRAMC_REGS_NUM]; 66*edd3a59dSStrahinja Jankovic }; 67*edd3a59dSStrahinja Jankovic 68*edd3a59dSStrahinja Jankovic #endif /* HW_MISC_ALLWINNER_A10_DRAMC_H */ 69