1*e78597ccSYoshinori Sato /* 2*e78597ccSYoshinori Sato * RX Interrupt Control Unit 3*e78597ccSYoshinori Sato * 4*e78597ccSYoshinori Sato * Copyright (c) 2019 Yoshinori Sato 5*e78597ccSYoshinori Sato * 6*e78597ccSYoshinori Sato * SPDX-License-Identifier: GPL-2.0-or-later 7*e78597ccSYoshinori Sato * 8*e78597ccSYoshinori Sato * This program is free software; you can redistribute it and/or modify it 9*e78597ccSYoshinori Sato * under the terms and conditions of the GNU General Public License, 10*e78597ccSYoshinori Sato * version 2 or later, as published by the Free Software Foundation. 11*e78597ccSYoshinori Sato * 12*e78597ccSYoshinori Sato * This program is distributed in the hope it will be useful, but WITHOUT 13*e78597ccSYoshinori Sato * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14*e78597ccSYoshinori Sato * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15*e78597ccSYoshinori Sato * more details. 16*e78597ccSYoshinori Sato * 17*e78597ccSYoshinori Sato * You should have received a copy of the GNU General Public License along with 18*e78597ccSYoshinori Sato * this program. If not, see <http://www.gnu.org/licenses/>. 19*e78597ccSYoshinori Sato */ 20*e78597ccSYoshinori Sato 21*e78597ccSYoshinori Sato #ifndef HW_INTC_RX_ICU_H 22*e78597ccSYoshinori Sato #define HW_INTC_RX_ICU_H 23*e78597ccSYoshinori Sato 24*e78597ccSYoshinori Sato #include "hw/sysbus.h" 25*e78597ccSYoshinori Sato 26*e78597ccSYoshinori Sato enum TRG_MODE { 27*e78597ccSYoshinori Sato TRG_LEVEL = 0, 28*e78597ccSYoshinori Sato TRG_NEDGE = 1, /* Falling */ 29*e78597ccSYoshinori Sato TRG_PEDGE = 2, /* Raising */ 30*e78597ccSYoshinori Sato TRG_BEDGE = 3, /* Both */ 31*e78597ccSYoshinori Sato }; 32*e78597ccSYoshinori Sato 33*e78597ccSYoshinori Sato struct IRQSource { 34*e78597ccSYoshinori Sato enum TRG_MODE sense; 35*e78597ccSYoshinori Sato int level; 36*e78597ccSYoshinori Sato }; 37*e78597ccSYoshinori Sato 38*e78597ccSYoshinori Sato enum { 39*e78597ccSYoshinori Sato /* Software interrupt request */ 40*e78597ccSYoshinori Sato SWI = 27, 41*e78597ccSYoshinori Sato NR_IRQS = 256 42*e78597ccSYoshinori Sato }; 43*e78597ccSYoshinori Sato 44*e78597ccSYoshinori Sato struct RXICUState { 45*e78597ccSYoshinori Sato /*< private >*/ 46*e78597ccSYoshinori Sato SysBusDevice parent_obj; 47*e78597ccSYoshinori Sato /*< public >*/ 48*e78597ccSYoshinori Sato 49*e78597ccSYoshinori Sato MemoryRegion memory; 50*e78597ccSYoshinori Sato struct IRQSource src[NR_IRQS]; 51*e78597ccSYoshinori Sato uint32_t nr_irqs; 52*e78597ccSYoshinori Sato uint8_t *map; 53*e78597ccSYoshinori Sato uint32_t nr_sense; 54*e78597ccSYoshinori Sato uint8_t *init_sense; 55*e78597ccSYoshinori Sato 56*e78597ccSYoshinori Sato uint8_t ir[NR_IRQS]; 57*e78597ccSYoshinori Sato uint8_t dtcer[NR_IRQS]; 58*e78597ccSYoshinori Sato uint8_t ier[NR_IRQS / 8]; 59*e78597ccSYoshinori Sato uint8_t ipr[142]; 60*e78597ccSYoshinori Sato uint8_t dmasr[4]; 61*e78597ccSYoshinori Sato uint16_t fir; 62*e78597ccSYoshinori Sato uint8_t nmisr; 63*e78597ccSYoshinori Sato uint8_t nmier; 64*e78597ccSYoshinori Sato uint8_t nmiclr; 65*e78597ccSYoshinori Sato uint8_t nmicr; 66*e78597ccSYoshinori Sato int16_t req_irq; 67*e78597ccSYoshinori Sato qemu_irq _irq; 68*e78597ccSYoshinori Sato qemu_irq _fir; 69*e78597ccSYoshinori Sato qemu_irq _swi; 70*e78597ccSYoshinori Sato }; 71*e78597ccSYoshinori Sato typedef struct RXICUState RXICUState; 72*e78597ccSYoshinori Sato 73*e78597ccSYoshinori Sato #define TYPE_RX_ICU "rx-icu" 74*e78597ccSYoshinori Sato #define RX_ICU(obj) OBJECT_CHECK(RXICUState, (obj), TYPE_RX_ICU) 75*e78597ccSYoshinori Sato 76*e78597ccSYoshinori Sato #endif /* RX_ICU_H */ 77