1deeca9cbSBibo Mao /* SPDX-License-Identifier: GPL-2.0-or-later */ 2deeca9cbSBibo Mao /* 3deeca9cbSBibo Mao * LoongArch 7A1000 I/O interrupt controller definitions 4deeca9cbSBibo Mao * Copyright (c) 2024 Loongson Technology Corporation Limited 5deeca9cbSBibo Mao */ 6deeca9cbSBibo Mao 7deeca9cbSBibo Mao #ifndef HW_LOONGARCH_PIC_COMMON_H 8deeca9cbSBibo Mao #define HW_LOONGARCH_PIC_COMMON_H 9deeca9cbSBibo Mao 10deeca9cbSBibo Mao #include "hw/pci-host/ls7a.h" 11deeca9cbSBibo Mao #include "hw/sysbus.h" 12deeca9cbSBibo Mao 13deeca9cbSBibo Mao #define PCH_PIC_INT_ID_VAL 0x7000000UL 14deeca9cbSBibo Mao #define PCH_PIC_INT_ID_VER 0x1UL 15deeca9cbSBibo Mao #define PCH_PIC_INT_ID_LO 0x00 16deeca9cbSBibo Mao #define PCH_PIC_INT_ID_HI 0x04 17deeca9cbSBibo Mao #define PCH_PIC_INT_MASK_LO 0x20 18deeca9cbSBibo Mao #define PCH_PIC_INT_MASK_HI 0x24 19deeca9cbSBibo Mao #define PCH_PIC_HTMSI_EN_LO 0x40 20deeca9cbSBibo Mao #define PCH_PIC_HTMSI_EN_HI 0x44 21deeca9cbSBibo Mao #define PCH_PIC_INT_EDGE_LO 0x60 22deeca9cbSBibo Mao #define PCH_PIC_INT_EDGE_HI 0x64 23deeca9cbSBibo Mao #define PCH_PIC_INT_CLEAR_LO 0x80 24deeca9cbSBibo Mao #define PCH_PIC_INT_CLEAR_HI 0x84 25deeca9cbSBibo Mao #define PCH_PIC_AUTO_CTRL0_LO 0xc0 26deeca9cbSBibo Mao #define PCH_PIC_AUTO_CTRL0_HI 0xc4 27deeca9cbSBibo Mao #define PCH_PIC_AUTO_CTRL1_LO 0xe0 28deeca9cbSBibo Mao #define PCH_PIC_AUTO_CTRL1_HI 0xe4 29deeca9cbSBibo Mao #define PCH_PIC_ROUTE_ENTRY_OFFSET 0x100 30deeca9cbSBibo Mao #define PCH_PIC_ROUTE_ENTRY_END 0x13f 31deeca9cbSBibo Mao #define PCH_PIC_HTMSI_VEC_OFFSET 0x200 32deeca9cbSBibo Mao #define PCH_PIC_HTMSI_VEC_END 0x23f 33deeca9cbSBibo Mao #define PCH_PIC_INT_STATUS_LO 0x3a0 34deeca9cbSBibo Mao #define PCH_PIC_INT_STATUS_HI 0x3a4 35deeca9cbSBibo Mao #define PCH_PIC_INT_POL_LO 0x3e0 36deeca9cbSBibo Mao #define PCH_PIC_INT_POL_HI 0x3e4 37deeca9cbSBibo Mao 38deeca9cbSBibo Mao #define STATUS_LO_START 0 39deeca9cbSBibo Mao #define STATUS_HI_START 0x4 40deeca9cbSBibo Mao #define POL_LO_START 0x40 41deeca9cbSBibo Mao #define POL_HI_START 0x44 42f58ac978SBibo Mao 438bf26a9eSBibo Mao #define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common" 448bf26a9eSBibo Mao OBJECT_DECLARE_TYPE(LoongArchPICCommonState, 458bf26a9eSBibo Mao LoongArchPICCommonClass, LOONGARCH_PIC_COMMON) 468bf26a9eSBibo Mao 47f58ac978SBibo Mao struct LoongArchPICCommonState { 48f58ac978SBibo Mao SysBusDevice parent_obj; 49f58ac978SBibo Mao 50f58ac978SBibo Mao qemu_irq parent_irq[64]; 51f58ac978SBibo Mao uint64_t int_mask; /* 0x020 interrupt mask register */ 52f58ac978SBibo Mao uint64_t htmsi_en; /* 0x040 1=msi */ 53f58ac978SBibo Mao uint64_t intedge; /* 0x060 edge=1 level=0 */ 54f58ac978SBibo Mao uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */ 55f58ac978SBibo Mao uint64_t auto_crtl0; /* 0x0c0 */ 56f58ac978SBibo Mao uint64_t auto_crtl1; /* 0x0e0 */ 57f58ac978SBibo Mao uint64_t last_intirr; /* edge detection */ 58f58ac978SBibo Mao uint64_t intirr; /* 0x380 interrupt request register */ 59f58ac978SBibo Mao uint64_t intisr; /* 0x3a0 interrupt service register */ 60f58ac978SBibo Mao /* 61f58ac978SBibo Mao * 0x3e0 interrupt level polarity selection 62f58ac978SBibo Mao * register 0 for high level trigger 63f58ac978SBibo Mao */ 64f58ac978SBibo Mao uint64_t int_polarity; 65f58ac978SBibo Mao 66f58ac978SBibo Mao uint8_t route_entry[64]; /* 0x100 - 0x138 */ 67f58ac978SBibo Mao uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */ 68f58ac978SBibo Mao 69f58ac978SBibo Mao MemoryRegion iomem32_low; 70f58ac978SBibo Mao MemoryRegion iomem32_high; 71f58ac978SBibo Mao MemoryRegion iomem8; 72f58ac978SBibo Mao unsigned int irq_num; 73f58ac978SBibo Mao }; 748bf26a9eSBibo Mao 758bf26a9eSBibo Mao struct LoongArchPICCommonClass { 768bf26a9eSBibo Mao SysBusDeviceClass parent_class; 778bf26a9eSBibo Mao 788bf26a9eSBibo Mao DeviceRealize parent_realize; 79*36d31cf8SBibo Mao int (*pre_save)(LoongArchPICCommonState *s); 80*36d31cf8SBibo Mao int (*post_load)(LoongArchPICCommonState *s, int version_id); 818bf26a9eSBibo Mao }; 82deeca9cbSBibo Mao #endif /* HW_LOONGARCH_PIC_COMMON_H */ 83