xref: /openbmc/qemu/include/hw/intc/armv7m_nvic.h (revision d2db1de6ff15aad4c8898a416c6d8f2d93ff0282)
1*d2db1de6SPeter Maydell /*
2*d2db1de6SPeter Maydell  * ARMv7M NVIC object
3*d2db1de6SPeter Maydell  *
4*d2db1de6SPeter Maydell  * Copyright (c) 2017 Linaro Ltd
5*d2db1de6SPeter Maydell  * Written by Peter Maydell <peter.maydell@linaro.org>
6*d2db1de6SPeter Maydell  *
7*d2db1de6SPeter Maydell  * This code is licensed under the GPL version 2 or later.
8*d2db1de6SPeter Maydell  */
9*d2db1de6SPeter Maydell 
10*d2db1de6SPeter Maydell #ifndef HW_ARM_ARMV7M_NVIC_H
11*d2db1de6SPeter Maydell #define HW_ARM_ARMV7M_NVIC_H
12*d2db1de6SPeter Maydell 
13*d2db1de6SPeter Maydell #include "target/arm/cpu.h"
14*d2db1de6SPeter Maydell #include "hw/sysbus.h"
15*d2db1de6SPeter Maydell #include "hw/timer/armv7m_systick.h"
16*d2db1de6SPeter Maydell 
17*d2db1de6SPeter Maydell #define TYPE_NVIC "armv7m_nvic"
18*d2db1de6SPeter Maydell 
19*d2db1de6SPeter Maydell #define NVIC(obj) \
20*d2db1de6SPeter Maydell     OBJECT_CHECK(NVICState, (obj), TYPE_NVIC)
21*d2db1de6SPeter Maydell 
22*d2db1de6SPeter Maydell /* Highest permitted number of exceptions (architectural limit) */
23*d2db1de6SPeter Maydell #define NVIC_MAX_VECTORS 512
24*d2db1de6SPeter Maydell 
25*d2db1de6SPeter Maydell typedef struct VecInfo {
26*d2db1de6SPeter Maydell     /* Exception priorities can range from -3 to 255; only the unmodifiable
27*d2db1de6SPeter Maydell      * priority values for RESET, NMI and HardFault can be negative.
28*d2db1de6SPeter Maydell      */
29*d2db1de6SPeter Maydell     int16_t prio;
30*d2db1de6SPeter Maydell     uint8_t enabled;
31*d2db1de6SPeter Maydell     uint8_t pending;
32*d2db1de6SPeter Maydell     uint8_t active;
33*d2db1de6SPeter Maydell     uint8_t level; /* exceptions <=15 never set level */
34*d2db1de6SPeter Maydell } VecInfo;
35*d2db1de6SPeter Maydell 
36*d2db1de6SPeter Maydell typedef struct NVICState {
37*d2db1de6SPeter Maydell     /*< private >*/
38*d2db1de6SPeter Maydell     SysBusDevice parent_obj;
39*d2db1de6SPeter Maydell     /*< public >*/
40*d2db1de6SPeter Maydell 
41*d2db1de6SPeter Maydell     ARMCPU *cpu;
42*d2db1de6SPeter Maydell 
43*d2db1de6SPeter Maydell     VecInfo vectors[NVIC_MAX_VECTORS];
44*d2db1de6SPeter Maydell     uint32_t prigroup;
45*d2db1de6SPeter Maydell 
46*d2db1de6SPeter Maydell     /* vectpending and exception_prio are both cached state that can
47*d2db1de6SPeter Maydell      * be recalculated from the vectors[] array and the prigroup field.
48*d2db1de6SPeter Maydell      */
49*d2db1de6SPeter Maydell     unsigned int vectpending; /* highest prio pending enabled exception */
50*d2db1de6SPeter Maydell     int exception_prio; /* group prio of the highest prio active exception */
51*d2db1de6SPeter Maydell 
52*d2db1de6SPeter Maydell     MemoryRegion sysregmem;
53*d2db1de6SPeter Maydell     MemoryRegion container;
54*d2db1de6SPeter Maydell 
55*d2db1de6SPeter Maydell     uint32_t num_irq;
56*d2db1de6SPeter Maydell     qemu_irq excpout;
57*d2db1de6SPeter Maydell     qemu_irq sysresetreq;
58*d2db1de6SPeter Maydell 
59*d2db1de6SPeter Maydell     SysTickState systick;
60*d2db1de6SPeter Maydell } NVICState;
61*d2db1de6SPeter Maydell 
62*d2db1de6SPeter Maydell #endif
63