1d2db1de6SPeter Maydell /* 2d2db1de6SPeter Maydell * ARMv7M NVIC object 3d2db1de6SPeter Maydell * 4d2db1de6SPeter Maydell * Copyright (c) 2017 Linaro Ltd 5d2db1de6SPeter Maydell * Written by Peter Maydell <peter.maydell@linaro.org> 6d2db1de6SPeter Maydell * 7d2db1de6SPeter Maydell * This code is licensed under the GPL version 2 or later. 8d2db1de6SPeter Maydell */ 9d2db1de6SPeter Maydell 10d2db1de6SPeter Maydell #ifndef HW_ARM_ARMV7M_NVIC_H 11d2db1de6SPeter Maydell #define HW_ARM_ARMV7M_NVIC_H 12d2db1de6SPeter Maydell 13d2db1de6SPeter Maydell #include "target/arm/cpu.h" 14d2db1de6SPeter Maydell #include "hw/sysbus.h" 15d2db1de6SPeter Maydell #include "hw/timer/armv7m_systick.h" 16d2db1de6SPeter Maydell 17d2db1de6SPeter Maydell #define TYPE_NVIC "armv7m_nvic" 18d2db1de6SPeter Maydell 19d2db1de6SPeter Maydell #define NVIC(obj) \ 20d2db1de6SPeter Maydell OBJECT_CHECK(NVICState, (obj), TYPE_NVIC) 21d2db1de6SPeter Maydell 22d2db1de6SPeter Maydell /* Highest permitted number of exceptions (architectural limit) */ 23d2db1de6SPeter Maydell #define NVIC_MAX_VECTORS 512 24*17906a16SPeter Maydell /* Number of internal exceptions */ 25*17906a16SPeter Maydell #define NVIC_INTERNAL_VECTORS 16 26d2db1de6SPeter Maydell 27d2db1de6SPeter Maydell typedef struct VecInfo { 28d2db1de6SPeter Maydell /* Exception priorities can range from -3 to 255; only the unmodifiable 29d2db1de6SPeter Maydell * priority values for RESET, NMI and HardFault can be negative. 30d2db1de6SPeter Maydell */ 31d2db1de6SPeter Maydell int16_t prio; 32d2db1de6SPeter Maydell uint8_t enabled; 33d2db1de6SPeter Maydell uint8_t pending; 34d2db1de6SPeter Maydell uint8_t active; 35d2db1de6SPeter Maydell uint8_t level; /* exceptions <=15 never set level */ 36d2db1de6SPeter Maydell } VecInfo; 37d2db1de6SPeter Maydell 38d2db1de6SPeter Maydell typedef struct NVICState { 39d2db1de6SPeter Maydell /*< private >*/ 40d2db1de6SPeter Maydell SysBusDevice parent_obj; 41d2db1de6SPeter Maydell /*< public >*/ 42d2db1de6SPeter Maydell 43d2db1de6SPeter Maydell ARMCPU *cpu; 44d2db1de6SPeter Maydell 45d2db1de6SPeter Maydell VecInfo vectors[NVIC_MAX_VECTORS]; 46*17906a16SPeter Maydell /* If the v8M security extension is implemented, some of the internal 47*17906a16SPeter Maydell * exceptions are banked between security states (ie there exists both 48*17906a16SPeter Maydell * a Secure and a NonSecure version of the exception and its state): 49*17906a16SPeter Maydell * HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV) 50*17906a16SPeter Maydell * The rest (including all the external exceptions) are not banked, though 51*17906a16SPeter Maydell * they may be configurable to target either Secure or NonSecure state. 52*17906a16SPeter Maydell * We store the secure exception state in sec_vectors[] for the banked 53*17906a16SPeter Maydell * exceptions, and otherwise use only vectors[] (including for exceptions 54*17906a16SPeter Maydell * like SecureFault that unconditionally target Secure state). 55*17906a16SPeter Maydell * Entries in sec_vectors[] for non-banked exception numbers are unused. 56*17906a16SPeter Maydell */ 57*17906a16SPeter Maydell VecInfo sec_vectors[NVIC_INTERNAL_VECTORS]; 58d2db1de6SPeter Maydell uint32_t prigroup; 59d2db1de6SPeter Maydell 60d2db1de6SPeter Maydell /* vectpending and exception_prio are both cached state that can 61d2db1de6SPeter Maydell * be recalculated from the vectors[] array and the prigroup field. 62d2db1de6SPeter Maydell */ 63d2db1de6SPeter Maydell unsigned int vectpending; /* highest prio pending enabled exception */ 64d2db1de6SPeter Maydell int exception_prio; /* group prio of the highest prio active exception */ 65d2db1de6SPeter Maydell 66d2db1de6SPeter Maydell MemoryRegion sysregmem; 67f104919dSPeter Maydell MemoryRegion sysreg_ns_mem; 68d2db1de6SPeter Maydell MemoryRegion container; 69d2db1de6SPeter Maydell 70d2db1de6SPeter Maydell uint32_t num_irq; 71d2db1de6SPeter Maydell qemu_irq excpout; 72d2db1de6SPeter Maydell qemu_irq sysresetreq; 73d2db1de6SPeter Maydell 74d2db1de6SPeter Maydell SysTickState systick; 75d2db1de6SPeter Maydell } NVICState; 76d2db1de6SPeter Maydell 77d2db1de6SPeter Maydell #endif 78