1*c3931ee8Sliguang #ifndef AW_A10_PIC_H 2*c3931ee8Sliguang #define AW_A10_PIC_H 3*c3931ee8Sliguang 4*c3931ee8Sliguang #define TYPE_AW_A10_PIC "allwinner-a10-pic" 5*c3931ee8Sliguang #define AW_A10_PIC(obj) OBJECT_CHECK(AwA10PICState, (obj), TYPE_AW_A10_PIC) 6*c3931ee8Sliguang 7*c3931ee8Sliguang #define AW_A10_PIC_VECTOR 0 8*c3931ee8Sliguang #define AW_A10_PIC_BASE_ADDR 4 9*c3931ee8Sliguang #define AW_A10_PIC_PROTECT 8 10*c3931ee8Sliguang #define AW_A10_PIC_NMI 0xc 11*c3931ee8Sliguang #define AW_A10_PIC_IRQ_PENDING 0x10 12*c3931ee8Sliguang #define AW_A10_PIC_FIQ_PENDING 0x20 13*c3931ee8Sliguang #define AW_A10_PIC_SELECT 0x30 14*c3931ee8Sliguang #define AW_A10_PIC_ENABLE 0x40 15*c3931ee8Sliguang #define AW_A10_PIC_MASK 0x50 16*c3931ee8Sliguang 17*c3931ee8Sliguang #define AW_A10_PIC_INT_NR 95 18*c3931ee8Sliguang #define AW_A10_PIC_REG_NUM DIV_ROUND_UP(AW_A10_PIC_INT_NR, 32) 19*c3931ee8Sliguang 20*c3931ee8Sliguang typedef struct AwA10PICState { 21*c3931ee8Sliguang /*< private >*/ 22*c3931ee8Sliguang SysBusDevice parent_obj; 23*c3931ee8Sliguang /*< public >*/ 24*c3931ee8Sliguang MemoryRegion iomem; 25*c3931ee8Sliguang qemu_irq parent_fiq; 26*c3931ee8Sliguang qemu_irq parent_irq; 27*c3931ee8Sliguang 28*c3931ee8Sliguang uint32_t vector; 29*c3931ee8Sliguang uint32_t base_addr; 30*c3931ee8Sliguang uint32_t protect; 31*c3931ee8Sliguang uint32_t nmi; 32*c3931ee8Sliguang uint32_t irq_pending[AW_A10_PIC_REG_NUM]; 33*c3931ee8Sliguang uint32_t fiq_pending[AW_A10_PIC_REG_NUM]; 34*c3931ee8Sliguang uint32_t select[AW_A10_PIC_REG_NUM]; 35*c3931ee8Sliguang uint32_t enable[AW_A10_PIC_REG_NUM]; 36*c3931ee8Sliguang uint32_t mask[AW_A10_PIC_REG_NUM]; 37*c3931ee8Sliguang /*priority setting here*/ 38*c3931ee8Sliguang } AwA10PICState; 39*c3931ee8Sliguang 40*c3931ee8Sliguang #endif 41