1*121d0712SMarkus Armbruster #ifndef ALLWINNER_A10_PIC_H 2*121d0712SMarkus Armbruster #define ALLWINNER_A10_PIC_H 3c3931ee8Sliguang 4c3931ee8Sliguang #define TYPE_AW_A10_PIC "allwinner-a10-pic" 5c3931ee8Sliguang #define AW_A10_PIC(obj) OBJECT_CHECK(AwA10PICState, (obj), TYPE_AW_A10_PIC) 6c3931ee8Sliguang 7c3931ee8Sliguang #define AW_A10_PIC_VECTOR 0 8c3931ee8Sliguang #define AW_A10_PIC_BASE_ADDR 4 9c3931ee8Sliguang #define AW_A10_PIC_PROTECT 8 10c3931ee8Sliguang #define AW_A10_PIC_NMI 0xc 11c3931ee8Sliguang #define AW_A10_PIC_IRQ_PENDING 0x10 12c3931ee8Sliguang #define AW_A10_PIC_FIQ_PENDING 0x20 13c3931ee8Sliguang #define AW_A10_PIC_SELECT 0x30 14c3931ee8Sliguang #define AW_A10_PIC_ENABLE 0x40 15c3931ee8Sliguang #define AW_A10_PIC_MASK 0x50 16c3931ee8Sliguang 17c3931ee8Sliguang #define AW_A10_PIC_INT_NR 95 18c3931ee8Sliguang #define AW_A10_PIC_REG_NUM DIV_ROUND_UP(AW_A10_PIC_INT_NR, 32) 19c3931ee8Sliguang 20c3931ee8Sliguang typedef struct AwA10PICState { 21c3931ee8Sliguang /*< private >*/ 22c3931ee8Sliguang SysBusDevice parent_obj; 23c3931ee8Sliguang /*< public >*/ 24c3931ee8Sliguang MemoryRegion iomem; 25c3931ee8Sliguang qemu_irq parent_fiq; 26c3931ee8Sliguang qemu_irq parent_irq; 27c3931ee8Sliguang 28c3931ee8Sliguang uint32_t vector; 29c3931ee8Sliguang uint32_t base_addr; 30c3931ee8Sliguang uint32_t protect; 31c3931ee8Sliguang uint32_t nmi; 32c3931ee8Sliguang uint32_t irq_pending[AW_A10_PIC_REG_NUM]; 33c3931ee8Sliguang uint32_t fiq_pending[AW_A10_PIC_REG_NUM]; 34c3931ee8Sliguang uint32_t select[AW_A10_PIC_REG_NUM]; 35c3931ee8Sliguang uint32_t enable[AW_A10_PIC_REG_NUM]; 36c3931ee8Sliguang uint32_t mask[AW_A10_PIC_REG_NUM]; 37c3931ee8Sliguang /*priority setting here*/ 38c3931ee8Sliguang } AwA10PICState; 39c3931ee8Sliguang 40c3931ee8Sliguang #endif 41