1121d0712SMarkus Armbruster #ifndef ALLWINNER_A10_PIC_H 2121d0712SMarkus Armbruster #define ALLWINNER_A10_PIC_H 3c3931ee8Sliguang 4ec150c7eSMarkus Armbruster #include "hw/sysbus.h" 5db1015e9SEduardo Habkost #include "qom/object.h" 6ec150c7eSMarkus Armbruster 7c3931ee8Sliguang #define TYPE_AW_A10_PIC "allwinner-a10-pic" 8*8063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(AwA10PICState, AW_A10_PIC) 9c3931ee8Sliguang 10c3931ee8Sliguang #define AW_A10_PIC_VECTOR 0 11c3931ee8Sliguang #define AW_A10_PIC_BASE_ADDR 4 12c3931ee8Sliguang #define AW_A10_PIC_PROTECT 8 13c3931ee8Sliguang #define AW_A10_PIC_NMI 0xc 14c3931ee8Sliguang #define AW_A10_PIC_IRQ_PENDING 0x10 15c3931ee8Sliguang #define AW_A10_PIC_FIQ_PENDING 0x20 16c3931ee8Sliguang #define AW_A10_PIC_SELECT 0x30 17c3931ee8Sliguang #define AW_A10_PIC_ENABLE 0x40 18c3931ee8Sliguang #define AW_A10_PIC_MASK 0x50 19c3931ee8Sliguang 20c3931ee8Sliguang #define AW_A10_PIC_INT_NR 95 21c3931ee8Sliguang #define AW_A10_PIC_REG_NUM DIV_ROUND_UP(AW_A10_PIC_INT_NR, 32) 22c3931ee8Sliguang 23db1015e9SEduardo Habkost struct AwA10PICState { 24c3931ee8Sliguang /*< private >*/ 25c3931ee8Sliguang SysBusDevice parent_obj; 26c3931ee8Sliguang /*< public >*/ 27c3931ee8Sliguang MemoryRegion iomem; 28c3931ee8Sliguang qemu_irq parent_fiq; 29c3931ee8Sliguang qemu_irq parent_irq; 30c3931ee8Sliguang 31c3931ee8Sliguang uint32_t vector; 32c3931ee8Sliguang uint32_t base_addr; 33c3931ee8Sliguang uint32_t protect; 34c3931ee8Sliguang uint32_t nmi; 35c3931ee8Sliguang uint32_t irq_pending[AW_A10_PIC_REG_NUM]; 36c3931ee8Sliguang uint32_t fiq_pending[AW_A10_PIC_REG_NUM]; 37c3931ee8Sliguang uint32_t select[AW_A10_PIC_REG_NUM]; 38c3931ee8Sliguang uint32_t enable[AW_A10_PIC_REG_NUM]; 39c3931ee8Sliguang uint32_t mask[AW_A10_PIC_REG_NUM]; 40c3931ee8Sliguang /*priority setting here*/ 41db1015e9SEduardo Habkost }; 42c3931ee8Sliguang 43c3931ee8Sliguang #endif 44