1*4921a0ceSBin Meng /* 2*4921a0ceSBin Meng * SiFive System-on-Chip general purpose input/output register definition 3*4921a0ceSBin Meng * 4*4921a0ceSBin Meng * Copyright 2019 AdaCore 5*4921a0ceSBin Meng * 6*4921a0ceSBin Meng * Base on nrf51_gpio.c: 7*4921a0ceSBin Meng * 8*4921a0ceSBin Meng * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> 9*4921a0ceSBin Meng * 10*4921a0ceSBin Meng * This code is licensed under the GPL version 2 or later. See 11*4921a0ceSBin Meng * the COPYING file in the top-level directory. 12*4921a0ceSBin Meng */ 13*4921a0ceSBin Meng 14*4921a0ceSBin Meng #ifndef SIFIVE_GPIO_H 15*4921a0ceSBin Meng #define SIFIVE_GPIO_H 16*4921a0ceSBin Meng 17*4921a0ceSBin Meng #include "hw/sysbus.h" 18*4921a0ceSBin Meng 19*4921a0ceSBin Meng #define TYPE_SIFIVE_GPIO "sifive_soc.gpio" 20*4921a0ceSBin Meng #define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO) 21*4921a0ceSBin Meng 22*4921a0ceSBin Meng #define SIFIVE_GPIO_PINS 32 23*4921a0ceSBin Meng 24*4921a0ceSBin Meng #define SIFIVE_GPIO_SIZE 0x100 25*4921a0ceSBin Meng 26*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_VALUE 0x000 27*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_INPUT_EN 0x004 28*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_OUTPUT_EN 0x008 29*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_PORT 0x00C 30*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_PUE 0x010 31*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_DS 0x014 32*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_RISE_IE 0x018 33*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_RISE_IP 0x01C 34*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_FALL_IE 0x020 35*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_FALL_IP 0x024 36*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_HIGH_IE 0x028 37*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_HIGH_IP 0x02C 38*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_LOW_IE 0x030 39*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_LOW_IP 0x034 40*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_IOF_EN 0x038 41*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_IOF_SEL 0x03C 42*4921a0ceSBin Meng #define SIFIVE_GPIO_REG_OUT_XOR 0x040 43*4921a0ceSBin Meng 44*4921a0ceSBin Meng typedef struct SIFIVEGPIOState { 45*4921a0ceSBin Meng SysBusDevice parent_obj; 46*4921a0ceSBin Meng 47*4921a0ceSBin Meng MemoryRegion mmio; 48*4921a0ceSBin Meng 49*4921a0ceSBin Meng qemu_irq irq[SIFIVE_GPIO_PINS]; 50*4921a0ceSBin Meng qemu_irq output[SIFIVE_GPIO_PINS]; 51*4921a0ceSBin Meng 52*4921a0ceSBin Meng uint32_t value; /* Actual value of the pin */ 53*4921a0ceSBin Meng uint32_t input_en; 54*4921a0ceSBin Meng uint32_t output_en; 55*4921a0ceSBin Meng uint32_t port; /* Pin value requested by the user */ 56*4921a0ceSBin Meng uint32_t pue; 57*4921a0ceSBin Meng uint32_t ds; 58*4921a0ceSBin Meng uint32_t rise_ie; 59*4921a0ceSBin Meng uint32_t rise_ip; 60*4921a0ceSBin Meng uint32_t fall_ie; 61*4921a0ceSBin Meng uint32_t fall_ip; 62*4921a0ceSBin Meng uint32_t high_ie; 63*4921a0ceSBin Meng uint32_t high_ip; 64*4921a0ceSBin Meng uint32_t low_ie; 65*4921a0ceSBin Meng uint32_t low_ip; 66*4921a0ceSBin Meng uint32_t iof_en; 67*4921a0ceSBin Meng uint32_t iof_sel; 68*4921a0ceSBin Meng uint32_t out_xor; 69*4921a0ceSBin Meng uint32_t in; 70*4921a0ceSBin Meng uint32_t in_mask; 71*4921a0ceSBin Meng 72*4921a0ceSBin Meng /* config */ 73*4921a0ceSBin Meng uint32_t ngpio; 74*4921a0ceSBin Meng } SIFIVEGPIOState; 75*4921a0ceSBin Meng 76*4921a0ceSBin Meng #endif /* SIFIVE_GPIO_H */ 77