14921a0ceSBin Meng /* 24921a0ceSBin Meng * SiFive System-on-Chip general purpose input/output register definition 34921a0ceSBin Meng * 44921a0ceSBin Meng * Copyright 2019 AdaCore 54921a0ceSBin Meng * 64921a0ceSBin Meng * Base on nrf51_gpio.c: 74921a0ceSBin Meng * 84921a0ceSBin Meng * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> 94921a0ceSBin Meng * 104921a0ceSBin Meng * This code is licensed under the GPL version 2 or later. See 114921a0ceSBin Meng * the COPYING file in the top-level directory. 124921a0ceSBin Meng */ 134921a0ceSBin Meng 144921a0ceSBin Meng #ifndef SIFIVE_GPIO_H 154921a0ceSBin Meng #define SIFIVE_GPIO_H 164921a0ceSBin Meng 174921a0ceSBin Meng #include "hw/sysbus.h" 18ac900edeSEduardo Habkost #include "qom/object.h" 194921a0ceSBin Meng 204921a0ceSBin Meng #define TYPE_SIFIVE_GPIO "sifive_soc.gpio" 21ac900edeSEduardo Habkost typedef struct SIFIVEGPIOState SIFIVEGPIOState; 22*e38d3c5cSEduardo Habkost DECLARE_INSTANCE_CHECKER(SIFIVEGPIOState, SIFIVE_GPIO, 23*e38d3c5cSEduardo Habkost TYPE_SIFIVE_GPIO) 244921a0ceSBin Meng 254921a0ceSBin Meng #define SIFIVE_GPIO_PINS 32 264921a0ceSBin Meng 274921a0ceSBin Meng #define SIFIVE_GPIO_SIZE 0x100 284921a0ceSBin Meng 294921a0ceSBin Meng #define SIFIVE_GPIO_REG_VALUE 0x000 304921a0ceSBin Meng #define SIFIVE_GPIO_REG_INPUT_EN 0x004 314921a0ceSBin Meng #define SIFIVE_GPIO_REG_OUTPUT_EN 0x008 324921a0ceSBin Meng #define SIFIVE_GPIO_REG_PORT 0x00C 334921a0ceSBin Meng #define SIFIVE_GPIO_REG_PUE 0x010 344921a0ceSBin Meng #define SIFIVE_GPIO_REG_DS 0x014 354921a0ceSBin Meng #define SIFIVE_GPIO_REG_RISE_IE 0x018 364921a0ceSBin Meng #define SIFIVE_GPIO_REG_RISE_IP 0x01C 374921a0ceSBin Meng #define SIFIVE_GPIO_REG_FALL_IE 0x020 384921a0ceSBin Meng #define SIFIVE_GPIO_REG_FALL_IP 0x024 394921a0ceSBin Meng #define SIFIVE_GPIO_REG_HIGH_IE 0x028 404921a0ceSBin Meng #define SIFIVE_GPIO_REG_HIGH_IP 0x02C 414921a0ceSBin Meng #define SIFIVE_GPIO_REG_LOW_IE 0x030 424921a0ceSBin Meng #define SIFIVE_GPIO_REG_LOW_IP 0x034 434921a0ceSBin Meng #define SIFIVE_GPIO_REG_IOF_EN 0x038 444921a0ceSBin Meng #define SIFIVE_GPIO_REG_IOF_SEL 0x03C 454921a0ceSBin Meng #define SIFIVE_GPIO_REG_OUT_XOR 0x040 464921a0ceSBin Meng 47ac900edeSEduardo Habkost struct SIFIVEGPIOState { 484921a0ceSBin Meng SysBusDevice parent_obj; 494921a0ceSBin Meng 504921a0ceSBin Meng MemoryRegion mmio; 514921a0ceSBin Meng 524921a0ceSBin Meng qemu_irq irq[SIFIVE_GPIO_PINS]; 534921a0ceSBin Meng qemu_irq output[SIFIVE_GPIO_PINS]; 544921a0ceSBin Meng 554921a0ceSBin Meng uint32_t value; /* Actual value of the pin */ 564921a0ceSBin Meng uint32_t input_en; 574921a0ceSBin Meng uint32_t output_en; 584921a0ceSBin Meng uint32_t port; /* Pin value requested by the user */ 594921a0ceSBin Meng uint32_t pue; 604921a0ceSBin Meng uint32_t ds; 614921a0ceSBin Meng uint32_t rise_ie; 624921a0ceSBin Meng uint32_t rise_ip; 634921a0ceSBin Meng uint32_t fall_ie; 644921a0ceSBin Meng uint32_t fall_ip; 654921a0ceSBin Meng uint32_t high_ie; 664921a0ceSBin Meng uint32_t high_ip; 674921a0ceSBin Meng uint32_t low_ie; 684921a0ceSBin Meng uint32_t low_ip; 694921a0ceSBin Meng uint32_t iof_en; 704921a0ceSBin Meng uint32_t iof_sel; 714921a0ceSBin Meng uint32_t out_xor; 724921a0ceSBin Meng uint32_t in; 734921a0ceSBin Meng uint32_t in_mask; 744921a0ceSBin Meng 754921a0ceSBin Meng /* config */ 764921a0ceSBin Meng uint32_t ngpio; 77ac900edeSEduardo Habkost }; 784921a0ceSBin Meng 794921a0ceSBin Meng #endif /* SIFIVE_GPIO_H */ 80