1*526dbbe0SHavard Skinnemoen /* 2*526dbbe0SHavard Skinnemoen * Nuvoton NPCM7xx General Purpose Input / Output (GPIO) 3*526dbbe0SHavard Skinnemoen * 4*526dbbe0SHavard Skinnemoen * Copyright 2020 Google LLC 5*526dbbe0SHavard Skinnemoen * 6*526dbbe0SHavard Skinnemoen * This program is free software; you can redistribute it and/or 7*526dbbe0SHavard Skinnemoen * modify it under the terms of the GNU General Public License 8*526dbbe0SHavard Skinnemoen * version 2 as published by the Free Software Foundation. 9*526dbbe0SHavard Skinnemoen * 10*526dbbe0SHavard Skinnemoen * This program is distributed in the hope that it will be useful, 11*526dbbe0SHavard Skinnemoen * but WITHOUT ANY WARRANTY; without even the implied warranty of 12*526dbbe0SHavard Skinnemoen * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*526dbbe0SHavard Skinnemoen * GNU General Public License for more details. 14*526dbbe0SHavard Skinnemoen */ 15*526dbbe0SHavard Skinnemoen #ifndef NPCM7XX_GPIO_H 16*526dbbe0SHavard Skinnemoen #define NPCM7XX_GPIO_H 17*526dbbe0SHavard Skinnemoen 18*526dbbe0SHavard Skinnemoen #include "exec/memory.h" 19*526dbbe0SHavard Skinnemoen #include "hw/sysbus.h" 20*526dbbe0SHavard Skinnemoen 21*526dbbe0SHavard Skinnemoen /* Number of pins managed by each controller. */ 22*526dbbe0SHavard Skinnemoen #define NPCM7XX_GPIO_NR_PINS (32) 23*526dbbe0SHavard Skinnemoen 24*526dbbe0SHavard Skinnemoen /* 25*526dbbe0SHavard Skinnemoen * Number of registers in our device state structure. Don't change this without 26*526dbbe0SHavard Skinnemoen * incrementing the version_id in the vmstate. 27*526dbbe0SHavard Skinnemoen */ 28*526dbbe0SHavard Skinnemoen #define NPCM7XX_GPIO_NR_REGS (0x80 / sizeof(uint32_t)) 29*526dbbe0SHavard Skinnemoen 30*526dbbe0SHavard Skinnemoen typedef struct NPCM7xxGPIOState { 31*526dbbe0SHavard Skinnemoen SysBusDevice parent; 32*526dbbe0SHavard Skinnemoen 33*526dbbe0SHavard Skinnemoen /* Properties to be defined by the SoC */ 34*526dbbe0SHavard Skinnemoen uint32_t reset_pu; 35*526dbbe0SHavard Skinnemoen uint32_t reset_pd; 36*526dbbe0SHavard Skinnemoen uint32_t reset_osrc; 37*526dbbe0SHavard Skinnemoen uint32_t reset_odsc; 38*526dbbe0SHavard Skinnemoen 39*526dbbe0SHavard Skinnemoen MemoryRegion mmio; 40*526dbbe0SHavard Skinnemoen 41*526dbbe0SHavard Skinnemoen qemu_irq irq; 42*526dbbe0SHavard Skinnemoen qemu_irq output[NPCM7XX_GPIO_NR_PINS]; 43*526dbbe0SHavard Skinnemoen 44*526dbbe0SHavard Skinnemoen uint32_t pin_level; 45*526dbbe0SHavard Skinnemoen uint32_t ext_level; 46*526dbbe0SHavard Skinnemoen uint32_t ext_driven; 47*526dbbe0SHavard Skinnemoen 48*526dbbe0SHavard Skinnemoen uint32_t regs[NPCM7XX_GPIO_NR_REGS]; 49*526dbbe0SHavard Skinnemoen } NPCM7xxGPIOState; 50*526dbbe0SHavard Skinnemoen 51*526dbbe0SHavard Skinnemoen #define TYPE_NPCM7XX_GPIO "npcm7xx-gpio" 52*526dbbe0SHavard Skinnemoen #define NPCM7XX_GPIO(obj) \ 53*526dbbe0SHavard Skinnemoen OBJECT_CHECK(NPCM7xxGPIOState, (obj), TYPE_NPCM7XX_GPIO) 54*526dbbe0SHavard Skinnemoen 55*526dbbe0SHavard Skinnemoen #endif /* NPCM7XX_GPIO_H */ 56