1 /* 2 * QEMU CXL PCI interfaces 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_PCI_H 11 #define CXL_PCI_H 12 13 #include "qemu/compiler.h" 14 #include "hw/cxl/cxl_cdat.h" 15 16 #define CXL_VENDOR_ID 0x1e98 17 18 #define PCIE_DVSEC_HEADER1_OFFSET 0x4 /* Offset from start of extend cap */ 19 #define PCIE_DVSEC_ID_OFFSET 0x8 20 21 #define PCIE_CXL_DEVICE_DVSEC_LENGTH 0x38 22 #define PCIE_CXL1_DEVICE_DVSEC_REVID 0 23 #define PCIE_CXL2_DEVICE_DVSEC_REVID 1 24 25 #define EXTENSIONS_PORT_DVSEC_LENGTH 0x28 26 #define EXTENSIONS_PORT_DVSEC_REVID 0 27 28 #define GPF_PORT_DVSEC_LENGTH 0x10 29 #define GPF_PORT_DVSEC_REVID 0 30 31 #define GPF_DEVICE_DVSEC_LENGTH 0x10 32 #define GPF_DEVICE_DVSEC_REVID 0 33 34 #define PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0 0x14 35 #define PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0 1 36 37 #define REG_LOC_DVSEC_LENGTH 0x24 38 #define REG_LOC_DVSEC_REVID 0 39 40 enum { 41 PCIE_CXL_DEVICE_DVSEC = 0, 42 NON_CXL_FUNCTION_MAP_DVSEC = 2, 43 EXTENSIONS_PORT_DVSEC = 3, 44 GPF_PORT_DVSEC = 4, 45 GPF_DEVICE_DVSEC = 5, 46 PCIE_FLEXBUS_PORT_DVSEC = 7, 47 REG_LOC_DVSEC = 8, 48 MLD_DVSEC = 9, 49 CXL20_MAX_DVSEC 50 }; 51 52 typedef struct DVSECHeader { 53 uint32_t cap_hdr; 54 uint32_t dv_hdr1; 55 uint16_t dv_hdr2; 56 } QEMU_PACKED DVSECHeader; 57 QEMU_BUILD_BUG_ON(sizeof(DVSECHeader) != 10); 58 59 /* 60 * CXL 2.0 devices must implement certain DVSEC IDs, and can [optionally] 61 * implement others. 62 * 63 * CXL 2.0 Device: 0, [2], 5, 8 64 * CXL 2.0 RP: 3, 4, 7, 8 65 * CXL 2.0 Upstream Port: [2], 7, 8 66 * CXL 2.0 Downstream Port: 3, 4, 7, 8 67 */ 68 69 /* CXL 2.0 - 8.1.3 (ID 0001) */ 70 typedef struct CXLDVSECDevice { 71 DVSECHeader hdr; 72 uint16_t cap; 73 uint16_t ctrl; 74 uint16_t status; 75 uint16_t ctrl2; 76 uint16_t status2; 77 uint16_t lock; 78 uint16_t cap2; 79 uint32_t range1_size_hi; 80 uint32_t range1_size_lo; 81 uint32_t range1_base_hi; 82 uint32_t range1_base_lo; 83 uint32_t range2_size_hi; 84 uint32_t range2_size_lo; 85 uint32_t range2_base_hi; 86 uint32_t range2_base_lo; 87 } CXLDVSECDevice; 88 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice) != 0x38); 89 90 /* CXL 2.0 - 8.1.5 (ID 0003) */ 91 typedef struct CXLDVSECPortExtensions { 92 DVSECHeader hdr; 93 uint16_t status; 94 uint16_t control; 95 uint8_t alt_bus_base; 96 uint8_t alt_bus_limit; 97 uint16_t alt_memory_base; 98 uint16_t alt_memory_limit; 99 uint16_t alt_prefetch_base; 100 uint16_t alt_prefetch_limit; 101 uint32_t alt_prefetch_base_high; 102 uint32_t alt_prefetch_limit_high; 103 uint32_t rcrb_base; 104 uint32_t rcrb_base_high; 105 } CXLDVSECPortExtensions; 106 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExtensions) != 0x28); 107 108 #define PORT_CONTROL_OFFSET 0xc 109 #define PORT_CONTROL_UNMASK_SBR 1 110 #define PORT_CONTROL_ALT_MEMID_EN 4 111 112 /* CXL 2.0 - 8.1.6 GPF DVSEC (ID 0004) */ 113 typedef struct CXLDVSECPortGPF { 114 DVSECHeader hdr; 115 uint16_t rsvd; 116 uint16_t phase1_ctrl; 117 uint16_t phase2_ctrl; 118 } CXLDVSECPortGPF; 119 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortGPF) != 0x10); 120 121 /* CXL 2.0 - 8.1.7 GPF DVSEC for CXL Device */ 122 typedef struct CXLDVSECDeviceGPF { 123 DVSECHeader hdr; 124 uint16_t phase2_duration; 125 uint32_t phase2_power; 126 } CXLDVSECDeviceGPF; 127 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDeviceGPF) != 0x10); 128 129 /* CXL 2.0 - 8.1.8/8.2.1.3 Flex Bus DVSEC (ID 0007) */ 130 typedef struct CXLDVSECPortFlexBus { 131 DVSECHeader hdr; 132 uint16_t cap; 133 uint16_t ctrl; 134 uint16_t status; 135 uint32_t rcvd_mod_ts_data_phase1; 136 } CXLDVSECPortFlexBus; 137 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortFlexBus) != 0x14); 138 139 /* CXL 2.0 - 8.1.9 Register Locator DVSEC (ID 0008) */ 140 typedef struct CXLDVSECRegisterLocator { 141 DVSECHeader hdr; 142 uint16_t rsvd; 143 uint32_t reg0_base_lo; 144 uint32_t reg0_base_hi; 145 uint32_t reg1_base_lo; 146 uint32_t reg1_base_hi; 147 uint32_t reg2_base_lo; 148 uint32_t reg2_base_hi; 149 } CXLDVSECRegisterLocator; 150 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECRegisterLocator) != 0x24); 151 152 /* BAR Equivalence Indicator */ 153 #define BEI_BAR_10H 0 154 #define BEI_BAR_14H 1 155 #define BEI_BAR_18H 2 156 #define BEI_BAR_1cH 3 157 #define BEI_BAR_20H 4 158 #define BEI_BAR_24H 5 159 160 /* Register Block Identifier */ 161 #define RBI_EMPTY 0 162 #define RBI_COMPONENT_REG (1 << 8) 163 #define RBI_BAR_VIRT_ACL (2 << 8) 164 #define RBI_CXL_DEVICE_REG (3 << 8) 165 166 #endif 167