1 /* 2 * QEMU CXL Component 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_COMPONENT_H 11 #define CXL_COMPONENT_H 12 13 /* CXL 2.0 - 8.2.4 */ 14 #define CXL2_COMPONENT_IO_REGION_SIZE 0x1000 15 #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000 16 #define CXL2_COMPONENT_BLOCK_SIZE 0x10000 17 18 #include "qemu/range.h" 19 #include "hw/cxl/cxl_cdat.h" 20 #include "hw/register.h" 21 #include "qapi/error.h" 22 23 enum reg_type { 24 CXL2_DEVICE, 25 CXL2_TYPE3_DEVICE, 26 CXL2_LOGICAL_DEVICE, 27 CXL2_ROOT_PORT, 28 CXL2_UPSTREAM_PORT, 29 CXL2_DOWNSTREAM_PORT, 30 CXL3_SWITCH_MAILBOX_CCI, 31 }; 32 33 /* 34 * Capability registers are defined at the top of the CXL.cache/mem region and 35 * are packed. For our purposes we will always define the caps in the same 36 * order. 37 * CXL 2.0 - 8.2.5 Table 142 for details. 38 */ 39 40 /* CXL 2.0 - 8.2.5.1 */ 41 REG32(CXL_CAPABILITY_HEADER, 0) 42 FIELD(CXL_CAPABILITY_HEADER, ID, 0, 16) 43 FIELD(CXL_CAPABILITY_HEADER, VERSION, 16, 4) 44 FIELD(CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 20, 4) 45 FIELD(CXL_CAPABILITY_HEADER, ARRAY_SIZE, 24, 8) 46 47 #define CXLx_CAPABILITY_HEADER(type, offset) \ 48 REG32(CXL_##type##_CAPABILITY_HEADER, offset) \ 49 FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \ 50 FIELD(CXL_##type##_CAPABILITY_HEADER, VERSION, 16, 4) \ 51 FIELD(CXL_##type##_CAPABILITY_HEADER, PTR, 20, 12) 52 CXLx_CAPABILITY_HEADER(RAS, 0x4) 53 CXLx_CAPABILITY_HEADER(LINK, 0x8) 54 CXLx_CAPABILITY_HEADER(HDM, 0xc) 55 CXLx_CAPABILITY_HEADER(EXTSEC, 0x10) 56 CXLx_CAPABILITY_HEADER(SNOOP, 0x14) 57 58 /* 59 * Capability structures contain the actual registers that the CXL component 60 * implements. Some of these are specific to certain types of components, but 61 * this implementation leaves enough space regardless. 62 */ 63 /* 8.2.5.9 - CXL RAS Capability Structure */ 64 65 /* Give ample space for caps before this */ 66 #define CXL_RAS_REGISTERS_OFFSET 0x80 67 #define CXL_RAS_REGISTERS_SIZE 0x58 68 REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET) 69 #define CXL_RAS_UNC_ERR_CACHE_DATA_PARITY 0 70 #define CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY 1 71 #define CXL_RAS_UNC_ERR_CACHE_BE_PARITY 2 72 #define CXL_RAS_UNC_ERR_CACHE_DATA_ECC 3 73 #define CXL_RAS_UNC_ERR_MEM_DATA_PARITY 4 74 #define CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY 5 75 #define CXL_RAS_UNC_ERR_MEM_BE_PARITY 6 76 #define CXL_RAS_UNC_ERR_MEM_DATA_ECC 7 77 #define CXL_RAS_UNC_ERR_REINIT_THRESHOLD 8 78 #define CXL_RAS_UNC_ERR_RSVD_ENCODING 9 79 #define CXL_RAS_UNC_ERR_POISON_RECEIVED 10 80 #define CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW 11 81 #define CXL_RAS_UNC_ERR_INTERNAL 14 82 #define CXL_RAS_UNC_ERR_CXL_IDE_TX 15 83 #define CXL_RAS_UNC_ERR_CXL_IDE_RX 16 84 #define CXL_RAS_UNC_ERR_CXL_UNUSED 63 /* Magic value */ 85 REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4) 86 REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8) 87 REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc) 88 #define CXL_RAS_COR_ERR_CACHE_DATA_ECC 0 89 #define CXL_RAS_COR_ERR_MEM_DATA_ECC 1 90 #define CXL_RAS_COR_ERR_CRC_THRESHOLD 2 91 #define CXL_RAS_COR_ERR_RETRY_THRESHOLD 3 92 #define CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED 4 93 #define CXL_RAS_COR_ERR_MEM_POISON_RECEIVED 5 94 #define CXL_RAS_COR_ERR_PHYSICAL 6 95 REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10) 96 REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14) 97 FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6) 98 REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18) 99 #define CXL_RAS_ERR_HEADER_NUM 32 100 /* Offset 0x18 - 0x58 reserved for RAS logs */ 101 102 /* 8.2.5.10 - CXL Security Capability Structure */ 103 #define CXL_SEC_REGISTERS_OFFSET \ 104 (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE) 105 #define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */ 106 107 /* 8.2.5.11 - CXL Link Capability Structure */ 108 #define CXL_LINK_REGISTERS_OFFSET \ 109 (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE) 110 #define CXL_LINK_REGISTERS_SIZE 0x38 111 112 /* CXL r3.1 Section 8.2.4.20: CXL HDM Decoder Capability Structure */ 113 #define HDM_DECODE_MAX 10 /* Maximum decoders for Devices */ 114 #define CXL_HDM_CAPABILITY_VERSION 3 115 #define CXL_HDM_REGISTERS_OFFSET \ 116 (CXL_LINK_REGISTERS_OFFSET + CXL_LINK_REGISTERS_SIZE) 117 #define CXL_HDM_REGISTERS_SIZE (0x10 + 0x20 * HDM_DECODE_MAX) 118 #define HDM_DECODER_INIT(n) \ 119 REG32(CXL_HDM_DECODER##n##_BASE_LO, \ 120 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x10) \ 121 FIELD(CXL_HDM_DECODER##n##_BASE_LO, L, 28, 4) \ 122 REG32(CXL_HDM_DECODER##n##_BASE_HI, \ 123 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x14) \ 124 REG32(CXL_HDM_DECODER##n##_SIZE_LO, \ 125 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x18) \ 126 REG32(CXL_HDM_DECODER##n##_SIZE_HI, \ 127 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x1C) \ 128 REG32(CXL_HDM_DECODER##n##_CTRL, \ 129 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x20) \ 130 FIELD(CXL_HDM_DECODER##n##_CTRL, IG, 0, 4) \ 131 FIELD(CXL_HDM_DECODER##n##_CTRL, IW, 4, 4) \ 132 FIELD(CXL_HDM_DECODER##n##_CTRL, LOCK_ON_COMMIT, 8, 1) \ 133 FIELD(CXL_HDM_DECODER##n##_CTRL, COMMIT, 9, 1) \ 134 FIELD(CXL_HDM_DECODER##n##_CTRL, COMMITTED, 10, 1) \ 135 FIELD(CXL_HDM_DECODER##n##_CTRL, ERR, 11, 1) \ 136 FIELD(CXL_HDM_DECODER##n##_CTRL, TYPE, 12, 1) \ 137 FIELD(CXL_HDM_DECODER##n##_CTRL, BI, 13, 1) \ 138 FIELD(CXL_HDM_DECODER##n##_CTRL, UIO, 14, 1) \ 139 FIELD(CXL_HDM_DECODER##n##_CTRL, UIG, 16, 4) \ 140 FIELD(CXL_HDM_DECODER##n##_CTRL, UIW, 20, 4) \ 141 FIELD(CXL_HDM_DECODER##n##_CTRL, ISP, 24, 4) \ 142 REG32(CXL_HDM_DECODER##n##_TARGET_LIST_LO, \ 143 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ 144 REG32(CXL_HDM_DECODER##n##_TARGET_LIST_HI, \ 145 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) \ 146 REG32(CXL_HDM_DECODER##n##_DPA_SKIP_LO, \ 147 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ 148 REG32(CXL_HDM_DECODER##n##_DPA_SKIP_HI, \ 149 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) 150 151 REG32(CXL_HDM_DECODER_CAPABILITY, CXL_HDM_REGISTERS_OFFSET) 152 FIELD(CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 0, 4) 153 FIELD(CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 4, 4) 154 FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 8, 1) 155 FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 9, 1) 156 FIELD(CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 10, 1) 157 FIELD(CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 11, 1) 158 FIELD(CXL_HDM_DECODER_CAPABILITY, 16_WAY, 12, 1) 159 FIELD(CXL_HDM_DECODER_CAPABILITY, UIO, 13, 1) 160 FIELD(CXL_HDM_DECODER_CAPABILITY, UIO_DECODER_COUNT, 16, 4) 161 FIELD(CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CAP, 20, 1) 162 FIELD(CXL_HDM_DECODER_CAPABILITY, SUPPORTED_COHERENCY_MODEL, 21, 2) 163 REG32(CXL_HDM_DECODER_GLOBAL_CONTROL, CXL_HDM_REGISTERS_OFFSET + 4) 164 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, POISON_ON_ERR_EN, 0, 1) 165 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 1, 1) 166 167 /* Support 4 decoders at all levels of topology */ 168 #define CXL_HDM_DECODER_COUNT 4 169 170 HDM_DECODER_INIT(0); 171 HDM_DECODER_INIT(1); 172 HDM_DECODER_INIT(2); 173 HDM_DECODER_INIT(3); 174 175 /* 8.2.5.13 - CXL Extended Security Capability Structure (Root complex only) */ 176 #define EXTSEC_ENTRY_MAX 256 177 #define CXL_EXTSEC_REGISTERS_OFFSET \ 178 (CXL_HDM_REGISTERS_OFFSET + CXL_HDM_REGISTERS_SIZE) 179 #define CXL_EXTSEC_REGISTERS_SIZE (8 * EXTSEC_ENTRY_MAX + 4) 180 181 /* 8.2.5.14 - CXL IDE Capability Structure */ 182 #define CXL_IDE_REGISTERS_OFFSET \ 183 (CXL_EXTSEC_REGISTERS_OFFSET + CXL_EXTSEC_REGISTERS_SIZE) 184 #define CXL_IDE_REGISTERS_SIZE 0x20 185 186 /* 8.2.5.15 - CXL Snoop Filter Capability Structure */ 187 #define CXL_SNOOP_REGISTERS_OFFSET \ 188 (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE) 189 #define CXL_SNOOP_REGISTERS_SIZE 0x8 190 191 QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET + 192 CXL_SNOOP_REGISTERS_SIZE) >= 0x1000, 193 "No space for registers"); 194 195 typedef struct component_registers { 196 /* 197 * Main memory region to be registered with QEMU core. 198 */ 199 MemoryRegion component_registers; 200 201 /* 202 * 8.2.4 Table 141: 203 * 0x0000 - 0x0fff CXL.io registers 204 * 0x1000 - 0x1fff CXL.cache and CXL.mem 205 * 0x2000 - 0xdfff Implementation specific 206 * 0xe000 - 0xe3ff CXL ARB/MUX registers 207 * 0xe400 - 0xffff RSVD 208 */ 209 uint32_t io_registers[CXL2_COMPONENT_IO_REGION_SIZE >> 2]; 210 MemoryRegion io; 211 212 uint32_t cache_mem_registers[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; 213 uint32_t cache_mem_regs_write_mask[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; 214 MemoryRegion cache_mem; 215 216 MemoryRegion impl_specific; 217 MemoryRegion arb_mux; 218 MemoryRegion rsvd; 219 220 /* special_ops is used for any component that needs any specific handling */ 221 MemoryRegionOps *special_ops; 222 } ComponentRegisters; 223 224 /* 225 * A CXL component represents all entities in a CXL hierarchy. This includes, 226 * host bridges, root ports, upstream/downstream switch ports, and devices 227 */ 228 typedef struct cxl_component { 229 ComponentRegisters crb; 230 union { 231 struct { 232 Range dvsecs[CXL20_MAX_DVSEC]; 233 uint16_t dvsec_offset; 234 struct PCIDevice *pdev; 235 }; 236 }; 237 238 CDATObject cdat; 239 } CXLComponentState; 240 241 void cxl_component_register_block_init(Object *obj, 242 CXLComponentState *cxl_cstate, 243 const char *type); 244 void cxl_component_register_init_common(uint32_t *reg_state, 245 uint32_t *write_msk, 246 enum reg_type type); 247 248 void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, 249 enum reg_type cxl_dev_type, uint16_t length, 250 uint16_t type, uint8_t rev, uint8_t *body); 251 252 int cxl_decoder_count_enc(int count); 253 int cxl_decoder_count_dec(int enc_cnt); 254 255 uint8_t cxl_interleave_ways_enc(int iw, Error **errp); 256 int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp); 257 uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp); 258 259 hwaddr cxl_decode_ig(int ig); 260 261 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb); 262 bool cxl_get_hb_passthrough(PCIHostState *hb); 263 264 void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp); 265 void cxl_doe_cdat_release(CXLComponentState *cxl_cstate); 266 void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp); 267 268 #endif 269