xref: /openbmc/qemu/include/hw/cxl/cxl.h (revision f6b615b52d1d92f02103596a30df95f31138a2e4)
19e58f52dSBen Widawsky /*
29e58f52dSBen Widawsky  * QEMU CXL Support
39e58f52dSBen Widawsky  *
49e58f52dSBen Widawsky  * Copyright (c) 2020 Intel
59e58f52dSBen Widawsky  *
69e58f52dSBen Widawsky  * This work is licensed under the terms of the GNU GPL, version 2. See the
79e58f52dSBen Widawsky  * COPYING file in the top-level directory.
89e58f52dSBen Widawsky  */
99e58f52dSBen Widawsky 
109e58f52dSBen Widawsky #ifndef CXL_H
119e58f52dSBen Widawsky #define CXL_H
129e58f52dSBen Widawsky 
13aadfe320SJonathan Cameron 
14aadfe320SJonathan Cameron #include "qapi/qapi-types-machine.h"
1503b39fcfSJonathan Cameron #include "qapi/qapi-visit-machine.h"
166e4e3ae9SBen Widawsky #include "hw/pci/pci_host.h"
179e58f52dSBen Widawsky #include "cxl_pci.h"
189e58f52dSBen Widawsky #include "cxl_component.h"
19cd90126bSBen Widawsky #include "cxl_device.h"
209e58f52dSBen Widawsky 
219547754fSJonathan Cameron #define CXL_CACHE_LINE_SIZE 64
22464e14acSBen Widawsky #define CXL_COMPONENT_REG_BAR_IDX 0
23464e14acSBen Widawsky #define CXL_DEVICE_REG_BAR_IDX 2
24464e14acSBen Widawsky 
256e4e3ae9SBen Widawsky #define CXL_WINDOW_MAX 10
266e4e3ae9SBen Widawsky 
27c28db9e0SJonathan Cameron typedef struct PXBCXLDev PXBCXLDev;
2865c326ceSMarkus Armbruster 
29aadfe320SJonathan Cameron typedef struct CXLFixedWindow {
30aadfe320SJonathan Cameron     uint64_t size;
31aadfe320SJonathan Cameron     char **targets;
32de5bbfc6SDmitry Frolov     PXBCXLDev *target_hbs[16];
33aadfe320SJonathan Cameron     uint8_t num_targets;
34aadfe320SJonathan Cameron     uint8_t enc_int_ways;
35aadfe320SJonathan Cameron     uint8_t enc_int_gran;
36aadfe320SJonathan Cameron     /* Todo: XOR based interleaving */
37aadfe320SJonathan Cameron     MemoryRegion mr;
38aadfe320SJonathan Cameron     hwaddr base;
39aadfe320SJonathan Cameron } CXLFixedWindow;
40aadfe320SJonathan Cameron 
41abb3009bSJonathan Cameron typedef struct CXLState {
42abb3009bSJonathan Cameron     bool is_enabled;
436e4e3ae9SBen Widawsky     MemoryRegion host_mr;
446e4e3ae9SBen Widawsky     unsigned int next_mr_idx;
45aadfe320SJonathan Cameron     GList *fixed_windows;
4603b39fcfSJonathan Cameron     CXLFixedMemoryWindowOptionsList *cfmw_list;
47abb3009bSJonathan Cameron } CXLState;
48abb3009bSJonathan Cameron 
496e4e3ae9SBen Widawsky struct CXLHost {
506e4e3ae9SBen Widawsky     PCIHostState parent_obj;
516e4e3ae9SBen Widawsky 
526e4e3ae9SBen Widawsky     CXLComponentState cxl_cstate;
53154070eaSJonathan Cameron     bool passthrough;
546e4e3ae9SBen Widawsky };
556e4e3ae9SBen Widawsky 
566e4e3ae9SBen Widawsky #define TYPE_PXB_CXL_HOST "pxb-cxl-host"
576e4e3ae9SBen Widawsky OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST)
586e4e3ae9SBen Widawsky 
59638b752dSJonathan Cameron #define TYPE_CXL_USP "cxl-upstream"
60638b752dSJonathan Cameron 
61638b752dSJonathan Cameron typedef struct CXLUpstreamPort CXLUpstreamPort;
62638b752dSJonathan Cameron DECLARE_INSTANCE_CHECKER(CXLUpstreamPort, CXL_USP, TYPE_CXL_USP)
63638b752dSJonathan Cameron CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp);
64*3314efd2SJonathan Cameron 
65*3314efd2SJonathan Cameron #define TYPE_CXL_DSP "cxl-downstream"
66*3314efd2SJonathan Cameron 
67*3314efd2SJonathan Cameron typedef struct CXLDownstreamPort CXLDownstreamPort;
68*3314efd2SJonathan Cameron DECLARE_INSTANCE_CHECKER(CXLDownstreamPort, CXL_DSP, TYPE_CXL_DSP)
69*3314efd2SJonathan Cameron 
709e58f52dSBen Widawsky #endif
71