1f0a902f7SPeter Crosthwaite /* 2f0a902f7SPeter Crosthwaite * Xilinx Zynq MPSoC emulation 3f0a902f7SPeter Crosthwaite * 4f0a902f7SPeter Crosthwaite * Copyright (C) 2015 Xilinx Inc 5f0a902f7SPeter Crosthwaite * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6f0a902f7SPeter Crosthwaite * 7f0a902f7SPeter Crosthwaite * This program is free software; you can redistribute it and/or modify it 8f0a902f7SPeter Crosthwaite * under the terms of the GNU General Public License as published by the 9f0a902f7SPeter Crosthwaite * Free Software Foundation; either version 2 of the License, or 10f0a902f7SPeter Crosthwaite * (at your option) any later version. 11f0a902f7SPeter Crosthwaite * 12f0a902f7SPeter Crosthwaite * This program is distributed in the hope that it will be useful, but WITHOUT 13f0a902f7SPeter Crosthwaite * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14f0a902f7SPeter Crosthwaite * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15f0a902f7SPeter Crosthwaite * for more details. 16f0a902f7SPeter Crosthwaite */ 17f0a902f7SPeter Crosthwaite 18f0a902f7SPeter Crosthwaite #ifndef XLNX_ZYNQMP_H 19f0a902f7SPeter Crosthwaite 20f0a902f7SPeter Crosthwaite #include "qemu-common.h" 21f0a902f7SPeter Crosthwaite #include "hw/arm/arm.h" 227729e1f4SPeter Crosthwaite #include "hw/intc/arm_gic.h" 2314ca2e46SPeter Crosthwaite #include "hw/net/cadence_gem.h" 243bade2a9SPeter Crosthwaite #include "hw/char/cadence_uart.h" 25*6fdf3282SAlistair Francis #include "hw/ide/pci.h" 26*6fdf3282SAlistair Francis #include "hw/ide/ahci.h" 27f0a902f7SPeter Crosthwaite 28f0a902f7SPeter Crosthwaite #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" 29f0a902f7SPeter Crosthwaite #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ 30f0a902f7SPeter Crosthwaite TYPE_XLNX_ZYNQMP) 31f0a902f7SPeter Crosthwaite 322e5577bcSPeter Crosthwaite #define XLNX_ZYNQMP_NUM_APU_CPUS 4 33b58850e7SPeter Crosthwaite #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 3414ca2e46SPeter Crosthwaite #define XLNX_ZYNQMP_NUM_GEMS 4 353bade2a9SPeter Crosthwaite #define XLNX_ZYNQMP_NUM_UARTS 2 36f0a902f7SPeter Crosthwaite 376675d719SAlistair Francis #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 386675d719SAlistair Francis #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 396675d719SAlistair Francis #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 406675d719SAlistair Francis 417729e1f4SPeter Crosthwaite #define XLNX_ZYNQMP_GIC_REGIONS 2 427729e1f4SPeter Crosthwaite 437729e1f4SPeter Crosthwaite /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets 447729e1f4SPeter Crosthwaite * and under-decodes the 64k region. This mirrors the 4k regions to every 4k 457729e1f4SPeter Crosthwaite * aligned address in the 64k region. To implement each GIC region needs a 467729e1f4SPeter Crosthwaite * number of memory region aliases. 477729e1f4SPeter Crosthwaite */ 487729e1f4SPeter Crosthwaite 497729e1f4SPeter Crosthwaite #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x4000 507729e1f4SPeter Crosthwaite #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1) 517729e1f4SPeter Crosthwaite 52f0a902f7SPeter Crosthwaite typedef struct XlnxZynqMPState { 53f0a902f7SPeter Crosthwaite /*< private >*/ 54f0a902f7SPeter Crosthwaite DeviceState parent_obj; 55f0a902f7SPeter Crosthwaite 56f0a902f7SPeter Crosthwaite /*< public >*/ 572e5577bcSPeter Crosthwaite ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; 58b58850e7SPeter Crosthwaite ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; 597729e1f4SPeter Crosthwaite GICState gic; 607729e1f4SPeter Crosthwaite MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; 616675d719SAlistair Francis MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; 626675d719SAlistair Francis 6314ca2e46SPeter Crosthwaite CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; 643bade2a9SPeter Crosthwaite CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; 65*6fdf3282SAlistair Francis SysbusAHCIState sata; 666396a193SPeter Crosthwaite 676396a193SPeter Crosthwaite char *boot_cpu; 686396a193SPeter Crosthwaite ARMCPU *boot_cpu_ptr; 69f0a902f7SPeter Crosthwaite } XlnxZynqMPState; 70f0a902f7SPeter Crosthwaite 71f0a902f7SPeter Crosthwaite #define XLNX_ZYNQMP_H 72f0a902f7SPeter Crosthwaite #endif 73