1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/intc/aspeed_intc.h" 19 #include "hw/misc/aspeed_scu.h" 20 #include "hw/adc/aspeed_adc.h" 21 #include "hw/misc/aspeed_gfx.h" 22 #include "hw/misc/aspeed_sdmc.h" 23 #include "hw/misc/aspeed_xdma.h" 24 #include "hw/timer/aspeed_timer.h" 25 #include "hw/rtc/aspeed_rtc.h" 26 #include "hw/i2c/aspeed_i2c.h" 27 #include "hw/misc/aspeed_i3c.h" 28 #include "hw/ssi/aspeed_smc.h" 29 #include "hw/misc/aspeed_hace.h" 30 #include "hw/misc/aspeed_sbc.h" 31 #include "hw/misc/aspeed_sli.h" 32 #include "hw/watchdog/wdt_aspeed.h" 33 #include "hw/net/ftgmac100.h" 34 #include "target/arm/cpu.h" 35 #include "hw/gpio/aspeed_gpio.h" 36 #include "hw/sd/aspeed_sdhci.h" 37 #include "hw/usb/hcd-ehci.h" 38 #include "hw/usb/hcd-uhci-sysbus.h" 39 #include "qom/object.h" 40 #include "hw/misc/aspeed_lpc.h" 41 #include "hw/misc/unimp.h" 42 #include "hw/misc/aspeed_peci.h" 43 #include "hw/fsi/aspeed_apb2opb.h" 44 #include "hw/char/serial-mm.h" 45 #include "hw/intc/arm_gicv3.h" 46 47 #define ASPEED_SPIS_NUM 2 48 #define ASPEED_EHCIS_NUM 2 49 #define ASPEED_WDTS_NUM 8 50 #define ASPEED_CPUS_NUM 4 51 #define ASPEED_MACS_NUM 4 52 #define ASPEED_UARTS_NUM 13 53 #define ASPEED_JTAG_NUM 2 54 55 struct AspeedSoCState { 56 DeviceState parent; 57 58 MemoryRegion *memory; 59 MemoryRegion *dram_mr; 60 MemoryRegion dram_container; 61 MemoryRegion sram; 62 MemoryRegion spi_boot_container; 63 MemoryRegion spi_boot; 64 AddressSpace dram_as; 65 AspeedRtcState rtc; 66 AspeedTimerCtrlState timerctrl; 67 AspeedI2CState i2c; 68 AspeedI3CState i3c; 69 AspeedSCUState scu; 70 AspeedSCUState scuio; 71 AspeedHACEState hace; 72 AspeedXDMAState xdma; 73 AspeedADCState adc; 74 AspeedSMCState fmc; 75 AspeedSMCState spi[ASPEED_SPIS_NUM]; 76 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 77 ASPEEDUHCIState uhci; 78 AspeedSBCState sbc; 79 AspeedSLIState sli; 80 AspeedSLIState sliio; 81 MemoryRegion secsram; 82 UnimplementedDeviceState sbc_unimplemented; 83 AspeedSDMCState sdmc; 84 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 85 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 86 AspeedMiiState mii[ASPEED_MACS_NUM]; 87 AspeedGPIOState gpio; 88 AspeedGPIOState gpio_1_8v; 89 AspeedSDHCIState sdhci; 90 AspeedSDHCIState emmc; 91 AspeedLPCState lpc; 92 AspeedPECIState peci; 93 AspeedGFXState gfx; 94 SerialMM uart[ASPEED_UARTS_NUM]; 95 Clock *sysclk; 96 UnimplementedDeviceState iomem; 97 UnimplementedDeviceState video; 98 UnimplementedDeviceState emmc_boot_controller; 99 UnimplementedDeviceState dpmcu; 100 UnimplementedDeviceState pwm; 101 UnimplementedDeviceState espi; 102 UnimplementedDeviceState udc; 103 UnimplementedDeviceState sgpiom; 104 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 105 AspeedAPB2OPBState fsi[2]; 106 }; 107 108 #define TYPE_ASPEED_SOC "aspeed-soc" 109 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 110 111 struct Aspeed2400SoCState { 112 AspeedSoCState parent; 113 114 ARMCPU cpu[ASPEED_CPUS_NUM]; 115 AspeedVICState vic; 116 }; 117 118 #define TYPE_ASPEED2400_SOC "aspeed2400-soc" 119 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) 120 121 struct Aspeed2600SoCState { 122 AspeedSoCState parent; 123 124 A15MPPrivState a7mpcore; 125 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ 126 }; 127 128 #define TYPE_ASPEED2600_SOC "aspeed2600-soc" 129 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) 130 131 struct Aspeed27x0SoCState { 132 AspeedSoCState parent; 133 134 ARMCPU cpu[ASPEED_CPUS_NUM]; 135 AspeedINTCState intc; 136 GICv3State gic; 137 MemoryRegion dram_empty; 138 }; 139 140 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc" 141 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC) 142 143 struct Aspeed10x0SoCState { 144 AspeedSoCState parent; 145 146 ARMv7MState armv7m; 147 }; 148 149 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" 150 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) 151 152 struct AspeedSoCClass { 153 DeviceClass parent_class; 154 155 const char *name; 156 /** valid_cpu_types: NULL terminated array of a single CPU type. */ 157 const char * const *valid_cpu_types; 158 uint32_t silicon_rev; 159 uint64_t sram_size; 160 uint64_t secsram_size; 161 int spis_num; 162 int ehcis_num; 163 int wdts_num; 164 int macs_num; 165 int uarts_num; 166 int uarts_base; 167 const int *irqmap; 168 const hwaddr *memmap; 169 uint32_t num_cpus; 170 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 171 bool (*boot_from_emmc)(AspeedSoCState *s); 172 }; 173 174 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); 175 176 enum { 177 ASPEED_DEV_SPI_BOOT, 178 ASPEED_DEV_IOMEM, 179 ASPEED_DEV_UART0, 180 ASPEED_DEV_UART1, 181 ASPEED_DEV_UART2, 182 ASPEED_DEV_UART3, 183 ASPEED_DEV_UART4, 184 ASPEED_DEV_UART5, 185 ASPEED_DEV_UART6, 186 ASPEED_DEV_UART7, 187 ASPEED_DEV_UART8, 188 ASPEED_DEV_UART9, 189 ASPEED_DEV_UART10, 190 ASPEED_DEV_UART11, 191 ASPEED_DEV_UART12, 192 ASPEED_DEV_UART13, 193 ASPEED_DEV_VUART, 194 ASPEED_DEV_FMC, 195 ASPEED_DEV_SPI0, 196 ASPEED_DEV_SPI1, 197 ASPEED_DEV_SPI2, 198 ASPEED_DEV_EHCI1, 199 ASPEED_DEV_EHCI2, 200 ASPEED_DEV_UHCI, 201 ASPEED_DEV_VIC, 202 ASPEED_DEV_INTC, 203 ASPEED_DEV_SDMC, 204 ASPEED_DEV_SCU, 205 ASPEED_DEV_ADC, 206 ASPEED_DEV_SBC, 207 ASPEED_DEV_SECSRAM, 208 ASPEED_DEV_EMMC_BC, 209 ASPEED_DEV_VIDEO, 210 ASPEED_DEV_SRAM, 211 ASPEED_DEV_SDHCI, 212 ASPEED_DEV_GPIO, 213 ASPEED_DEV_GPIO_1_8V, 214 ASPEED_DEV_RTC, 215 ASPEED_DEV_TIMER1, 216 ASPEED_DEV_TIMER2, 217 ASPEED_DEV_TIMER3, 218 ASPEED_DEV_TIMER4, 219 ASPEED_DEV_TIMER5, 220 ASPEED_DEV_TIMER6, 221 ASPEED_DEV_TIMER7, 222 ASPEED_DEV_TIMER8, 223 ASPEED_DEV_WDT, 224 ASPEED_DEV_PWM, 225 ASPEED_DEV_LPC, 226 ASPEED_DEV_IBT, 227 ASPEED_DEV_I2C, 228 ASPEED_DEV_PECI, 229 ASPEED_DEV_ETH1, 230 ASPEED_DEV_ETH2, 231 ASPEED_DEV_ETH3, 232 ASPEED_DEV_ETH4, 233 ASPEED_DEV_MII1, 234 ASPEED_DEV_MII2, 235 ASPEED_DEV_MII3, 236 ASPEED_DEV_MII4, 237 ASPEED_DEV_SDRAM, 238 ASPEED_DEV_XDMA, 239 ASPEED_DEV_EMMC, 240 ASPEED_DEV_KCS, 241 ASPEED_DEV_HACE, 242 ASPEED_DEV_GFX, 243 ASPEED_DEV_DPMCU, 244 ASPEED_DEV_DP, 245 ASPEED_DEV_I3C, 246 ASPEED_DEV_ESPI, 247 ASPEED_DEV_UDC, 248 ASPEED_DEV_SGPIOM, 249 ASPEED_DEV_JTAG0, 250 ASPEED_DEV_JTAG1, 251 ASPEED_DEV_FSI1, 252 ASPEED_DEV_FSI2, 253 ASPEED_DEV_SCUIO, 254 ASPEED_DEV_SLI, 255 ASPEED_DEV_SLIIO, 256 ASPEED_GIC_DIST, 257 ASPEED_GIC_REDIST, 258 }; 259 260 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 261 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 262 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 263 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 264 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 265 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 266 const char *name, hwaddr addr, 267 uint64_t size); 268 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 269 unsigned int count, int unit0); 270 271 static inline int aspeed_uart_index(int uart_dev) 272 { 273 return uart_dev - ASPEED_DEV_UART0; 274 } 275 276 static inline int aspeed_uart_first(AspeedSoCClass *sc) 277 { 278 return aspeed_uart_index(sc->uarts_base); 279 } 280 281 static inline int aspeed_uart_last(AspeedSoCClass *sc) 282 { 283 return aspeed_uart_first(sc) + sc->uarts_num - 1; 284 } 285 286 #endif /* ASPEED_SOC_H */ 287