1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/intc/aspeed_intc.h" 19 #include "hw/misc/aspeed_scu.h" 20 #include "hw/adc/aspeed_adc.h" 21 #include "hw/misc/aspeed_gfx.h" 22 #include "hw/misc/aspeed_sdmc.h" 23 #include "hw/misc/aspeed_xdma.h" 24 #include "hw/timer/aspeed_timer.h" 25 #include "hw/rtc/aspeed_rtc.h" 26 #include "hw/i2c/aspeed_i2c.h" 27 #include "hw/misc/aspeed_i3c.h" 28 #include "hw/ssi/aspeed_smc.h" 29 #include "hw/misc/aspeed_hace.h" 30 #include "hw/misc/aspeed_sbc.h" 31 #include "hw/misc/aspeed_sli.h" 32 #include "hw/misc/aspeed_pwm.h" 33 #include "hw/watchdog/wdt_aspeed.h" 34 #include "hw/net/ftgmac100.h" 35 #include "target/arm/cpu.h" 36 #include "hw/gpio/aspeed_gpio.h" 37 #include "hw/sd/aspeed_sdhci.h" 38 #include "hw/usb/hcd-ehci.h" 39 #include "hw/usb/hcd-uhci-sysbus.h" 40 #include "qom/object.h" 41 #include "hw/misc/aspeed_lpc.h" 42 #include "hw/misc/unimp.h" 43 #include "hw/misc/aspeed_peci.h" 44 #include "hw/fsi/aspeed_apb2opb.h" 45 #include "hw/char/serial-mm.h" 46 #include "hw/intc/arm_gicv3.h" 47 48 #define ASPEED_SPIS_NUM 2 49 #define ASPEED_EHCIS_NUM 2 50 #define ASPEED_WDTS_NUM 8 51 #define ASPEED_CPUS_NUM 4 52 #define ASPEED_MACS_NUM 4 53 #define ASPEED_UARTS_NUM 13 54 #define ASPEED_JTAG_NUM 2 55 56 struct AspeedSoCState { 57 DeviceState parent; 58 59 MemoryRegion *memory; 60 MemoryRegion *dram_mr; 61 MemoryRegion dram_container; 62 MemoryRegion sram; 63 MemoryRegion spi_boot_container; 64 MemoryRegion spi_boot; 65 AddressSpace dram_as; 66 AspeedRtcState rtc; 67 AspeedTimerCtrlState timerctrl; 68 AspeedI2CState i2c; 69 AspeedI3CState i3c; 70 AspeedSCUState scu; 71 AspeedSCUState scuio; 72 AspeedHACEState hace; 73 AspeedXDMAState xdma; 74 AspeedADCState adc; 75 AspeedSMCState fmc; 76 AspeedSMCState spi[ASPEED_SPIS_NUM]; 77 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 78 ASPEEDUHCIState uhci; 79 AspeedSBCState sbc; 80 AspeedSLIState sli; 81 AspeedSLIState sliio; 82 MemoryRegion secsram; 83 UnimplementedDeviceState sbc_unimplemented; 84 AspeedSDMCState sdmc; 85 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 86 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 87 AspeedMiiState mii[ASPEED_MACS_NUM]; 88 AspeedGPIOState gpio; 89 AspeedGPIOState gpio_1_8v; 90 AspeedSDHCIState sdhci; 91 AspeedSDHCIState emmc; 92 AspeedLPCState lpc; 93 AspeedPECIState peci; 94 AspeedGFXState gfx; 95 SerialMM uart[ASPEED_UARTS_NUM]; 96 Clock *sysclk; 97 UnimplementedDeviceState iomem; 98 UnimplementedDeviceState video; 99 UnimplementedDeviceState emmc_boot_controller; 100 UnimplementedDeviceState dpmcu; 101 AspeedPWMState pwm; 102 UnimplementedDeviceState espi; 103 UnimplementedDeviceState udc; 104 UnimplementedDeviceState sgpiom; 105 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 106 AspeedAPB2OPBState fsi[2]; 107 }; 108 109 #define TYPE_ASPEED_SOC "aspeed-soc" 110 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 111 112 struct Aspeed2400SoCState { 113 AspeedSoCState parent; 114 115 ARMCPU cpu[ASPEED_CPUS_NUM]; 116 AspeedVICState vic; 117 }; 118 119 #define TYPE_ASPEED2400_SOC "aspeed2400-soc" 120 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) 121 122 struct Aspeed2600SoCState { 123 AspeedSoCState parent; 124 125 A15MPPrivState a7mpcore; 126 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ 127 }; 128 129 #define TYPE_ASPEED2600_SOC "aspeed2600-soc" 130 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) 131 132 struct Aspeed27x0SoCState { 133 AspeedSoCState parent; 134 135 ARMCPU cpu[ASPEED_CPUS_NUM]; 136 AspeedINTCState intc; 137 GICv3State gic; 138 MemoryRegion dram_empty; 139 }; 140 141 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc" 142 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC) 143 144 struct Aspeed10x0SoCState { 145 AspeedSoCState parent; 146 147 ARMv7MState armv7m; 148 }; 149 150 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" 151 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) 152 153 struct AspeedSoCClass { 154 DeviceClass parent_class; 155 156 const char *name; 157 /** valid_cpu_types: NULL terminated array of a single CPU type. */ 158 const char * const *valid_cpu_types; 159 uint32_t silicon_rev; 160 uint64_t sram_size; 161 uint64_t secsram_size; 162 int spis_num; 163 int ehcis_num; 164 int wdts_num; 165 int macs_num; 166 int uarts_num; 167 int uarts_base; 168 const int *irqmap; 169 const hwaddr *memmap; 170 uint32_t num_cpus; 171 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 172 bool (*boot_from_emmc)(AspeedSoCState *s); 173 }; 174 175 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); 176 177 enum { 178 ASPEED_DEV_SPI_BOOT, 179 ASPEED_DEV_IOMEM, 180 ASPEED_DEV_UART0, 181 ASPEED_DEV_UART1, 182 ASPEED_DEV_UART2, 183 ASPEED_DEV_UART3, 184 ASPEED_DEV_UART4, 185 ASPEED_DEV_UART5, 186 ASPEED_DEV_UART6, 187 ASPEED_DEV_UART7, 188 ASPEED_DEV_UART8, 189 ASPEED_DEV_UART9, 190 ASPEED_DEV_UART10, 191 ASPEED_DEV_UART11, 192 ASPEED_DEV_UART12, 193 ASPEED_DEV_UART13, 194 ASPEED_DEV_VUART, 195 ASPEED_DEV_FMC, 196 ASPEED_DEV_SPI0, 197 ASPEED_DEV_SPI1, 198 ASPEED_DEV_SPI2, 199 ASPEED_DEV_EHCI1, 200 ASPEED_DEV_EHCI2, 201 ASPEED_DEV_UHCI, 202 ASPEED_DEV_VIC, 203 ASPEED_DEV_INTC, 204 ASPEED_DEV_SDMC, 205 ASPEED_DEV_SCU, 206 ASPEED_DEV_ADC, 207 ASPEED_DEV_SBC, 208 ASPEED_DEV_SECSRAM, 209 ASPEED_DEV_EMMC_BC, 210 ASPEED_DEV_VIDEO, 211 ASPEED_DEV_SRAM, 212 ASPEED_DEV_SDHCI, 213 ASPEED_DEV_GPIO, 214 ASPEED_DEV_GPIO_1_8V, 215 ASPEED_DEV_RTC, 216 ASPEED_DEV_TIMER1, 217 ASPEED_DEV_TIMER2, 218 ASPEED_DEV_TIMER3, 219 ASPEED_DEV_TIMER4, 220 ASPEED_DEV_TIMER5, 221 ASPEED_DEV_TIMER6, 222 ASPEED_DEV_TIMER7, 223 ASPEED_DEV_TIMER8, 224 ASPEED_DEV_WDT, 225 ASPEED_DEV_PWM, 226 ASPEED_DEV_LPC, 227 ASPEED_DEV_IBT, 228 ASPEED_DEV_I2C, 229 ASPEED_DEV_PECI, 230 ASPEED_DEV_ETH1, 231 ASPEED_DEV_ETH2, 232 ASPEED_DEV_ETH3, 233 ASPEED_DEV_ETH4, 234 ASPEED_DEV_MII1, 235 ASPEED_DEV_MII2, 236 ASPEED_DEV_MII3, 237 ASPEED_DEV_MII4, 238 ASPEED_DEV_SDRAM, 239 ASPEED_DEV_XDMA, 240 ASPEED_DEV_EMMC, 241 ASPEED_DEV_KCS, 242 ASPEED_DEV_HACE, 243 ASPEED_DEV_GFX, 244 ASPEED_DEV_DPMCU, 245 ASPEED_DEV_DP, 246 ASPEED_DEV_I3C, 247 ASPEED_DEV_ESPI, 248 ASPEED_DEV_UDC, 249 ASPEED_DEV_SGPIOM, 250 ASPEED_DEV_JTAG0, 251 ASPEED_DEV_JTAG1, 252 ASPEED_DEV_FSI1, 253 ASPEED_DEV_FSI2, 254 ASPEED_DEV_SCUIO, 255 ASPEED_DEV_SLI, 256 ASPEED_DEV_SLIIO, 257 ASPEED_GIC_DIST, 258 ASPEED_GIC_REDIST, 259 }; 260 261 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 262 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 263 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 264 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 265 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 266 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 267 const char *name, hwaddr addr, 268 uint64_t size); 269 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 270 unsigned int count, int unit0); 271 272 static inline int aspeed_uart_index(int uart_dev) 273 { 274 return uart_dev - ASPEED_DEV_UART0; 275 } 276 277 static inline int aspeed_uart_first(AspeedSoCClass *sc) 278 { 279 return aspeed_uart_index(sc->uarts_base); 280 } 281 282 static inline int aspeed_uart_last(AspeedSoCClass *sc) 283 { 284 return aspeed_uart_first(sc) + sc->uarts_num - 1; 285 } 286 287 #endif /* ASPEED_SOC_H */ 288