1 /* 2 * ASPEED SoC family 3 * 4 * Andrew Jeffery <andrew@aj.id.au> 5 * 6 * Copyright 2016 IBM Corp. 7 * 8 * This code is licensed under the GPL version 2 or later. See 9 * the COPYING file in the top-level directory. 10 */ 11 12 #ifndef ASPEED_SOC_H 13 #define ASPEED_SOC_H 14 15 #include "hw/cpu/a15mpcore.h" 16 #include "hw/arm/armv7m.h" 17 #include "hw/intc/aspeed_vic.h" 18 #include "hw/intc/aspeed_intc.h" 19 #include "hw/misc/aspeed_scu.h" 20 #include "hw/adc/aspeed_adc.h" 21 #include "hw/misc/aspeed_gfx.h" 22 #include "hw/misc/aspeed_sdmc.h" 23 #include "hw/misc/aspeed_xdma.h" 24 #include "hw/timer/aspeed_timer.h" 25 #include "hw/rtc/aspeed_rtc.h" 26 #include "hw/misc/aspeed_ibt.h" 27 #include "hw/i2c/aspeed_i2c.h" 28 #include "hw/misc/aspeed_i3c.h" 29 #include "hw/ssi/aspeed_smc.h" 30 #include "hw/misc/aspeed_hace.h" 31 #include "hw/misc/aspeed_sbc.h" 32 #include "hw/misc/aspeed_sli.h" 33 #include "hw/misc/aspeed_pwm.h" 34 #include "hw/watchdog/wdt_aspeed.h" 35 #include "hw/net/ftgmac100.h" 36 #include "target/arm/cpu.h" 37 #include "hw/gpio/aspeed_gpio.h" 38 #include "hw/sd/aspeed_sdhci.h" 39 #include "hw/usb/hcd-ehci.h" 40 #include "hw/usb/hcd-uhci-sysbus.h" 41 #include "qom/object.h" 42 #include "hw/misc/aspeed_lpc.h" 43 #include "hw/misc/unimp.h" 44 #include "hw/misc/aspeed_peci.h" 45 #include "hw/fsi/aspeed_apb2opb.h" 46 #include "hw/char/serial-mm.h" 47 #include "hw/intc/arm_gicv3.h" 48 49 #define ASPEED_SPIS_NUM 2 50 #define ASPEED_EHCIS_NUM 2 51 #define ASPEED_WDTS_NUM 8 52 #define ASPEED_CPUS_NUM 4 53 #define ASPEED_MACS_NUM 4 54 #define ASPEED_UARTS_NUM 13 55 #define ASPEED_JTAG_NUM 2 56 57 struct AspeedSoCState { 58 DeviceState parent; 59 60 MemoryRegion *memory; 61 MemoryRegion *dram_mr; 62 MemoryRegion dram_container; 63 MemoryRegion sram; 64 MemoryRegion spi_boot_container; 65 MemoryRegion spi_boot; 66 AddressSpace dram_as; 67 AspeedRtcState rtc; 68 AspeedTimerCtrlState timerctrl; 69 AspeedIBTState ibt; 70 AspeedI2CState i2c; 71 AspeedI3CState i3c; 72 AspeedSCUState scu; 73 AspeedSCUState scuio; 74 AspeedHACEState hace; 75 AspeedXDMAState xdma; 76 AspeedADCState adc; 77 AspeedSMCState fmc; 78 AspeedSMCState spi[ASPEED_SPIS_NUM]; 79 EHCISysBusState ehci[ASPEED_EHCIS_NUM]; 80 ASPEEDUHCIState uhci; 81 AspeedSBCState sbc; 82 AspeedSLIState sli; 83 AspeedSLIState sliio; 84 MemoryRegion secsram; 85 UnimplementedDeviceState sbc_unimplemented; 86 AspeedSDMCState sdmc; 87 AspeedWDTState wdt[ASPEED_WDTS_NUM]; 88 FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; 89 AspeedMiiState mii[ASPEED_MACS_NUM]; 90 AspeedGPIOState gpio; 91 AspeedGPIOState gpio_1_8v; 92 AspeedSDHCIState sdhci; 93 AspeedSDHCIState emmc; 94 AspeedLPCState lpc; 95 AspeedPECIState peci; 96 AspeedGFXState gfx; 97 SerialMM uart[ASPEED_UARTS_NUM]; 98 Clock *sysclk; 99 UnimplementedDeviceState iomem; 100 UnimplementedDeviceState video; 101 UnimplementedDeviceState emmc_boot_controller; 102 UnimplementedDeviceState dpmcu; 103 AspeedPWMState pwm; 104 UnimplementedDeviceState espi; 105 UnimplementedDeviceState udc; 106 UnimplementedDeviceState sgpiom; 107 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; 108 AspeedAPB2OPBState fsi[2]; 109 }; 110 111 #define TYPE_ASPEED_SOC "aspeed-soc" 112 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) 113 114 struct Aspeed2400SoCState { 115 AspeedSoCState parent; 116 117 ARMCPU cpu[ASPEED_CPUS_NUM]; 118 AspeedVICState vic; 119 }; 120 121 #define TYPE_ASPEED2400_SOC "aspeed2400-soc" 122 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC) 123 124 struct Aspeed2600SoCState { 125 AspeedSoCState parent; 126 127 A15MPPrivState a7mpcore; 128 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */ 129 }; 130 131 #define TYPE_ASPEED2600_SOC "aspeed2600-soc" 132 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC) 133 134 struct Aspeed27x0SoCState { 135 AspeedSoCState parent; 136 137 ARMCPU cpu[ASPEED_CPUS_NUM]; 138 AspeedINTCState intc; 139 GICv3State gic; 140 MemoryRegion dram_empty; 141 }; 142 143 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc" 144 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC) 145 146 struct Aspeed10x0SoCState { 147 AspeedSoCState parent; 148 149 ARMv7MState armv7m; 150 }; 151 152 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc" 153 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC) 154 155 struct AspeedSoCClass { 156 DeviceClass parent_class; 157 158 const char *name; 159 /** valid_cpu_types: NULL terminated array of a single CPU type. */ 160 const char * const *valid_cpu_types; 161 uint32_t silicon_rev; 162 uint64_t sram_size; 163 uint64_t secsram_size; 164 int spis_num; 165 int ehcis_num; 166 int wdts_num; 167 int macs_num; 168 int uarts_num; 169 int uarts_base; 170 const int *irqmap; 171 const hwaddr *memmap; 172 uint32_t num_cpus; 173 qemu_irq (*get_irq)(AspeedSoCState *s, int dev); 174 bool (*boot_from_emmc)(AspeedSoCState *s); 175 }; 176 177 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); 178 179 enum { 180 ASPEED_DEV_SPI_BOOT, 181 ASPEED_DEV_IOMEM, 182 ASPEED_DEV_UART0, 183 ASPEED_DEV_UART1, 184 ASPEED_DEV_UART2, 185 ASPEED_DEV_UART3, 186 ASPEED_DEV_UART4, 187 ASPEED_DEV_UART5, 188 ASPEED_DEV_UART6, 189 ASPEED_DEV_UART7, 190 ASPEED_DEV_UART8, 191 ASPEED_DEV_UART9, 192 ASPEED_DEV_UART10, 193 ASPEED_DEV_UART11, 194 ASPEED_DEV_UART12, 195 ASPEED_DEV_UART13, 196 ASPEED_DEV_VUART, 197 ASPEED_DEV_FMC, 198 ASPEED_DEV_SPI0, 199 ASPEED_DEV_SPI1, 200 ASPEED_DEV_SPI2, 201 ASPEED_DEV_EHCI1, 202 ASPEED_DEV_EHCI2, 203 ASPEED_DEV_UHCI, 204 ASPEED_DEV_VIC, 205 ASPEED_DEV_INTC, 206 ASPEED_DEV_SDMC, 207 ASPEED_DEV_SCU, 208 ASPEED_DEV_ADC, 209 ASPEED_DEV_SBC, 210 ASPEED_DEV_SECSRAM, 211 ASPEED_DEV_EMMC_BC, 212 ASPEED_DEV_VIDEO, 213 ASPEED_DEV_SRAM, 214 ASPEED_DEV_SDHCI, 215 ASPEED_DEV_GPIO, 216 ASPEED_DEV_GPIO_1_8V, 217 ASPEED_DEV_RTC, 218 ASPEED_DEV_TIMER1, 219 ASPEED_DEV_TIMER2, 220 ASPEED_DEV_TIMER3, 221 ASPEED_DEV_TIMER4, 222 ASPEED_DEV_TIMER5, 223 ASPEED_DEV_TIMER6, 224 ASPEED_DEV_TIMER7, 225 ASPEED_DEV_TIMER8, 226 ASPEED_DEV_WDT, 227 ASPEED_DEV_PWM, 228 ASPEED_DEV_LPC, 229 ASPEED_DEV_IBT, 230 ASPEED_DEV_I2C, 231 ASPEED_DEV_PECI, 232 ASPEED_DEV_ETH1, 233 ASPEED_DEV_ETH2, 234 ASPEED_DEV_ETH3, 235 ASPEED_DEV_ETH4, 236 ASPEED_DEV_MII1, 237 ASPEED_DEV_MII2, 238 ASPEED_DEV_MII3, 239 ASPEED_DEV_MII4, 240 ASPEED_DEV_SDRAM, 241 ASPEED_DEV_XDMA, 242 ASPEED_DEV_EMMC, 243 ASPEED_DEV_KCS, 244 ASPEED_DEV_HACE, 245 ASPEED_DEV_GFX, 246 ASPEED_DEV_DPMCU, 247 ASPEED_DEV_DP, 248 ASPEED_DEV_I3C, 249 ASPEED_DEV_ESPI, 250 ASPEED_DEV_UDC, 251 ASPEED_DEV_SGPIOM, 252 ASPEED_DEV_JTAG0, 253 ASPEED_DEV_JTAG1, 254 ASPEED_DEV_FSI1, 255 ASPEED_DEV_FSI2, 256 ASPEED_DEV_SCUIO, 257 ASPEED_DEV_SLI, 258 ASPEED_DEV_SLIIO, 259 ASPEED_GIC_DIST, 260 ASPEED_GIC_REDIST, 261 }; 262 263 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); 264 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); 265 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); 266 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); 267 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); 268 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, 269 const char *name, hwaddr addr, 270 uint64_t size); 271 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, 272 unsigned int count, int unit0); 273 274 static inline int aspeed_uart_index(int uart_dev) 275 { 276 return uart_dev - ASPEED_DEV_UART0; 277 } 278 279 static inline int aspeed_uart_first(AspeedSoCClass *sc) 280 { 281 return aspeed_uart_index(sc->uarts_base); 282 } 283 284 static inline int aspeed_uart_last(AspeedSoCClass *sc) 285 { 286 return aspeed_uart_first(sc) + sc->uarts_num - 1; 287 } 288 289 #endif /* ASPEED_SOC_H */ 290