1 /* 2 * Aspeed ADC 3 * 4 * Copyright 2017-2021 IBM Corp. 5 * 6 * Andrew Jeffery <andrew@aj.id.au> 7 * 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 11 #ifndef HW_ADC_ASPEED_ADC_H 12 #define HW_ADC_ASPEED_ADC_H 13 14 #include "hw/sysbus.h" 15 16 #define TYPE_ASPEED_ADC "aspeed.adc" 17 #define TYPE_ASPEED_2400_ADC TYPE_ASPEED_ADC "-ast2400" 18 #define TYPE_ASPEED_2500_ADC TYPE_ASPEED_ADC "-ast2500" 19 #define TYPE_ASPEED_2600_ADC TYPE_ASPEED_ADC "-ast2600" 20 OBJECT_DECLARE_TYPE(AspeedADCState, AspeedADCClass, ASPEED_ADC) 21 22 #define TYPE_ASPEED_ADC_ENGINE "aspeed.adc.engine" 23 OBJECT_DECLARE_SIMPLE_TYPE(AspeedADCEngineState, ASPEED_ADC_ENGINE) 24 25 #define ASPEED_ADC_NR_CHANNELS 16 26 27 typedef struct AspeedADCEngineState { 28 /* <private> */ 29 SysBusDevice parent; 30 31 MemoryRegion mmio; 32 qemu_irq irq; 33 uint32_t engine_id; 34 uint32_t ch_off; 35 36 uint32_t engine_ctrl; 37 uint32_t irq_ctrl; 38 uint32_t vga_detect_ctrl; 39 uint32_t adc_clk_ctrl; 40 uint32_t channels[ASPEED_ADC_NR_CHANNELS / 2]; 41 uint32_t bounds[ASPEED_ADC_NR_CHANNELS]; 42 uint32_t hysteresis[ASPEED_ADC_NR_CHANNELS]; 43 uint32_t irq_src; 44 uint32_t comp_trim; 45 } AspeedADCEngineState; 46 47 typedef struct AspeedADCState { 48 /* <private> */ 49 SysBusDevice parent; 50 51 MemoryRegion mmio; 52 qemu_irq irq; 53 54 AspeedADCEngineState engines[2]; 55 } AspeedADCState; 56 57 struct AspeedADCClass { 58 SysBusDeviceClass parent_class; 59 60 uint8_t nr_engines; 61 }; 62 63 #endif /* HW_ADC_ASPEED_ADC_H */ 64