xref: /openbmc/qemu/include/hw/acpi/ich9_tco.h (revision fbae27e857061e1098c21944c81bd025c8946c62)
1*fbae27e8SPhilippe Mathieu-Daudé /*
2*fbae27e8SPhilippe Mathieu-Daudé  * QEMU ICH9 TCO emulation (total cost of ownership)
3*fbae27e8SPhilippe Mathieu-Daudé  *
4*fbae27e8SPhilippe Mathieu-Daudé  * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
5*fbae27e8SPhilippe Mathieu-Daudé  *
6*fbae27e8SPhilippe Mathieu-Daudé  * This work is licensed under the terms of the GNU GPL, version 2 or later.
7*fbae27e8SPhilippe Mathieu-Daudé  * See the COPYING file in the top-level directory.
8*fbae27e8SPhilippe Mathieu-Daudé  */
9*fbae27e8SPhilippe Mathieu-Daudé 
10*fbae27e8SPhilippe Mathieu-Daudé #ifndef HW_ACPI_TCO_H
11*fbae27e8SPhilippe Mathieu-Daudé #define HW_ACPI_TCO_H
12*fbae27e8SPhilippe Mathieu-Daudé 
13*fbae27e8SPhilippe Mathieu-Daudé #include "exec/memory.h"
14*fbae27e8SPhilippe Mathieu-Daudé 
15*fbae27e8SPhilippe Mathieu-Daudé /* As per ICH9 spec, the internal timer has an error of ~0.6s on every tick */
16*fbae27e8SPhilippe Mathieu-Daudé #define TCO_TICK_NSEC 600000000LL
17*fbae27e8SPhilippe Mathieu-Daudé 
18*fbae27e8SPhilippe Mathieu-Daudé /* TCO I/O register offsets */
19*fbae27e8SPhilippe Mathieu-Daudé enum {
20*fbae27e8SPhilippe Mathieu-Daudé     TCO_RLD           = 0x00,
21*fbae27e8SPhilippe Mathieu-Daudé     TCO_DAT_IN        = 0x02,
22*fbae27e8SPhilippe Mathieu-Daudé     TCO_DAT_OUT       = 0x03,
23*fbae27e8SPhilippe Mathieu-Daudé     TCO1_STS          = 0x04,
24*fbae27e8SPhilippe Mathieu-Daudé     TCO2_STS          = 0x06,
25*fbae27e8SPhilippe Mathieu-Daudé     TCO1_CNT          = 0x08,
26*fbae27e8SPhilippe Mathieu-Daudé     TCO2_CNT          = 0x0a,
27*fbae27e8SPhilippe Mathieu-Daudé     TCO_MESSAGE1      = 0x0c,
28*fbae27e8SPhilippe Mathieu-Daudé     TCO_MESSAGE2      = 0x0d,
29*fbae27e8SPhilippe Mathieu-Daudé     TCO_WDCNT         = 0x0e,
30*fbae27e8SPhilippe Mathieu-Daudé     SW_IRQ_GEN        = 0x10,
31*fbae27e8SPhilippe Mathieu-Daudé     TCO_TMR           = 0x12,
32*fbae27e8SPhilippe Mathieu-Daudé };
33*fbae27e8SPhilippe Mathieu-Daudé 
34*fbae27e8SPhilippe Mathieu-Daudé /* TCO I/O register control/status bits */
35*fbae27e8SPhilippe Mathieu-Daudé enum {
36*fbae27e8SPhilippe Mathieu-Daudé     SW_TCO_SMI           = 1 << 1,
37*fbae27e8SPhilippe Mathieu-Daudé     TCO_INT_STS          = 1 << 2,
38*fbae27e8SPhilippe Mathieu-Daudé     TCO_LOCK             = 1 << 12,
39*fbae27e8SPhilippe Mathieu-Daudé     TCO_TMR_HLT          = 1 << 11,
40*fbae27e8SPhilippe Mathieu-Daudé     TCO_TIMEOUT          = 1 << 3,
41*fbae27e8SPhilippe Mathieu-Daudé     TCO_SECOND_TO_STS    = 1 << 1,
42*fbae27e8SPhilippe Mathieu-Daudé     TCO_BOOT_STS         = 1 << 2,
43*fbae27e8SPhilippe Mathieu-Daudé };
44*fbae27e8SPhilippe Mathieu-Daudé 
45*fbae27e8SPhilippe Mathieu-Daudé /* TCO I/O registers mask bits */
46*fbae27e8SPhilippe Mathieu-Daudé enum {
47*fbae27e8SPhilippe Mathieu-Daudé     TCO_RLD_MASK     = 0x3ff,
48*fbae27e8SPhilippe Mathieu-Daudé     TCO1_STS_MASK    = 0xe870,
49*fbae27e8SPhilippe Mathieu-Daudé     TCO2_STS_MASK    = 0xfff8,
50*fbae27e8SPhilippe Mathieu-Daudé     TCO1_CNT_MASK    = 0xfeff,
51*fbae27e8SPhilippe Mathieu-Daudé     TCO_TMR_MASK     = 0x3ff,
52*fbae27e8SPhilippe Mathieu-Daudé };
53*fbae27e8SPhilippe Mathieu-Daudé 
54*fbae27e8SPhilippe Mathieu-Daudé typedef struct TCOIORegs {
55*fbae27e8SPhilippe Mathieu-Daudé     struct {
56*fbae27e8SPhilippe Mathieu-Daudé         uint16_t rld;
57*fbae27e8SPhilippe Mathieu-Daudé         uint8_t din;
58*fbae27e8SPhilippe Mathieu-Daudé         uint8_t dout;
59*fbae27e8SPhilippe Mathieu-Daudé         uint16_t sts1;
60*fbae27e8SPhilippe Mathieu-Daudé         uint16_t sts2;
61*fbae27e8SPhilippe Mathieu-Daudé         uint16_t cnt1;
62*fbae27e8SPhilippe Mathieu-Daudé         uint16_t cnt2;
63*fbae27e8SPhilippe Mathieu-Daudé         uint8_t msg1;
64*fbae27e8SPhilippe Mathieu-Daudé         uint8_t msg2;
65*fbae27e8SPhilippe Mathieu-Daudé         uint8_t wdcnt;
66*fbae27e8SPhilippe Mathieu-Daudé         uint16_t tmr;
67*fbae27e8SPhilippe Mathieu-Daudé     } tco;
68*fbae27e8SPhilippe Mathieu-Daudé     uint8_t sw_irq_gen;
69*fbae27e8SPhilippe Mathieu-Daudé 
70*fbae27e8SPhilippe Mathieu-Daudé     QEMUTimer *tco_timer;
71*fbae27e8SPhilippe Mathieu-Daudé     int64_t expire_time;
72*fbae27e8SPhilippe Mathieu-Daudé     uint8_t timeouts_no;
73*fbae27e8SPhilippe Mathieu-Daudé 
74*fbae27e8SPhilippe Mathieu-Daudé     MemoryRegion io;
75*fbae27e8SPhilippe Mathieu-Daudé } TCOIORegs;
76*fbae27e8SPhilippe Mathieu-Daudé 
77*fbae27e8SPhilippe Mathieu-Daudé /* tco.c */
78*fbae27e8SPhilippe Mathieu-Daudé void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent);
79*fbae27e8SPhilippe Mathieu-Daudé 
80*fbae27e8SPhilippe Mathieu-Daudé extern const VMStateDescription vmstate_tco_io_sts;
81*fbae27e8SPhilippe Mathieu-Daudé 
82*fbae27e8SPhilippe Mathieu-Daudé #endif /* HW_ACPI_TCO_H */
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