1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "qemu/host-utils.h" 27 #include "qemu/thread.h" 28 #ifndef CONFIG_USER_ONLY 29 #include "exec/hwaddr.h" 30 #endif 31 #include "exec/memattrs.h" 32 #include "hw/core/cpu.h" 33 34 #include "cpu-param.h" 35 36 #ifndef TARGET_LONG_BITS 37 # error TARGET_LONG_BITS must be defined in cpu-param.h 38 #endif 39 #ifndef TARGET_PHYS_ADDR_SPACE_BITS 40 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h 41 #endif 42 #ifndef TARGET_VIRT_ADDR_SPACE_BITS 43 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h 44 #endif 45 #ifndef TARGET_PAGE_BITS 46 # ifdef TARGET_PAGE_BITS_VARY 47 # ifndef TARGET_PAGE_BITS_MIN 48 # error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h 49 # endif 50 # else 51 # error TARGET_PAGE_BITS must be defined in cpu-param.h 52 # endif 53 #endif 54 55 #include "exec/target_long.h" 56 57 /* 58 * Fix the number of mmu modes to 16, which is also the maximum 59 * supported by the softmmu tlb api. 60 */ 61 #ifndef NB_MMU_MODES 62 #define NB_MMU_MODES 16 63 #endif 64 65 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 66 67 /* use a fully associative victim tlb of 8 entries */ 68 #define CPU_VTLB_SIZE 8 69 70 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 71 #define CPU_TLB_ENTRY_BITS 4 72 #else 73 #define CPU_TLB_ENTRY_BITS 5 74 #endif 75 76 #define CPU_TLB_DYN_MIN_BITS 6 77 #define CPU_TLB_DYN_DEFAULT_BITS 8 78 79 # if HOST_LONG_BITS == 32 80 /* Make sure we do not require a double-word shift for the TLB load */ 81 # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 82 # else /* HOST_LONG_BITS == 64 */ 83 /* 84 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 85 * 2**34 == 16G of address space. This is roughly what one would expect a 86 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 87 * Skylake's Level-2 STLB has 16 1G entries. 88 * Also, make sure we do not size the TLB past the guest's address space. 89 */ 90 # ifdef TARGET_PAGE_BITS_VARY 91 # define CPU_TLB_DYN_MAX_BITS \ 92 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 93 # else 94 # define CPU_TLB_DYN_MAX_BITS \ 95 MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 96 # endif 97 # endif 98 99 /* Minimalized TLB entry for use by TCG fast path. */ 100 typedef struct CPUTLBEntry { 101 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 102 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 103 go directly to ram. 104 bit 3 : indicates that the entry is invalid 105 bit 2..0 : zero 106 */ 107 union { 108 struct { 109 target_ulong addr_read; 110 target_ulong addr_write; 111 target_ulong addr_code; 112 /* Addend to virtual address to get host address. IO accesses 113 use the corresponding iotlb value. */ 114 uintptr_t addend; 115 }; 116 /* padding to get a power of two size */ 117 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; 118 }; 119 } CPUTLBEntry; 120 121 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 122 123 124 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 125 126 #if !defined(CONFIG_USER_ONLY) 127 /* 128 * The full TLB entry, which is not accessed by generated TCG code, 129 * so the layout is not as critical as that of CPUTLBEntry. This is 130 * also why we don't want to combine the two structs. 131 */ 132 typedef struct CPUTLBEntryFull { 133 /* 134 * @xlat_section contains: 135 * - in the lower TARGET_PAGE_BITS, a physical section number 136 * - with the lower TARGET_PAGE_BITS masked off, an offset which 137 * must be added to the virtual address to obtain: 138 * + the ram_addr_t of the target RAM (if the physical section 139 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) 140 * + the offset within the target MemoryRegion (otherwise) 141 */ 142 hwaddr xlat_section; 143 144 /* 145 * @phys_addr contains the physical address in the address space 146 * given by cpu_asidx_from_attrs(cpu, @attrs). 147 */ 148 hwaddr phys_addr; 149 150 /* @attrs contains the memory transaction attributes for the page. */ 151 MemTxAttrs attrs; 152 153 /* @prot contains the complete protections for the page. */ 154 uint8_t prot; 155 156 /* @lg_page_size contains the log2 of the page size. */ 157 uint8_t lg_page_size; 158 159 /* 160 * Allow target-specific additions to this structure. 161 * This may be used to cache items from the guest cpu 162 * page tables for later use by the implementation. 163 */ 164 #ifdef TARGET_PAGE_ENTRY_EXTRA 165 TARGET_PAGE_ENTRY_EXTRA 166 #endif 167 } CPUTLBEntryFull; 168 #endif /* !CONFIG_USER_ONLY */ 169 170 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 171 /* 172 * Data elements that are per MMU mode, minus the bits accessed by 173 * the TCG fast path. 174 */ 175 typedef struct CPUTLBDesc { 176 /* 177 * Describe a region covering all of the large pages allocated 178 * into the tlb. When any page within this region is flushed, 179 * we must flush the entire tlb. The region is matched if 180 * (addr & large_page_mask) == large_page_addr. 181 */ 182 target_ulong large_page_addr; 183 target_ulong large_page_mask; 184 /* host time (in ns) at the beginning of the time window */ 185 int64_t window_begin_ns; 186 /* maximum number of entries observed in the window */ 187 size_t window_max_entries; 188 size_t n_used_entries; 189 /* The next index to use in the tlb victim table. */ 190 size_t vindex; 191 /* The tlb victim table, in two parts. */ 192 CPUTLBEntry vtable[CPU_VTLB_SIZE]; 193 CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; 194 CPUTLBEntryFull *fulltlb; 195 } CPUTLBDesc; 196 197 /* 198 * Data elements that are per MMU mode, accessed by the fast path. 199 * The structure is aligned to aid loading the pair with one insn. 200 */ 201 typedef struct CPUTLBDescFast { 202 /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ 203 uintptr_t mask; 204 /* The array of tlb entries itself. */ 205 CPUTLBEntry *table; 206 } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); 207 208 /* 209 * Data elements that are shared between all MMU modes. 210 */ 211 typedef struct CPUTLBCommon { 212 /* Serialize updates to f.table and d.vtable, and others as noted. */ 213 QemuSpin lock; 214 /* 215 * Within dirty, for each bit N, modifications have been made to 216 * mmu_idx N since the last time that mmu_idx was flushed. 217 * Protected by tlb_c.lock. 218 */ 219 uint16_t dirty; 220 /* 221 * Statistics. These are not lock protected, but are read and 222 * written atomically. This allows the monitor to print a snapshot 223 * of the stats without interfering with the cpu. 224 */ 225 size_t full_flush_count; 226 size_t part_flush_count; 227 size_t elide_flush_count; 228 } CPUTLBCommon; 229 230 /* 231 * The entire softmmu tlb, for all MMU modes. 232 * The meaning of each of the MMU modes is defined in the target code. 233 * Since this is placed within CPUNegativeOffsetState, the smallest 234 * negative offsets are at the end of the struct. 235 */ 236 237 typedef struct CPUTLB { 238 CPUTLBCommon c; 239 CPUTLBDesc d[NB_MMU_MODES]; 240 CPUTLBDescFast f[NB_MMU_MODES]; 241 } CPUTLB; 242 243 /* This will be used by TCG backends to compute offsets. */ 244 #define TLB_MASK_TABLE_OFS(IDX) \ 245 ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) 246 247 #else 248 249 typedef struct CPUTLB { } CPUTLB; 250 251 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 252 253 /* 254 * This structure must be placed in ArchCPU immediately 255 * before CPUArchState, as a field named "neg". 256 */ 257 typedef struct CPUNegativeOffsetState { 258 CPUTLB tlb; 259 IcountDecr icount_decr; 260 } CPUNegativeOffsetState; 261 262 #endif 263