xref: /openbmc/qemu/hw/xtensa/sim.c (revision c5ea91da443b458352c1b629b490ee6631775cb4)
1b707ab75SMax Filippov /*
2b707ab75SMax Filippov  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3b707ab75SMax Filippov  * All rights reserved.
4b707ab75SMax Filippov  *
5b707ab75SMax Filippov  * Redistribution and use in source and binary forms, with or without
6b707ab75SMax Filippov  * modification, are permitted provided that the following conditions are met:
7b707ab75SMax Filippov  *     * Redistributions of source code must retain the above copyright
8b707ab75SMax Filippov  *       notice, this list of conditions and the following disclaimer.
9b707ab75SMax Filippov  *     * Redistributions in binary form must reproduce the above copyright
10b707ab75SMax Filippov  *       notice, this list of conditions and the following disclaimer in the
11b707ab75SMax Filippov  *       documentation and/or other materials provided with the distribution.
12b707ab75SMax Filippov  *     * Neither the name of the Open Source and Linux Lab nor the
13b707ab75SMax Filippov  *       names of its contributors may be used to endorse or promote products
14b707ab75SMax Filippov  *       derived from this software without specific prior written permission.
15b707ab75SMax Filippov  *
16b707ab75SMax Filippov  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17b707ab75SMax Filippov  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18b707ab75SMax Filippov  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19b707ab75SMax Filippov  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20b707ab75SMax Filippov  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21b707ab75SMax Filippov  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22b707ab75SMax Filippov  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23b707ab75SMax Filippov  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24b707ab75SMax Filippov  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25b707ab75SMax Filippov  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26b707ab75SMax Filippov  */
27b707ab75SMax Filippov 
2809aae23dSPeter Maydell #include "qemu/osdep.h"
29da34e65cSMarkus Armbruster #include "qapi/error.h"
3071e8a915SMarkus Armbruster #include "sysemu/reset.h"
31b707ab75SMax Filippov #include "sysemu/sysemu.h"
32b707ab75SMax Filippov #include "hw/boards.h"
33b707ab75SMax Filippov #include "hw/loader.h"
34b707ab75SMax Filippov #include "elf.h"
35b707ab75SMax Filippov #include "exec/memory.h"
368488ab02SMax Filippov #include "qemu/error-report.h"
37e53fa62cSMax Filippov #include "xtensa_memory.h"
38d9e8553bSMax Filippov #include "xtensa_sim.h"
39b68755c1SMax Filippov 
translate_phys_addr(void * opaque,uint64_t addr)40b707ab75SMax Filippov static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
41b707ab75SMax Filippov {
42b707ab75SMax Filippov     XtensaCPU *cpu = opaque;
43b707ab75SMax Filippov 
44b707ab75SMax Filippov     return cpu_get_phys_page_debug(CPU(cpu), addr);
45b707ab75SMax Filippov }
46b707ab75SMax Filippov 
sim_reset(void * opaque)47b707ab75SMax Filippov static void sim_reset(void *opaque)
48b707ab75SMax Filippov {
49b707ab75SMax Filippov     XtensaCPU *cpu = opaque;
50b707ab75SMax Filippov 
51b707ab75SMax Filippov     cpu_reset(CPU(cpu));
52b707ab75SMax Filippov }
53b707ab75SMax Filippov 
xtensa_sim_common_init(MachineState * machine)54d9e8553bSMax Filippov XtensaCPU *xtensa_sim_common_init(MachineState *machine)
55b707ab75SMax Filippov {
56b707ab75SMax Filippov     XtensaCPU *cpu = NULL;
57b707ab75SMax Filippov     CPUXtensaState *env = NULL;
58b707ab75SMax Filippov     ram_addr_t ram_size = machine->ram_size;
59b707ab75SMax Filippov     int n;
60b707ab75SMax Filippov 
6133decbd2SLike Xu     for (n = 0; n < machine->smp.cpus; n++) {
62d58eeae3SIgor Mammedov         cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
63b707ab75SMax Filippov         env = &cpu->env;
64b707ab75SMax Filippov 
65b707ab75SMax Filippov         env->sregs[PRID] = n;
66b707ab75SMax Filippov         qemu_register_reset(sim_reset, cpu);
67b707ab75SMax Filippov         /* Need MMU initialized prior to ELF loading,
68b707ab75SMax Filippov          * so that ELF gets loaded into virtual addresses
69b707ab75SMax Filippov          */
70b707ab75SMax Filippov         sim_reset(cpu);
71b707ab75SMax Filippov     }
72b707ab75SMax Filippov 
73b68755c1SMax Filippov     if (env) {
74b68755c1SMax Filippov         XtensaMemory sysram = env->config->sysram;
75b707ab75SMax Filippov 
76b68755c1SMax Filippov         sysram.location[0].size = ram_size;
77e53fa62cSMax Filippov         xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
78e53fa62cSMax Filippov                                      get_system_memory());
79e53fa62cSMax Filippov         xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
80e53fa62cSMax Filippov                                      get_system_memory());
81e53fa62cSMax Filippov         xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
82e53fa62cSMax Filippov                                      get_system_memory());
83e53fa62cSMax Filippov         xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
84e53fa62cSMax Filippov                                      get_system_memory());
85e53fa62cSMax Filippov         xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
86e53fa62cSMax Filippov                                      get_system_memory());
87e53fa62cSMax Filippov         xtensa_create_memory_regions(&sysram, "xtensa.sysram",
88e53fa62cSMax Filippov                                      get_system_memory());
89b68755c1SMax Filippov     }
909bca0edbSPeter Maydell     if (serial_hd(0)) {
919bca0edbSPeter Maydell         xtensa_sim_open_console(serial_hd(0));
928128b3e0SMax Filippov     }
93d9e8553bSMax Filippov     return cpu;
94d9e8553bSMax Filippov }
95d9e8553bSMax Filippov 
xtensa_sim_load_kernel(XtensaCPU * cpu,MachineState * machine)96d9e8553bSMax Filippov void xtensa_sim_load_kernel(XtensaCPU *cpu, MachineState *machine)
97d9e8553bSMax Filippov {
98d9e8553bSMax Filippov     const char *kernel_filename = machine->kernel_filename;
99d9e8553bSMax Filippov 
100b707ab75SMax Filippov     if (kernel_filename) {
101b707ab75SMax Filippov         uint64_t elf_entry;
102d9e8553bSMax Filippov         int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
103*ded625e7SThomas Huth                                &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN,
104d9e8553bSMax Filippov                                EM_XTENSA, 0, 0);
105d9e8553bSMax Filippov 
106b707ab75SMax Filippov         if (success > 0) {
107d9e8553bSMax Filippov             cpu->env.pc = elf_entry;
108b707ab75SMax Filippov         }
109b707ab75SMax Filippov     }
110b707ab75SMax Filippov }
111b707ab75SMax Filippov 
xtensa_sim_init(MachineState * machine)112d9e8553bSMax Filippov static void xtensa_sim_init(MachineState *machine)
113d9e8553bSMax Filippov {
114d9e8553bSMax Filippov     XtensaCPU *cpu = xtensa_sim_common_init(machine);
115d9e8553bSMax Filippov 
116d9e8553bSMax Filippov     xtensa_sim_load_kernel(cpu, machine);
117d9e8553bSMax Filippov }
118d9e8553bSMax Filippov 
xtensa_sim_machine_init(MachineClass * mc)119e264d29dSEduardo Habkost static void xtensa_sim_machine_init(MachineClass *mc)
120b707ab75SMax Filippov {
121e264d29dSEduardo Habkost     mc->desc = "sim machine (" XTENSA_DEFAULT_CPU_MODEL ")";
122e264d29dSEduardo Habkost     mc->is_default = true;
123e264d29dSEduardo Habkost     mc->init = xtensa_sim_init;
124e264d29dSEduardo Habkost     mc->max_cpus = 4;
1258128b3e0SMax Filippov     mc->no_serial = 1;
126d58eeae3SIgor Mammedov     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
127b707ab75SMax Filippov }
128b707ab75SMax Filippov 
129e264d29dSEduardo Habkost DEFINE_MACHINE("sim", xtensa_sim_machine_init)
130