1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/pci.h" 31 #include "qemu-timer.h" 32 #include "iov.h" 33 #include "dma.h" 34 #include "trace.h" 35 36 //#define DEBUG 37 //#define DEBUG_DUMP_DATA 38 39 #define UHCI_CMD_FGR (1 << 4) 40 #define UHCI_CMD_EGSM (1 << 3) 41 #define UHCI_CMD_GRESET (1 << 2) 42 #define UHCI_CMD_HCRESET (1 << 1) 43 #define UHCI_CMD_RS (1 << 0) 44 45 #define UHCI_STS_HCHALTED (1 << 5) 46 #define UHCI_STS_HCPERR (1 << 4) 47 #define UHCI_STS_HSERR (1 << 3) 48 #define UHCI_STS_RD (1 << 2) 49 #define UHCI_STS_USBERR (1 << 1) 50 #define UHCI_STS_USBINT (1 << 0) 51 52 #define TD_CTRL_SPD (1 << 29) 53 #define TD_CTRL_ERROR_SHIFT 27 54 #define TD_CTRL_IOS (1 << 25) 55 #define TD_CTRL_IOC (1 << 24) 56 #define TD_CTRL_ACTIVE (1 << 23) 57 #define TD_CTRL_STALL (1 << 22) 58 #define TD_CTRL_BABBLE (1 << 20) 59 #define TD_CTRL_NAK (1 << 19) 60 #define TD_CTRL_TIMEOUT (1 << 18) 61 62 #define UHCI_PORT_SUSPEND (1 << 12) 63 #define UHCI_PORT_RESET (1 << 9) 64 #define UHCI_PORT_LSDA (1 << 8) 65 #define UHCI_PORT_RD (1 << 6) 66 #define UHCI_PORT_ENC (1 << 3) 67 #define UHCI_PORT_EN (1 << 2) 68 #define UHCI_PORT_CSC (1 << 1) 69 #define UHCI_PORT_CCS (1 << 0) 70 71 #define UHCI_PORT_READ_ONLY (0x1bb) 72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) 73 74 #define FRAME_TIMER_FREQ 1000 75 76 #define FRAME_MAX_LOOPS 256 77 78 #define NB_PORTS 2 79 80 enum { 81 TD_RESULT_STOP_FRAME = -1, 82 TD_RESULT_COMPLETE = 0, 83 TD_RESULT_NEXT_QH = 1, 84 TD_RESULT_ASYNC = 2, 85 }; 86 87 typedef struct UHCIState UHCIState; 88 typedef struct UHCIAsync UHCIAsync; 89 typedef struct UHCIQueue UHCIQueue; 90 91 /* 92 * Pending async transaction. 93 * 'packet' must be the first field because completion 94 * handler does "(UHCIAsync *) pkt" cast. 95 */ 96 97 struct UHCIAsync { 98 USBPacket packet; 99 QEMUSGList sgl; 100 UHCIQueue *queue; 101 QTAILQ_ENTRY(UHCIAsync) next; 102 uint32_t td; 103 uint8_t isoc; 104 uint8_t done; 105 }; 106 107 struct UHCIQueue { 108 uint32_t token; 109 UHCIState *uhci; 110 QTAILQ_ENTRY(UHCIQueue) next; 111 QTAILQ_HEAD(, UHCIAsync) asyncs; 112 int8_t valid; 113 }; 114 115 typedef struct UHCIPort { 116 USBPort port; 117 uint16_t ctrl; 118 } UHCIPort; 119 120 struct UHCIState { 121 PCIDevice dev; 122 MemoryRegion io_bar; 123 USBBus bus; /* Note unused when we're a companion controller */ 124 uint16_t cmd; /* cmd register */ 125 uint16_t status; 126 uint16_t intr; /* interrupt enable register */ 127 uint16_t frnum; /* frame number */ 128 uint32_t fl_base_addr; /* frame list base address */ 129 uint8_t sof_timing; 130 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 131 int64_t expire_time; 132 QEMUTimer *frame_timer; 133 UHCIPort ports[NB_PORTS]; 134 135 /* Interrupts that should be raised at the end of the current frame. */ 136 uint32_t pending_int_mask; 137 138 /* Active packets */ 139 QTAILQ_HEAD(, UHCIQueue) queues; 140 uint8_t num_ports_vmstate; 141 142 /* Properties */ 143 char *masterbus; 144 uint32_t firstport; 145 }; 146 147 typedef struct UHCI_TD { 148 uint32_t link; 149 uint32_t ctrl; /* see TD_CTRL_xxx */ 150 uint32_t token; 151 uint32_t buffer; 152 } UHCI_TD; 153 154 typedef struct UHCI_QH { 155 uint32_t link; 156 uint32_t el_link; 157 } UHCI_QH; 158 159 static inline int32_t uhci_queue_token(UHCI_TD *td) 160 { 161 /* covers ep, dev, pid -> identifies the endpoint */ 162 return td->token & 0x7ffff; 163 } 164 165 static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td) 166 { 167 uint32_t token = uhci_queue_token(td); 168 UHCIQueue *queue; 169 170 QTAILQ_FOREACH(queue, &s->queues, next) { 171 if (queue->token == token) { 172 return queue; 173 } 174 } 175 176 queue = g_new0(UHCIQueue, 1); 177 queue->uhci = s; 178 queue->token = token; 179 QTAILQ_INIT(&queue->asyncs); 180 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 181 trace_usb_uhci_queue_add(queue->token); 182 return queue; 183 } 184 185 static void uhci_queue_free(UHCIQueue *queue) 186 { 187 UHCIState *s = queue->uhci; 188 189 trace_usb_uhci_queue_del(queue->token); 190 QTAILQ_REMOVE(&s->queues, queue, next); 191 g_free(queue); 192 } 193 194 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr) 195 { 196 UHCIAsync *async = g_new0(UHCIAsync, 1); 197 198 async->queue = queue; 199 async->td = addr; 200 usb_packet_init(&async->packet); 201 pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1); 202 trace_usb_uhci_packet_add(async->queue->token, async->td); 203 204 return async; 205 } 206 207 static void uhci_async_free(UHCIAsync *async) 208 { 209 trace_usb_uhci_packet_del(async->queue->token, async->td); 210 usb_packet_cleanup(&async->packet); 211 qemu_sglist_destroy(&async->sgl); 212 g_free(async); 213 } 214 215 static void uhci_async_link(UHCIAsync *async) 216 { 217 UHCIQueue *queue = async->queue; 218 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 219 trace_usb_uhci_packet_link_async(async->queue->token, async->td); 220 } 221 222 static void uhci_async_unlink(UHCIAsync *async) 223 { 224 UHCIQueue *queue = async->queue; 225 QTAILQ_REMOVE(&queue->asyncs, async, next); 226 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td); 227 } 228 229 static void uhci_async_cancel(UHCIAsync *async) 230 { 231 trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done); 232 if (!async->done) 233 usb_cancel_packet(&async->packet); 234 uhci_async_free(async); 235 } 236 237 /* 238 * Mark all outstanding async packets as invalid. 239 * This is used for canceling them when TDs are removed by the HCD. 240 */ 241 static void uhci_async_validate_begin(UHCIState *s) 242 { 243 UHCIQueue *queue; 244 245 QTAILQ_FOREACH(queue, &s->queues, next) { 246 queue->valid--; 247 } 248 } 249 250 /* 251 * Cancel async packets that are no longer valid 252 */ 253 static void uhci_async_validate_end(UHCIState *s) 254 { 255 UHCIQueue *queue, *n; 256 UHCIAsync *async; 257 258 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 259 if (queue->valid > 0) { 260 continue; 261 } 262 while (!QTAILQ_EMPTY(&queue->asyncs)) { 263 async = QTAILQ_FIRST(&queue->asyncs); 264 uhci_async_unlink(async); 265 uhci_async_cancel(async); 266 } 267 uhci_queue_free(queue); 268 } 269 } 270 271 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 272 { 273 UHCIQueue *queue; 274 UHCIAsync *curr, *n; 275 276 QTAILQ_FOREACH(queue, &s->queues, next) { 277 QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { 278 if (!usb_packet_is_inflight(&curr->packet) || 279 curr->packet.ep->dev != dev) { 280 continue; 281 } 282 uhci_async_unlink(curr); 283 uhci_async_cancel(curr); 284 } 285 } 286 } 287 288 static void uhci_async_cancel_all(UHCIState *s) 289 { 290 UHCIQueue *queue; 291 UHCIAsync *curr, *n; 292 293 QTAILQ_FOREACH(queue, &s->queues, next) { 294 QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { 295 uhci_async_unlink(curr); 296 uhci_async_cancel(curr); 297 } 298 uhci_queue_free(queue); 299 } 300 } 301 302 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td) 303 { 304 uint32_t token = uhci_queue_token(td); 305 UHCIQueue *queue; 306 UHCIAsync *async; 307 308 QTAILQ_FOREACH(queue, &s->queues, next) { 309 if (queue->token == token) { 310 break; 311 } 312 } 313 if (queue == NULL) { 314 return NULL; 315 } 316 317 QTAILQ_FOREACH(async, &queue->asyncs, next) { 318 if (async->td == addr) { 319 return async; 320 } 321 } 322 323 return NULL; 324 } 325 326 static void uhci_update_irq(UHCIState *s) 327 { 328 int level; 329 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 330 ((s->status2 & 2) && (s->intr & (1 << 3))) || 331 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 332 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 333 (s->status & UHCI_STS_HSERR) || 334 (s->status & UHCI_STS_HCPERR)) { 335 level = 1; 336 } else { 337 level = 0; 338 } 339 qemu_set_irq(s->dev.irq[3], level); 340 } 341 342 static void uhci_reset(void *opaque) 343 { 344 UHCIState *s = opaque; 345 uint8_t *pci_conf; 346 int i; 347 UHCIPort *port; 348 349 trace_usb_uhci_reset(); 350 351 pci_conf = s->dev.config; 352 353 pci_conf[0x6a] = 0x01; /* usb clock */ 354 pci_conf[0x6b] = 0x00; 355 s->cmd = 0; 356 s->status = 0; 357 s->status2 = 0; 358 s->intr = 0; 359 s->fl_base_addr = 0; 360 s->sof_timing = 64; 361 362 for(i = 0; i < NB_PORTS; i++) { 363 port = &s->ports[i]; 364 port->ctrl = 0x0080; 365 if (port->port.dev && port->port.dev->attached) { 366 usb_port_reset(&port->port); 367 } 368 } 369 370 uhci_async_cancel_all(s); 371 } 372 373 static void uhci_pre_save(void *opaque) 374 { 375 UHCIState *s = opaque; 376 377 uhci_async_cancel_all(s); 378 } 379 380 static const VMStateDescription vmstate_uhci_port = { 381 .name = "uhci port", 382 .version_id = 1, 383 .minimum_version_id = 1, 384 .minimum_version_id_old = 1, 385 .fields = (VMStateField []) { 386 VMSTATE_UINT16(ctrl, UHCIPort), 387 VMSTATE_END_OF_LIST() 388 } 389 }; 390 391 static const VMStateDescription vmstate_uhci = { 392 .name = "uhci", 393 .version_id = 2, 394 .minimum_version_id = 1, 395 .minimum_version_id_old = 1, 396 .pre_save = uhci_pre_save, 397 .fields = (VMStateField []) { 398 VMSTATE_PCI_DEVICE(dev, UHCIState), 399 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 400 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 401 vmstate_uhci_port, UHCIPort), 402 VMSTATE_UINT16(cmd, UHCIState), 403 VMSTATE_UINT16(status, UHCIState), 404 VMSTATE_UINT16(intr, UHCIState), 405 VMSTATE_UINT16(frnum, UHCIState), 406 VMSTATE_UINT32(fl_base_addr, UHCIState), 407 VMSTATE_UINT8(sof_timing, UHCIState), 408 VMSTATE_UINT8(status2, UHCIState), 409 VMSTATE_TIMER(frame_timer, UHCIState), 410 VMSTATE_INT64_V(expire_time, UHCIState, 2), 411 VMSTATE_END_OF_LIST() 412 } 413 }; 414 415 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) 416 { 417 UHCIState *s = opaque; 418 419 addr &= 0x1f; 420 switch(addr) { 421 case 0x0c: 422 s->sof_timing = val; 423 break; 424 } 425 } 426 427 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) 428 { 429 UHCIState *s = opaque; 430 uint32_t val; 431 432 addr &= 0x1f; 433 switch(addr) { 434 case 0x0c: 435 val = s->sof_timing; 436 break; 437 default: 438 val = 0xff; 439 break; 440 } 441 return val; 442 } 443 444 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) 445 { 446 UHCIState *s = opaque; 447 448 addr &= 0x1f; 449 trace_usb_uhci_mmio_writew(addr, val); 450 451 switch(addr) { 452 case 0x00: 453 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 454 /* start frame processing */ 455 trace_usb_uhci_schedule_start(); 456 s->expire_time = qemu_get_clock_ns(vm_clock) + 457 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 458 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); 459 s->status &= ~UHCI_STS_HCHALTED; 460 } else if (!(val & UHCI_CMD_RS)) { 461 s->status |= UHCI_STS_HCHALTED; 462 } 463 if (val & UHCI_CMD_GRESET) { 464 UHCIPort *port; 465 int i; 466 467 /* send reset on the USB bus */ 468 for(i = 0; i < NB_PORTS; i++) { 469 port = &s->ports[i]; 470 usb_device_reset(port->port.dev); 471 } 472 uhci_reset(s); 473 return; 474 } 475 if (val & UHCI_CMD_HCRESET) { 476 uhci_reset(s); 477 return; 478 } 479 s->cmd = val; 480 break; 481 case 0x02: 482 s->status &= ~val; 483 /* XXX: the chip spec is not coherent, so we add a hidden 484 register to distinguish between IOC and SPD */ 485 if (val & UHCI_STS_USBINT) 486 s->status2 = 0; 487 uhci_update_irq(s); 488 break; 489 case 0x04: 490 s->intr = val; 491 uhci_update_irq(s); 492 break; 493 case 0x06: 494 if (s->status & UHCI_STS_HCHALTED) 495 s->frnum = val & 0x7ff; 496 break; 497 case 0x10 ... 0x1f: 498 { 499 UHCIPort *port; 500 USBDevice *dev; 501 int n; 502 503 n = (addr >> 1) & 7; 504 if (n >= NB_PORTS) 505 return; 506 port = &s->ports[n]; 507 dev = port->port.dev; 508 if (dev && dev->attached) { 509 /* port reset */ 510 if ( (val & UHCI_PORT_RESET) && 511 !(port->ctrl & UHCI_PORT_RESET) ) { 512 usb_device_reset(dev); 513 } 514 } 515 port->ctrl &= UHCI_PORT_READ_ONLY; 516 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 517 /* some bits are reset when a '1' is written to them */ 518 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 519 } 520 break; 521 } 522 } 523 524 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) 525 { 526 UHCIState *s = opaque; 527 uint32_t val; 528 529 addr &= 0x1f; 530 switch(addr) { 531 case 0x00: 532 val = s->cmd; 533 break; 534 case 0x02: 535 val = s->status; 536 break; 537 case 0x04: 538 val = s->intr; 539 break; 540 case 0x06: 541 val = s->frnum; 542 break; 543 case 0x10 ... 0x1f: 544 { 545 UHCIPort *port; 546 int n; 547 n = (addr >> 1) & 7; 548 if (n >= NB_PORTS) 549 goto read_default; 550 port = &s->ports[n]; 551 val = port->ctrl; 552 } 553 break; 554 default: 555 read_default: 556 val = 0xff7f; /* disabled port */ 557 break; 558 } 559 560 trace_usb_uhci_mmio_readw(addr, val); 561 562 return val; 563 } 564 565 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) 566 { 567 UHCIState *s = opaque; 568 569 addr &= 0x1f; 570 trace_usb_uhci_mmio_writel(addr, val); 571 572 switch(addr) { 573 case 0x08: 574 s->fl_base_addr = val & ~0xfff; 575 break; 576 } 577 } 578 579 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) 580 { 581 UHCIState *s = opaque; 582 uint32_t val; 583 584 addr &= 0x1f; 585 switch(addr) { 586 case 0x08: 587 val = s->fl_base_addr; 588 break; 589 default: 590 val = 0xffffffff; 591 break; 592 } 593 trace_usb_uhci_mmio_readl(addr, val); 594 return val; 595 } 596 597 /* signal resume if controller suspended */ 598 static void uhci_resume (void *opaque) 599 { 600 UHCIState *s = (UHCIState *)opaque; 601 602 if (!s) 603 return; 604 605 if (s->cmd & UHCI_CMD_EGSM) { 606 s->cmd |= UHCI_CMD_FGR; 607 s->status |= UHCI_STS_RD; 608 uhci_update_irq(s); 609 } 610 } 611 612 static void uhci_attach(USBPort *port1) 613 { 614 UHCIState *s = port1->opaque; 615 UHCIPort *port = &s->ports[port1->index]; 616 617 /* set connect status */ 618 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 619 620 /* update speed */ 621 if (port->port.dev->speed == USB_SPEED_LOW) { 622 port->ctrl |= UHCI_PORT_LSDA; 623 } else { 624 port->ctrl &= ~UHCI_PORT_LSDA; 625 } 626 627 uhci_resume(s); 628 } 629 630 static void uhci_detach(USBPort *port1) 631 { 632 UHCIState *s = port1->opaque; 633 UHCIPort *port = &s->ports[port1->index]; 634 635 uhci_async_cancel_device(s, port1->dev); 636 637 /* set connect status */ 638 if (port->ctrl & UHCI_PORT_CCS) { 639 port->ctrl &= ~UHCI_PORT_CCS; 640 port->ctrl |= UHCI_PORT_CSC; 641 } 642 /* disable port */ 643 if (port->ctrl & UHCI_PORT_EN) { 644 port->ctrl &= ~UHCI_PORT_EN; 645 port->ctrl |= UHCI_PORT_ENC; 646 } 647 648 uhci_resume(s); 649 } 650 651 static void uhci_child_detach(USBPort *port1, USBDevice *child) 652 { 653 UHCIState *s = port1->opaque; 654 655 uhci_async_cancel_device(s, child); 656 } 657 658 static void uhci_wakeup(USBPort *port1) 659 { 660 UHCIState *s = port1->opaque; 661 UHCIPort *port = &s->ports[port1->index]; 662 663 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 664 port->ctrl |= UHCI_PORT_RD; 665 uhci_resume(s); 666 } 667 } 668 669 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 670 { 671 USBDevice *dev; 672 int i; 673 674 for (i = 0; i < NB_PORTS; i++) { 675 UHCIPort *port = &s->ports[i]; 676 if (!(port->ctrl & UHCI_PORT_EN)) { 677 continue; 678 } 679 dev = usb_find_device(&port->port, addr); 680 if (dev != NULL) { 681 return dev; 682 } 683 } 684 return NULL; 685 } 686 687 static void uhci_async_complete(USBPort *port, USBPacket *packet); 688 static void uhci_process_frame(UHCIState *s); 689 690 /* return -1 if fatal error (frame must be stopped) 691 0 if TD successful 692 1 if TD unsuccessful or inactive 693 */ 694 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 695 { 696 int len = 0, max_len, err, ret; 697 uint8_t pid; 698 699 max_len = ((td->token >> 21) + 1) & 0x7ff; 700 pid = td->token & 0xff; 701 702 ret = async->packet.result; 703 704 if (td->ctrl & TD_CTRL_IOS) 705 td->ctrl &= ~TD_CTRL_ACTIVE; 706 707 if (ret < 0) 708 goto out; 709 710 len = async->packet.result; 711 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 712 713 /* The NAK bit may have been set by a previous frame, so clear it 714 here. The docs are somewhat unclear, but win2k relies on this 715 behavior. */ 716 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 717 if (td->ctrl & TD_CTRL_IOC) 718 *int_mask |= 0x01; 719 720 if (pid == USB_TOKEN_IN) { 721 if (len > max_len) { 722 ret = USB_RET_BABBLE; 723 goto out; 724 } 725 726 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 727 *int_mask |= 0x02; 728 /* short packet: do not update QH */ 729 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 730 async->td); 731 return TD_RESULT_NEXT_QH; 732 } 733 } 734 735 /* success */ 736 trace_usb_uhci_packet_complete_success(async->queue->token, async->td); 737 return TD_RESULT_COMPLETE; 738 739 out: 740 switch(ret) { 741 case USB_RET_STALL: 742 td->ctrl |= TD_CTRL_STALL; 743 td->ctrl &= ~TD_CTRL_ACTIVE; 744 s->status |= UHCI_STS_USBERR; 745 if (td->ctrl & TD_CTRL_IOC) { 746 *int_mask |= 0x01; 747 } 748 uhci_update_irq(s); 749 trace_usb_uhci_packet_complete_stall(async->queue->token, async->td); 750 return TD_RESULT_NEXT_QH; 751 752 case USB_RET_BABBLE: 753 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 754 td->ctrl &= ~TD_CTRL_ACTIVE; 755 s->status |= UHCI_STS_USBERR; 756 if (td->ctrl & TD_CTRL_IOC) { 757 *int_mask |= 0x01; 758 } 759 uhci_update_irq(s); 760 /* frame interrupted */ 761 trace_usb_uhci_packet_complete_babble(async->queue->token, async->td); 762 return TD_RESULT_STOP_FRAME; 763 764 case USB_RET_NAK: 765 td->ctrl |= TD_CTRL_NAK; 766 if (pid == USB_TOKEN_SETUP) 767 break; 768 return TD_RESULT_NEXT_QH; 769 770 case USB_RET_IOERROR: 771 case USB_RET_NODEV: 772 default: 773 break; 774 } 775 776 /* Retry the TD if error count is not zero */ 777 778 td->ctrl |= TD_CTRL_TIMEOUT; 779 err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3; 780 if (err != 0) { 781 err--; 782 if (err == 0) { 783 td->ctrl &= ~TD_CTRL_ACTIVE; 784 s->status |= UHCI_STS_USBERR; 785 if (td->ctrl & TD_CTRL_IOC) 786 *int_mask |= 0x01; 787 uhci_update_irq(s); 788 trace_usb_uhci_packet_complete_error(async->queue->token, 789 async->td); 790 } 791 } 792 td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) | 793 (err << TD_CTRL_ERROR_SHIFT); 794 return TD_RESULT_NEXT_QH; 795 } 796 797 static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) 798 { 799 UHCIAsync *async; 800 int len = 0, max_len; 801 uint8_t pid; 802 USBDevice *dev; 803 USBEndpoint *ep; 804 805 /* Is active ? */ 806 if (!(td->ctrl & TD_CTRL_ACTIVE)) 807 return TD_RESULT_NEXT_QH; 808 809 async = uhci_async_find_td(s, addr, td); 810 if (async) { 811 /* Already submitted */ 812 async->queue->valid = 32; 813 814 if (!async->done) 815 return TD_RESULT_NEXT_QH; 816 817 uhci_async_unlink(async); 818 goto done; 819 } 820 821 /* Allocate new packet */ 822 async = uhci_async_alloc(uhci_queue_get(s, td), addr); 823 if (!async) 824 return TD_RESULT_NEXT_QH; 825 826 /* valid needs to be large enough to handle 10 frame delay 827 * for initial isochronous requests 828 */ 829 async->queue->valid = 32; 830 async->isoc = td->ctrl & TD_CTRL_IOS; 831 832 max_len = ((td->token >> 21) + 1) & 0x7ff; 833 pid = td->token & 0xff; 834 835 dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 836 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 837 usb_packet_setup(&async->packet, pid, ep); 838 qemu_sglist_add(&async->sgl, td->buffer, max_len); 839 usb_packet_map(&async->packet, &async->sgl); 840 841 switch(pid) { 842 case USB_TOKEN_OUT: 843 case USB_TOKEN_SETUP: 844 len = usb_handle_packet(dev, &async->packet); 845 if (len >= 0) 846 len = max_len; 847 break; 848 849 case USB_TOKEN_IN: 850 len = usb_handle_packet(dev, &async->packet); 851 break; 852 853 default: 854 /* invalid pid : frame interrupted */ 855 uhci_async_free(async); 856 s->status |= UHCI_STS_HCPERR; 857 uhci_update_irq(s); 858 return TD_RESULT_STOP_FRAME; 859 } 860 861 if (len == USB_RET_ASYNC) { 862 uhci_async_link(async); 863 return TD_RESULT_ASYNC; 864 } 865 866 async->packet.result = len; 867 868 done: 869 len = uhci_complete_td(s, td, async, int_mask); 870 usb_packet_unmap(&async->packet); 871 uhci_async_free(async); 872 return len; 873 } 874 875 static void uhci_async_complete(USBPort *port, USBPacket *packet) 876 { 877 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 878 UHCIState *s = async->queue->uhci; 879 880 if (async->isoc) { 881 UHCI_TD td; 882 uint32_t link = async->td; 883 uint32_t int_mask = 0, val; 884 885 pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); 886 le32_to_cpus(&td.link); 887 le32_to_cpus(&td.ctrl); 888 le32_to_cpus(&td.token); 889 le32_to_cpus(&td.buffer); 890 891 uhci_async_unlink(async); 892 uhci_complete_td(s, &td, async, &int_mask); 893 s->pending_int_mask |= int_mask; 894 895 /* update the status bits of the TD */ 896 val = cpu_to_le32(td.ctrl); 897 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 898 uhci_async_free(async); 899 } else { 900 async->done = 1; 901 uhci_process_frame(s); 902 } 903 } 904 905 static int is_valid(uint32_t link) 906 { 907 return (link & 1) == 0; 908 } 909 910 static int is_qh(uint32_t link) 911 { 912 return (link & 2) != 0; 913 } 914 915 static int depth_first(uint32_t link) 916 { 917 return (link & 4) != 0; 918 } 919 920 /* QH DB used for detecting QH loops */ 921 #define UHCI_MAX_QUEUES 128 922 typedef struct { 923 uint32_t addr[UHCI_MAX_QUEUES]; 924 int count; 925 } QhDb; 926 927 static void qhdb_reset(QhDb *db) 928 { 929 db->count = 0; 930 } 931 932 /* Add QH to DB. Returns 1 if already present or DB is full. */ 933 static int qhdb_insert(QhDb *db, uint32_t addr) 934 { 935 int i; 936 for (i = 0; i < db->count; i++) 937 if (db->addr[i] == addr) 938 return 1; 939 940 if (db->count >= UHCI_MAX_QUEUES) 941 return 1; 942 943 db->addr[db->count++] = addr; 944 return 0; 945 } 946 947 static void uhci_fill_queue(UHCIState *s, UHCI_TD *td) 948 { 949 uint32_t int_mask = 0; 950 uint32_t plink = td->link; 951 uint32_t token = uhci_queue_token(td); 952 UHCI_TD ptd; 953 int ret; 954 955 while (is_valid(plink)) { 956 pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd)); 957 le32_to_cpus(&ptd.link); 958 le32_to_cpus(&ptd.ctrl); 959 le32_to_cpus(&ptd.token); 960 le32_to_cpus(&ptd.buffer); 961 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 962 break; 963 } 964 if (uhci_queue_token(&ptd) != token) { 965 break; 966 } 967 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 968 ret = uhci_handle_td(s, plink, &ptd, &int_mask); 969 assert(ret == TD_RESULT_ASYNC); 970 assert(int_mask == 0); 971 plink = ptd.link; 972 } 973 } 974 975 static void uhci_process_frame(UHCIState *s) 976 { 977 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 978 uint32_t curr_qh, td_count = 0, bytes_count = 0; 979 int cnt, ret; 980 UHCI_TD td; 981 UHCI_QH qh; 982 QhDb qhdb; 983 984 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 985 986 pci_dma_read(&s->dev, frame_addr, &link, 4); 987 le32_to_cpus(&link); 988 989 int_mask = 0; 990 curr_qh = 0; 991 992 qhdb_reset(&qhdb); 993 994 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 995 if (is_qh(link)) { 996 /* QH */ 997 trace_usb_uhci_qh_load(link & ~0xf); 998 999 if (qhdb_insert(&qhdb, link)) { 1000 /* 1001 * We're going in circles. Which is not a bug because 1002 * HCD is allowed to do that as part of the BW management. 1003 * 1004 * Stop processing here if 1005 * (a) no transaction has been done since we've been 1006 * here last time, or 1007 * (b) we've reached the usb 1.1 bandwidth, which is 1008 * 1280 bytes/frame. 1009 */ 1010 if (td_count == 0) { 1011 trace_usb_uhci_frame_loop_stop_idle(); 1012 break; 1013 } else if (bytes_count >= 1280) { 1014 trace_usb_uhci_frame_loop_stop_bandwidth(); 1015 break; 1016 } else { 1017 trace_usb_uhci_frame_loop_continue(); 1018 td_count = 0; 1019 qhdb_reset(&qhdb); 1020 qhdb_insert(&qhdb, link); 1021 } 1022 } 1023 1024 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1025 le32_to_cpus(&qh.link); 1026 le32_to_cpus(&qh.el_link); 1027 1028 if (!is_valid(qh.el_link)) { 1029 /* QH w/o elements */ 1030 curr_qh = 0; 1031 link = qh.link; 1032 } else { 1033 /* QH with elements */ 1034 curr_qh = link; 1035 link = qh.el_link; 1036 } 1037 continue; 1038 } 1039 1040 /* TD */ 1041 pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); 1042 le32_to_cpus(&td.link); 1043 le32_to_cpus(&td.ctrl); 1044 le32_to_cpus(&td.token); 1045 le32_to_cpus(&td.buffer); 1046 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1047 1048 old_td_ctrl = td.ctrl; 1049 ret = uhci_handle_td(s, link, &td, &int_mask); 1050 if (old_td_ctrl != td.ctrl) { 1051 /* update the status bits of the TD */ 1052 val = cpu_to_le32(td.ctrl); 1053 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1054 } 1055 1056 switch (ret) { 1057 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1058 goto out; 1059 1060 case TD_RESULT_NEXT_QH: 1061 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1062 link = curr_qh ? qh.link : td.link; 1063 continue; 1064 1065 case TD_RESULT_ASYNC: 1066 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1067 if (is_valid(td.link)) { 1068 uhci_fill_queue(s, &td); 1069 } 1070 link = curr_qh ? qh.link : td.link; 1071 continue; 1072 1073 case TD_RESULT_COMPLETE: 1074 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1075 link = td.link; 1076 td_count++; 1077 bytes_count += (td.ctrl & 0x7ff) + 1; 1078 1079 if (curr_qh) { 1080 /* update QH element link */ 1081 qh.el_link = link; 1082 val = cpu_to_le32(qh.el_link); 1083 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1084 1085 if (!depth_first(link)) { 1086 /* done with this QH */ 1087 curr_qh = 0; 1088 link = qh.link; 1089 } 1090 } 1091 break; 1092 1093 default: 1094 assert(!"unknown return code"); 1095 } 1096 1097 /* go to the next entry */ 1098 } 1099 1100 out: 1101 s->pending_int_mask |= int_mask; 1102 } 1103 1104 static void uhci_frame_timer(void *opaque) 1105 { 1106 UHCIState *s = opaque; 1107 1108 /* prepare the timer for the next frame */ 1109 s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); 1110 1111 if (!(s->cmd & UHCI_CMD_RS)) { 1112 /* Full stop */ 1113 trace_usb_uhci_schedule_stop(); 1114 qemu_del_timer(s->frame_timer); 1115 uhci_async_cancel_all(s); 1116 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1117 s->status |= UHCI_STS_HCHALTED; 1118 return; 1119 } 1120 1121 /* Complete the previous frame */ 1122 if (s->pending_int_mask) { 1123 s->status2 |= s->pending_int_mask; 1124 s->status |= UHCI_STS_USBINT; 1125 uhci_update_irq(s); 1126 } 1127 s->pending_int_mask = 0; 1128 1129 /* Start new frame */ 1130 s->frnum = (s->frnum + 1) & 0x7ff; 1131 1132 trace_usb_uhci_frame_start(s->frnum); 1133 1134 uhci_async_validate_begin(s); 1135 1136 uhci_process_frame(s); 1137 1138 uhci_async_validate_end(s); 1139 1140 qemu_mod_timer(s->frame_timer, s->expire_time); 1141 } 1142 1143 static const MemoryRegionPortio uhci_portio[] = { 1144 { 0, 32, 2, .write = uhci_ioport_writew, }, 1145 { 0, 32, 2, .read = uhci_ioport_readw, }, 1146 { 0, 32, 4, .write = uhci_ioport_writel, }, 1147 { 0, 32, 4, .read = uhci_ioport_readl, }, 1148 { 0, 32, 1, .write = uhci_ioport_writeb, }, 1149 { 0, 32, 1, .read = uhci_ioport_readb, }, 1150 PORTIO_END_OF_LIST() 1151 }; 1152 1153 static const MemoryRegionOps uhci_ioport_ops = { 1154 .old_portio = uhci_portio, 1155 }; 1156 1157 static USBPortOps uhci_port_ops = { 1158 .attach = uhci_attach, 1159 .detach = uhci_detach, 1160 .child_detach = uhci_child_detach, 1161 .wakeup = uhci_wakeup, 1162 .complete = uhci_async_complete, 1163 }; 1164 1165 static USBBusOps uhci_bus_ops = { 1166 }; 1167 1168 static int usb_uhci_common_initfn(PCIDevice *dev) 1169 { 1170 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1171 uint8_t *pci_conf = s->dev.config; 1172 int i; 1173 1174 pci_conf[PCI_CLASS_PROG] = 0x00; 1175 /* TODO: reset value should be 0. */ 1176 pci_conf[PCI_INTERRUPT_PIN] = 4; /* interrupt pin D */ 1177 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1178 1179 if (s->masterbus) { 1180 USBPort *ports[NB_PORTS]; 1181 for(i = 0; i < NB_PORTS; i++) { 1182 ports[i] = &s->ports[i].port; 1183 } 1184 if (usb_register_companion(s->masterbus, ports, NB_PORTS, 1185 s->firstport, s, &uhci_port_ops, 1186 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1187 return -1; 1188 } 1189 } else { 1190 usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); 1191 for (i = 0; i < NB_PORTS; i++) { 1192 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1193 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1194 } 1195 } 1196 s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); 1197 s->num_ports_vmstate = NB_PORTS; 1198 QTAILQ_INIT(&s->queues); 1199 1200 qemu_register_reset(uhci_reset, s); 1201 1202 memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); 1203 /* Use region 4 for consistency with real hardware. BSD guests seem 1204 to rely on this. */ 1205 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1206 1207 return 0; 1208 } 1209 1210 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) 1211 { 1212 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1213 uint8_t *pci_conf = s->dev.config; 1214 1215 /* USB misc control 1/2 */ 1216 pci_set_long(pci_conf + 0x40,0x00001000); 1217 /* PM capability */ 1218 pci_set_long(pci_conf + 0x80,0x00020001); 1219 /* USB legacy support */ 1220 pci_set_long(pci_conf + 0xc0,0x00002000); 1221 1222 return usb_uhci_common_initfn(dev); 1223 } 1224 1225 static int usb_uhci_exit(PCIDevice *dev) 1226 { 1227 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1228 1229 memory_region_destroy(&s->io_bar); 1230 return 0; 1231 } 1232 1233 static Property uhci_properties[] = { 1234 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1235 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1236 DEFINE_PROP_END_OF_LIST(), 1237 }; 1238 1239 static void piix3_uhci_class_init(ObjectClass *klass, void *data) 1240 { 1241 DeviceClass *dc = DEVICE_CLASS(klass); 1242 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1243 1244 k->init = usb_uhci_common_initfn; 1245 k->exit = usb_uhci_exit; 1246 k->vendor_id = PCI_VENDOR_ID_INTEL; 1247 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; 1248 k->revision = 0x01; 1249 k->class_id = PCI_CLASS_SERIAL_USB; 1250 dc->vmsd = &vmstate_uhci; 1251 dc->props = uhci_properties; 1252 } 1253 1254 static TypeInfo piix3_uhci_info = { 1255 .name = "piix3-usb-uhci", 1256 .parent = TYPE_PCI_DEVICE, 1257 .instance_size = sizeof(UHCIState), 1258 .class_init = piix3_uhci_class_init, 1259 }; 1260 1261 static void piix4_uhci_class_init(ObjectClass *klass, void *data) 1262 { 1263 DeviceClass *dc = DEVICE_CLASS(klass); 1264 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1265 1266 k->init = usb_uhci_common_initfn; 1267 k->exit = usb_uhci_exit; 1268 k->vendor_id = PCI_VENDOR_ID_INTEL; 1269 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; 1270 k->revision = 0x01; 1271 k->class_id = PCI_CLASS_SERIAL_USB; 1272 dc->vmsd = &vmstate_uhci; 1273 dc->props = uhci_properties; 1274 } 1275 1276 static TypeInfo piix4_uhci_info = { 1277 .name = "piix4-usb-uhci", 1278 .parent = TYPE_PCI_DEVICE, 1279 .instance_size = sizeof(UHCIState), 1280 .class_init = piix4_uhci_class_init, 1281 }; 1282 1283 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) 1284 { 1285 DeviceClass *dc = DEVICE_CLASS(klass); 1286 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1287 1288 k->init = usb_uhci_vt82c686b_initfn; 1289 k->exit = usb_uhci_exit; 1290 k->vendor_id = PCI_VENDOR_ID_VIA; 1291 k->device_id = PCI_DEVICE_ID_VIA_UHCI; 1292 k->revision = 0x01; 1293 k->class_id = PCI_CLASS_SERIAL_USB; 1294 dc->vmsd = &vmstate_uhci; 1295 dc->props = uhci_properties; 1296 } 1297 1298 static TypeInfo vt82c686b_uhci_info = { 1299 .name = "vt82c686b-usb-uhci", 1300 .parent = TYPE_PCI_DEVICE, 1301 .instance_size = sizeof(UHCIState), 1302 .class_init = vt82c686b_uhci_class_init, 1303 }; 1304 1305 static void ich9_uhci1_class_init(ObjectClass *klass, void *data) 1306 { 1307 DeviceClass *dc = DEVICE_CLASS(klass); 1308 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1309 1310 k->init = usb_uhci_common_initfn; 1311 k->vendor_id = PCI_VENDOR_ID_INTEL; 1312 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; 1313 k->revision = 0x03; 1314 k->class_id = PCI_CLASS_SERIAL_USB; 1315 dc->vmsd = &vmstate_uhci; 1316 dc->props = uhci_properties; 1317 } 1318 1319 static TypeInfo ich9_uhci1_info = { 1320 .name = "ich9-usb-uhci1", 1321 .parent = TYPE_PCI_DEVICE, 1322 .instance_size = sizeof(UHCIState), 1323 .class_init = ich9_uhci1_class_init, 1324 }; 1325 1326 static void ich9_uhci2_class_init(ObjectClass *klass, void *data) 1327 { 1328 DeviceClass *dc = DEVICE_CLASS(klass); 1329 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1330 1331 k->init = usb_uhci_common_initfn; 1332 k->vendor_id = PCI_VENDOR_ID_INTEL; 1333 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; 1334 k->revision = 0x03; 1335 k->class_id = PCI_CLASS_SERIAL_USB; 1336 dc->vmsd = &vmstate_uhci; 1337 dc->props = uhci_properties; 1338 } 1339 1340 static TypeInfo ich9_uhci2_info = { 1341 .name = "ich9-usb-uhci2", 1342 .parent = TYPE_PCI_DEVICE, 1343 .instance_size = sizeof(UHCIState), 1344 .class_init = ich9_uhci2_class_init, 1345 }; 1346 1347 static void ich9_uhci3_class_init(ObjectClass *klass, void *data) 1348 { 1349 DeviceClass *dc = DEVICE_CLASS(klass); 1350 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1351 1352 k->init = usb_uhci_common_initfn; 1353 k->vendor_id = PCI_VENDOR_ID_INTEL; 1354 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; 1355 k->revision = 0x03; 1356 k->class_id = PCI_CLASS_SERIAL_USB; 1357 dc->vmsd = &vmstate_uhci; 1358 dc->props = uhci_properties; 1359 } 1360 1361 static TypeInfo ich9_uhci3_info = { 1362 .name = "ich9-usb-uhci3", 1363 .parent = TYPE_PCI_DEVICE, 1364 .instance_size = sizeof(UHCIState), 1365 .class_init = ich9_uhci3_class_init, 1366 }; 1367 1368 static void uhci_register_types(void) 1369 { 1370 type_register_static(&piix3_uhci_info); 1371 type_register_static(&piix4_uhci_info); 1372 type_register_static(&vt82c686b_uhci_info); 1373 type_register_static(&ich9_uhci1_info); 1374 type_register_static(&ich9_uhci2_info); 1375 type_register_static(&ich9_uhci3_info); 1376 } 1377 1378 type_init(uhci_register_types) 1379