1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/pci.h" 31 #include "qemu-timer.h" 32 #include "iov.h" 33 #include "dma.h" 34 #include "trace.h" 35 36 //#define DEBUG 37 //#define DEBUG_DUMP_DATA 38 39 #define UHCI_CMD_FGR (1 << 4) 40 #define UHCI_CMD_EGSM (1 << 3) 41 #define UHCI_CMD_GRESET (1 << 2) 42 #define UHCI_CMD_HCRESET (1 << 1) 43 #define UHCI_CMD_RS (1 << 0) 44 45 #define UHCI_STS_HCHALTED (1 << 5) 46 #define UHCI_STS_HCPERR (1 << 4) 47 #define UHCI_STS_HSERR (1 << 3) 48 #define UHCI_STS_RD (1 << 2) 49 #define UHCI_STS_USBERR (1 << 1) 50 #define UHCI_STS_USBINT (1 << 0) 51 52 #define TD_CTRL_SPD (1 << 29) 53 #define TD_CTRL_ERROR_SHIFT 27 54 #define TD_CTRL_IOS (1 << 25) 55 #define TD_CTRL_IOC (1 << 24) 56 #define TD_CTRL_ACTIVE (1 << 23) 57 #define TD_CTRL_STALL (1 << 22) 58 #define TD_CTRL_BABBLE (1 << 20) 59 #define TD_CTRL_NAK (1 << 19) 60 #define TD_CTRL_TIMEOUT (1 << 18) 61 62 #define UHCI_PORT_SUSPEND (1 << 12) 63 #define UHCI_PORT_RESET (1 << 9) 64 #define UHCI_PORT_LSDA (1 << 8) 65 #define UHCI_PORT_RD (1 << 6) 66 #define UHCI_PORT_ENC (1 << 3) 67 #define UHCI_PORT_EN (1 << 2) 68 #define UHCI_PORT_CSC (1 << 1) 69 #define UHCI_PORT_CCS (1 << 0) 70 71 #define UHCI_PORT_READ_ONLY (0x1bb) 72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) 73 74 #define FRAME_TIMER_FREQ 1000 75 76 #define FRAME_MAX_LOOPS 256 77 78 #define NB_PORTS 2 79 80 enum { 81 TD_RESULT_STOP_FRAME = 10, 82 TD_RESULT_COMPLETE, 83 TD_RESULT_NEXT_QH, 84 TD_RESULT_ASYNC_START, 85 TD_RESULT_ASYNC_CONT, 86 }; 87 88 typedef struct UHCIState UHCIState; 89 typedef struct UHCIAsync UHCIAsync; 90 typedef struct UHCIQueue UHCIQueue; 91 92 /* 93 * Pending async transaction. 94 * 'packet' must be the first field because completion 95 * handler does "(UHCIAsync *) pkt" cast. 96 */ 97 98 struct UHCIAsync { 99 USBPacket packet; 100 QEMUSGList sgl; 101 UHCIQueue *queue; 102 QTAILQ_ENTRY(UHCIAsync) next; 103 uint32_t td_addr; 104 uint8_t done; 105 }; 106 107 struct UHCIQueue { 108 uint32_t token; 109 UHCIState *uhci; 110 USBEndpoint *ep; 111 QTAILQ_ENTRY(UHCIQueue) next; 112 QTAILQ_HEAD(, UHCIAsync) asyncs; 113 int8_t valid; 114 }; 115 116 typedef struct UHCIPort { 117 USBPort port; 118 uint16_t ctrl; 119 } UHCIPort; 120 121 struct UHCIState { 122 PCIDevice dev; 123 MemoryRegion io_bar; 124 USBBus bus; /* Note unused when we're a companion controller */ 125 uint16_t cmd; /* cmd register */ 126 uint16_t status; 127 uint16_t intr; /* interrupt enable register */ 128 uint16_t frnum; /* frame number */ 129 uint32_t fl_base_addr; /* frame list base address */ 130 uint8_t sof_timing; 131 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 132 int64_t expire_time; 133 QEMUTimer *frame_timer; 134 QEMUBH *bh; 135 uint32_t frame_bytes; 136 uint32_t frame_bandwidth; 137 UHCIPort ports[NB_PORTS]; 138 139 /* Interrupts that should be raised at the end of the current frame. */ 140 uint32_t pending_int_mask; 141 int irq_pin; 142 143 /* Active packets */ 144 QTAILQ_HEAD(, UHCIQueue) queues; 145 uint8_t num_ports_vmstate; 146 147 /* Properties */ 148 char *masterbus; 149 uint32_t firstport; 150 }; 151 152 typedef struct UHCI_TD { 153 uint32_t link; 154 uint32_t ctrl; /* see TD_CTRL_xxx */ 155 uint32_t token; 156 uint32_t buffer; 157 } UHCI_TD; 158 159 typedef struct UHCI_QH { 160 uint32_t link; 161 uint32_t el_link; 162 } UHCI_QH; 163 164 static void uhci_async_cancel(UHCIAsync *async); 165 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td); 166 167 static inline int32_t uhci_queue_token(UHCI_TD *td) 168 { 169 /* covers ep, dev, pid -> identifies the endpoint */ 170 return td->token & 0x7ffff; 171 } 172 173 static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td, USBEndpoint *ep) 174 { 175 uint32_t token = uhci_queue_token(td); 176 UHCIQueue *queue; 177 178 QTAILQ_FOREACH(queue, &s->queues, next) { 179 if (queue->token == token) { 180 return queue; 181 } 182 } 183 184 queue = g_new0(UHCIQueue, 1); 185 queue->uhci = s; 186 queue->token = token; 187 queue->ep = ep; 188 QTAILQ_INIT(&queue->asyncs); 189 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 190 trace_usb_uhci_queue_add(queue->token); 191 return queue; 192 } 193 194 static void uhci_queue_free(UHCIQueue *queue) 195 { 196 UHCIState *s = queue->uhci; 197 UHCIAsync *async; 198 199 while (!QTAILQ_EMPTY(&queue->asyncs)) { 200 async = QTAILQ_FIRST(&queue->asyncs); 201 uhci_async_cancel(async); 202 } 203 204 trace_usb_uhci_queue_del(queue->token); 205 QTAILQ_REMOVE(&s->queues, queue, next); 206 g_free(queue); 207 } 208 209 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr) 210 { 211 UHCIAsync *async = g_new0(UHCIAsync, 1); 212 213 async->queue = queue; 214 async->td_addr = td_addr; 215 usb_packet_init(&async->packet); 216 pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1); 217 trace_usb_uhci_packet_add(async->queue->token, async->td_addr); 218 219 return async; 220 } 221 222 static void uhci_async_free(UHCIAsync *async) 223 { 224 trace_usb_uhci_packet_del(async->queue->token, async->td_addr); 225 usb_packet_cleanup(&async->packet); 226 qemu_sglist_destroy(&async->sgl); 227 g_free(async); 228 } 229 230 static void uhci_async_link(UHCIAsync *async) 231 { 232 UHCIQueue *queue = async->queue; 233 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 234 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr); 235 } 236 237 static void uhci_async_unlink(UHCIAsync *async) 238 { 239 UHCIQueue *queue = async->queue; 240 QTAILQ_REMOVE(&queue->asyncs, async, next); 241 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr); 242 } 243 244 static void uhci_async_cancel(UHCIAsync *async) 245 { 246 uhci_async_unlink(async); 247 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr, 248 async->done); 249 if (!async->done) 250 usb_cancel_packet(&async->packet); 251 usb_packet_unmap(&async->packet, &async->sgl); 252 uhci_async_free(async); 253 } 254 255 /* 256 * Mark all outstanding async packets as invalid. 257 * This is used for canceling them when TDs are removed by the HCD. 258 */ 259 static void uhci_async_validate_begin(UHCIState *s) 260 { 261 UHCIQueue *queue; 262 263 QTAILQ_FOREACH(queue, &s->queues, next) { 264 queue->valid--; 265 } 266 } 267 268 /* 269 * Cancel async packets that are no longer valid 270 */ 271 static void uhci_async_validate_end(UHCIState *s) 272 { 273 UHCIQueue *queue, *n; 274 275 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 276 if (!queue->valid) { 277 uhci_queue_free(queue); 278 } 279 } 280 } 281 282 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 283 { 284 UHCIQueue *queue, *n; 285 286 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 287 if (queue->ep->dev == dev) { 288 uhci_queue_free(queue, "cancel-device"); 289 } 290 } 291 } 292 293 static void uhci_async_cancel_all(UHCIState *s) 294 { 295 UHCIQueue *queue, *nq; 296 297 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 298 uhci_queue_free(queue); 299 } 300 } 301 302 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr, 303 UHCI_TD *td) 304 { 305 uint32_t token = uhci_queue_token(td); 306 UHCIQueue *queue; 307 UHCIAsync *async; 308 309 QTAILQ_FOREACH(queue, &s->queues, next) { 310 if (queue->token == token) { 311 break; 312 } 313 } 314 if (queue == NULL) { 315 return NULL; 316 } 317 318 QTAILQ_FOREACH(async, &queue->asyncs, next) { 319 if (async->td_addr == td_addr) { 320 return async; 321 } 322 } 323 324 return NULL; 325 } 326 327 static void uhci_update_irq(UHCIState *s) 328 { 329 int level; 330 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 331 ((s->status2 & 2) && (s->intr & (1 << 3))) || 332 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 333 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 334 (s->status & UHCI_STS_HSERR) || 335 (s->status & UHCI_STS_HCPERR)) { 336 level = 1; 337 } else { 338 level = 0; 339 } 340 qemu_set_irq(s->dev.irq[s->irq_pin], level); 341 } 342 343 static void uhci_reset(void *opaque) 344 { 345 UHCIState *s = opaque; 346 uint8_t *pci_conf; 347 int i; 348 UHCIPort *port; 349 350 trace_usb_uhci_reset(); 351 352 pci_conf = s->dev.config; 353 354 pci_conf[0x6a] = 0x01; /* usb clock */ 355 pci_conf[0x6b] = 0x00; 356 s->cmd = 0; 357 s->status = 0; 358 s->status2 = 0; 359 s->intr = 0; 360 s->fl_base_addr = 0; 361 s->sof_timing = 64; 362 363 for(i = 0; i < NB_PORTS; i++) { 364 port = &s->ports[i]; 365 port->ctrl = 0x0080; 366 if (port->port.dev && port->port.dev->attached) { 367 usb_port_reset(&port->port); 368 } 369 } 370 371 uhci_async_cancel_all(s); 372 qemu_bh_cancel(s->bh); 373 uhci_update_irq(s); 374 } 375 376 static const VMStateDescription vmstate_uhci_port = { 377 .name = "uhci port", 378 .version_id = 1, 379 .minimum_version_id = 1, 380 .minimum_version_id_old = 1, 381 .fields = (VMStateField []) { 382 VMSTATE_UINT16(ctrl, UHCIPort), 383 VMSTATE_END_OF_LIST() 384 } 385 }; 386 387 static int uhci_post_load(void *opaque, int version_id) 388 { 389 UHCIState *s = opaque; 390 391 if (version_id < 2) { 392 s->expire_time = qemu_get_clock_ns(vm_clock) + 393 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 394 } 395 return 0; 396 } 397 398 static const VMStateDescription vmstate_uhci = { 399 .name = "uhci", 400 .version_id = 2, 401 .minimum_version_id = 1, 402 .minimum_version_id_old = 1, 403 .post_load = uhci_post_load, 404 .fields = (VMStateField []) { 405 VMSTATE_PCI_DEVICE(dev, UHCIState), 406 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 407 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 408 vmstate_uhci_port, UHCIPort), 409 VMSTATE_UINT16(cmd, UHCIState), 410 VMSTATE_UINT16(status, UHCIState), 411 VMSTATE_UINT16(intr, UHCIState), 412 VMSTATE_UINT16(frnum, UHCIState), 413 VMSTATE_UINT32(fl_base_addr, UHCIState), 414 VMSTATE_UINT8(sof_timing, UHCIState), 415 VMSTATE_UINT8(status2, UHCIState), 416 VMSTATE_TIMER(frame_timer, UHCIState), 417 VMSTATE_INT64_V(expire_time, UHCIState, 2), 418 VMSTATE_END_OF_LIST() 419 } 420 }; 421 422 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) 423 { 424 UHCIState *s = opaque; 425 426 addr &= 0x1f; 427 switch(addr) { 428 case 0x0c: 429 s->sof_timing = val; 430 break; 431 } 432 } 433 434 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) 435 { 436 UHCIState *s = opaque; 437 uint32_t val; 438 439 addr &= 0x1f; 440 switch(addr) { 441 case 0x0c: 442 val = s->sof_timing; 443 break; 444 default: 445 val = 0xff; 446 break; 447 } 448 return val; 449 } 450 451 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) 452 { 453 UHCIState *s = opaque; 454 455 addr &= 0x1f; 456 trace_usb_uhci_mmio_writew(addr, val); 457 458 switch(addr) { 459 case 0x00: 460 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 461 /* start frame processing */ 462 trace_usb_uhci_schedule_start(); 463 s->expire_time = qemu_get_clock_ns(vm_clock) + 464 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 465 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); 466 s->status &= ~UHCI_STS_HCHALTED; 467 } else if (!(val & UHCI_CMD_RS)) { 468 s->status |= UHCI_STS_HCHALTED; 469 } 470 if (val & UHCI_CMD_GRESET) { 471 UHCIPort *port; 472 int i; 473 474 /* send reset on the USB bus */ 475 for(i = 0; i < NB_PORTS; i++) { 476 port = &s->ports[i]; 477 usb_device_reset(port->port.dev); 478 } 479 uhci_reset(s); 480 return; 481 } 482 if (val & UHCI_CMD_HCRESET) { 483 uhci_reset(s); 484 return; 485 } 486 s->cmd = val; 487 break; 488 case 0x02: 489 s->status &= ~val; 490 /* XXX: the chip spec is not coherent, so we add a hidden 491 register to distinguish between IOC and SPD */ 492 if (val & UHCI_STS_USBINT) 493 s->status2 = 0; 494 uhci_update_irq(s); 495 break; 496 case 0x04: 497 s->intr = val; 498 uhci_update_irq(s); 499 break; 500 case 0x06: 501 if (s->status & UHCI_STS_HCHALTED) 502 s->frnum = val & 0x7ff; 503 break; 504 case 0x10 ... 0x1f: 505 { 506 UHCIPort *port; 507 USBDevice *dev; 508 int n; 509 510 n = (addr >> 1) & 7; 511 if (n >= NB_PORTS) 512 return; 513 port = &s->ports[n]; 514 dev = port->port.dev; 515 if (dev && dev->attached) { 516 /* port reset */ 517 if ( (val & UHCI_PORT_RESET) && 518 !(port->ctrl & UHCI_PORT_RESET) ) { 519 usb_device_reset(dev); 520 } 521 } 522 port->ctrl &= UHCI_PORT_READ_ONLY; 523 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 524 /* some bits are reset when a '1' is written to them */ 525 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 526 } 527 break; 528 } 529 } 530 531 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) 532 { 533 UHCIState *s = opaque; 534 uint32_t val; 535 536 addr &= 0x1f; 537 switch(addr) { 538 case 0x00: 539 val = s->cmd; 540 break; 541 case 0x02: 542 val = s->status; 543 break; 544 case 0x04: 545 val = s->intr; 546 break; 547 case 0x06: 548 val = s->frnum; 549 break; 550 case 0x10 ... 0x1f: 551 { 552 UHCIPort *port; 553 int n; 554 n = (addr >> 1) & 7; 555 if (n >= NB_PORTS) 556 goto read_default; 557 port = &s->ports[n]; 558 val = port->ctrl; 559 } 560 break; 561 default: 562 read_default: 563 val = 0xff7f; /* disabled port */ 564 break; 565 } 566 567 trace_usb_uhci_mmio_readw(addr, val); 568 569 return val; 570 } 571 572 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) 573 { 574 UHCIState *s = opaque; 575 576 addr &= 0x1f; 577 trace_usb_uhci_mmio_writel(addr, val); 578 579 switch(addr) { 580 case 0x08: 581 s->fl_base_addr = val & ~0xfff; 582 break; 583 } 584 } 585 586 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) 587 { 588 UHCIState *s = opaque; 589 uint32_t val; 590 591 addr &= 0x1f; 592 switch(addr) { 593 case 0x08: 594 val = s->fl_base_addr; 595 break; 596 default: 597 val = 0xffffffff; 598 break; 599 } 600 trace_usb_uhci_mmio_readl(addr, val); 601 return val; 602 } 603 604 /* signal resume if controller suspended */ 605 static void uhci_resume (void *opaque) 606 { 607 UHCIState *s = (UHCIState *)opaque; 608 609 if (!s) 610 return; 611 612 if (s->cmd & UHCI_CMD_EGSM) { 613 s->cmd |= UHCI_CMD_FGR; 614 s->status |= UHCI_STS_RD; 615 uhci_update_irq(s); 616 } 617 } 618 619 static void uhci_attach(USBPort *port1) 620 { 621 UHCIState *s = port1->opaque; 622 UHCIPort *port = &s->ports[port1->index]; 623 624 /* set connect status */ 625 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 626 627 /* update speed */ 628 if (port->port.dev->speed == USB_SPEED_LOW) { 629 port->ctrl |= UHCI_PORT_LSDA; 630 } else { 631 port->ctrl &= ~UHCI_PORT_LSDA; 632 } 633 634 uhci_resume(s); 635 } 636 637 static void uhci_detach(USBPort *port1) 638 { 639 UHCIState *s = port1->opaque; 640 UHCIPort *port = &s->ports[port1->index]; 641 642 uhci_async_cancel_device(s, port1->dev); 643 644 /* set connect status */ 645 if (port->ctrl & UHCI_PORT_CCS) { 646 port->ctrl &= ~UHCI_PORT_CCS; 647 port->ctrl |= UHCI_PORT_CSC; 648 } 649 /* disable port */ 650 if (port->ctrl & UHCI_PORT_EN) { 651 port->ctrl &= ~UHCI_PORT_EN; 652 port->ctrl |= UHCI_PORT_ENC; 653 } 654 655 uhci_resume(s); 656 } 657 658 static void uhci_child_detach(USBPort *port1, USBDevice *child) 659 { 660 UHCIState *s = port1->opaque; 661 662 uhci_async_cancel_device(s, child); 663 } 664 665 static void uhci_wakeup(USBPort *port1) 666 { 667 UHCIState *s = port1->opaque; 668 UHCIPort *port = &s->ports[port1->index]; 669 670 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 671 port->ctrl |= UHCI_PORT_RD; 672 uhci_resume(s); 673 } 674 } 675 676 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 677 { 678 USBDevice *dev; 679 int i; 680 681 for (i = 0; i < NB_PORTS; i++) { 682 UHCIPort *port = &s->ports[i]; 683 if (!(port->ctrl & UHCI_PORT_EN)) { 684 continue; 685 } 686 dev = usb_find_device(&port->port, addr); 687 if (dev != NULL) { 688 return dev; 689 } 690 } 691 return NULL; 692 } 693 694 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) 695 { 696 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td)); 697 le32_to_cpus(&td->link); 698 le32_to_cpus(&td->ctrl); 699 le32_to_cpus(&td->token); 700 le32_to_cpus(&td->buffer); 701 } 702 703 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 704 { 705 int len = 0, max_len, err, ret; 706 uint8_t pid; 707 708 max_len = ((td->token >> 21) + 1) & 0x7ff; 709 pid = td->token & 0xff; 710 711 ret = async->packet.result; 712 713 if (td->ctrl & TD_CTRL_IOS) 714 td->ctrl &= ~TD_CTRL_ACTIVE; 715 716 if (ret < 0) 717 goto out; 718 719 len = async->packet.result; 720 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 721 722 /* The NAK bit may have been set by a previous frame, so clear it 723 here. The docs are somewhat unclear, but win2k relies on this 724 behavior. */ 725 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 726 if (td->ctrl & TD_CTRL_IOC) 727 *int_mask |= 0x01; 728 729 if (pid == USB_TOKEN_IN) { 730 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 731 *int_mask |= 0x02; 732 /* short packet: do not update QH */ 733 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 734 async->td_addr); 735 return TD_RESULT_NEXT_QH; 736 } 737 } 738 739 /* success */ 740 trace_usb_uhci_packet_complete_success(async->queue->token, 741 async->td_addr); 742 return TD_RESULT_COMPLETE; 743 744 out: 745 switch(ret) { 746 case USB_RET_NAK: 747 td->ctrl |= TD_CTRL_NAK; 748 return TD_RESULT_NEXT_QH; 749 750 case USB_RET_STALL: 751 td->ctrl |= TD_CTRL_STALL; 752 trace_usb_uhci_packet_complete_stall(async->queue->token, 753 async->td_addr); 754 err = TD_RESULT_NEXT_QH; 755 break; 756 757 case USB_RET_BABBLE: 758 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 759 /* frame interrupted */ 760 trace_usb_uhci_packet_complete_babble(async->queue->token, 761 async->td_addr); 762 err = TD_RESULT_STOP_FRAME; 763 break; 764 765 case USB_RET_IOERROR: 766 case USB_RET_NODEV: 767 default: 768 td->ctrl |= TD_CTRL_TIMEOUT; 769 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 770 trace_usb_uhci_packet_complete_error(async->queue->token, 771 async->td_addr); 772 err = TD_RESULT_NEXT_QH; 773 break; 774 } 775 776 td->ctrl &= ~TD_CTRL_ACTIVE; 777 s->status |= UHCI_STS_USBERR; 778 if (td->ctrl & TD_CTRL_IOC) { 779 *int_mask |= 0x01; 780 } 781 uhci_update_irq(s); 782 return err; 783 } 784 785 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, 786 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask) 787 { 788 UHCIAsync *async; 789 int len = 0, max_len; 790 bool spd; 791 bool queuing = (q != NULL); 792 uint8_t pid = td->token & 0xff; 793 794 /* Is active ? */ 795 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 796 /* 797 * ehci11d spec page 22: "Even if the Active bit in the TD is already 798 * cleared when the TD is fetched ... an IOC interrupt is generated" 799 */ 800 if (td->ctrl & TD_CTRL_IOC) { 801 *int_mask |= 0x01; 802 } 803 return TD_RESULT_NEXT_QH; 804 } 805 806 async = uhci_async_find_td(s, td_addr, td); 807 if (async) { 808 /* Already submitted */ 809 async->queue->valid = 32; 810 811 if (!async->done) 812 return TD_RESULT_ASYNC_CONT; 813 if (queuing) { 814 /* we are busy filling the queue, we are not prepared 815 to consume completed packages then, just leave them 816 in async state */ 817 return TD_RESULT_ASYNC_CONT; 818 } 819 820 uhci_async_unlink(async); 821 goto done; 822 } 823 824 /* Allocate new packet */ 825 if (q == NULL) { 826 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 827 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 828 q = uhci_queue_get(s, td, ep); 829 } 830 async = uhci_async_alloc(q, td_addr); 831 832 /* valid needs to be large enough to handle 10 frame delay 833 * for initial isochronous requests 834 */ 835 async->queue->valid = 32; 836 837 max_len = ((td->token >> 21) + 1) & 0x7ff; 838 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 839 usb_packet_setup(&async->packet, pid, q->ep, td_addr, spd, 840 (td->ctrl & TD_CTRL_IOC) != 0); 841 qemu_sglist_add(&async->sgl, td->buffer, max_len); 842 usb_packet_map(&async->packet, &async->sgl); 843 844 switch(pid) { 845 case USB_TOKEN_OUT: 846 case USB_TOKEN_SETUP: 847 len = usb_handle_packet(q->ep->dev, &async->packet); 848 if (len >= 0) 849 len = max_len; 850 break; 851 852 case USB_TOKEN_IN: 853 len = usb_handle_packet(q->ep->dev, &async->packet); 854 break; 855 856 default: 857 /* invalid pid : frame interrupted */ 858 usb_packet_unmap(&async->packet, &async->sgl); 859 uhci_async_free(async); 860 s->status |= UHCI_STS_HCPERR; 861 uhci_update_irq(s); 862 return TD_RESULT_STOP_FRAME; 863 } 864 865 if (len == USB_RET_ASYNC) { 866 uhci_async_link(async); 867 if (!queuing) { 868 uhci_queue_fill(q, td); 869 } 870 return TD_RESULT_ASYNC_START; 871 } 872 873 async->packet.result = len; 874 875 done: 876 len = uhci_complete_td(s, td, async, int_mask); 877 usb_packet_unmap(&async->packet, &async->sgl); 878 uhci_async_free(async); 879 return len; 880 } 881 882 static void uhci_async_complete(USBPort *port, USBPacket *packet) 883 { 884 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 885 UHCIState *s = async->queue->uhci; 886 887 if (packet->result == USB_RET_REMOVE_FROM_QUEUE) { 888 uhci_async_unlink(async); 889 uhci_async_cancel(async); 890 return; 891 } 892 893 async->done = 1; 894 if (s->frame_bytes < s->frame_bandwidth) { 895 qemu_bh_schedule(s->bh); 896 } 897 } 898 899 static int is_valid(uint32_t link) 900 { 901 return (link & 1) == 0; 902 } 903 904 static int is_qh(uint32_t link) 905 { 906 return (link & 2) != 0; 907 } 908 909 static int depth_first(uint32_t link) 910 { 911 return (link & 4) != 0; 912 } 913 914 /* QH DB used for detecting QH loops */ 915 #define UHCI_MAX_QUEUES 128 916 typedef struct { 917 uint32_t addr[UHCI_MAX_QUEUES]; 918 int count; 919 } QhDb; 920 921 static void qhdb_reset(QhDb *db) 922 { 923 db->count = 0; 924 } 925 926 /* Add QH to DB. Returns 1 if already present or DB is full. */ 927 static int qhdb_insert(QhDb *db, uint32_t addr) 928 { 929 int i; 930 for (i = 0; i < db->count; i++) 931 if (db->addr[i] == addr) 932 return 1; 933 934 if (db->count >= UHCI_MAX_QUEUES) 935 return 1; 936 937 db->addr[db->count++] = addr; 938 return 0; 939 } 940 941 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td) 942 { 943 uint32_t int_mask = 0; 944 uint32_t plink = td->link; 945 UHCI_TD ptd; 946 int ret; 947 948 while (is_valid(plink)) { 949 uhci_read_td(q->uhci, &ptd, plink); 950 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 951 break; 952 } 953 if (uhci_queue_token(&ptd) != q->token) { 954 break; 955 } 956 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 957 ret = uhci_handle_td(q->uhci, q, &ptd, plink, &int_mask); 958 if (ret == TD_RESULT_ASYNC_CONT) { 959 break; 960 } 961 assert(ret == TD_RESULT_ASYNC_START); 962 assert(int_mask == 0); 963 plink = ptd.link; 964 } 965 usb_device_flush_ep_queue(q->ep->dev, q->ep); 966 } 967 968 static void uhci_process_frame(UHCIState *s) 969 { 970 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 971 uint32_t curr_qh, td_count = 0; 972 int cnt, ret; 973 UHCI_TD td; 974 UHCI_QH qh; 975 QhDb qhdb; 976 977 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 978 979 pci_dma_read(&s->dev, frame_addr, &link, 4); 980 le32_to_cpus(&link); 981 982 int_mask = 0; 983 curr_qh = 0; 984 985 qhdb_reset(&qhdb); 986 987 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 988 if (s->frame_bytes >= s->frame_bandwidth) { 989 /* We've reached the usb 1.1 bandwidth, which is 990 1280 bytes/frame, stop processing */ 991 trace_usb_uhci_frame_stop_bandwidth(); 992 break; 993 } 994 if (is_qh(link)) { 995 /* QH */ 996 trace_usb_uhci_qh_load(link & ~0xf); 997 998 if (qhdb_insert(&qhdb, link)) { 999 /* 1000 * We're going in circles. Which is not a bug because 1001 * HCD is allowed to do that as part of the BW management. 1002 * 1003 * Stop processing here if no transaction has been done 1004 * since we've been here last time. 1005 */ 1006 if (td_count == 0) { 1007 trace_usb_uhci_frame_loop_stop_idle(); 1008 break; 1009 } else { 1010 trace_usb_uhci_frame_loop_continue(); 1011 td_count = 0; 1012 qhdb_reset(&qhdb); 1013 qhdb_insert(&qhdb, link); 1014 } 1015 } 1016 1017 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1018 le32_to_cpus(&qh.link); 1019 le32_to_cpus(&qh.el_link); 1020 1021 if (!is_valid(qh.el_link)) { 1022 /* QH w/o elements */ 1023 curr_qh = 0; 1024 link = qh.link; 1025 } else { 1026 /* QH with elements */ 1027 curr_qh = link; 1028 link = qh.el_link; 1029 } 1030 continue; 1031 } 1032 1033 /* TD */ 1034 uhci_read_td(s, &td, link); 1035 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1036 1037 old_td_ctrl = td.ctrl; 1038 ret = uhci_handle_td(s, NULL, &td, link, &int_mask); 1039 if (old_td_ctrl != td.ctrl) { 1040 /* update the status bits of the TD */ 1041 val = cpu_to_le32(td.ctrl); 1042 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1043 } 1044 1045 switch (ret) { 1046 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1047 goto out; 1048 1049 case TD_RESULT_NEXT_QH: 1050 case TD_RESULT_ASYNC_CONT: 1051 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1052 link = curr_qh ? qh.link : td.link; 1053 continue; 1054 1055 case TD_RESULT_ASYNC_START: 1056 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1057 link = curr_qh ? qh.link : td.link; 1058 continue; 1059 1060 case TD_RESULT_COMPLETE: 1061 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1062 link = td.link; 1063 td_count++; 1064 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1065 1066 if (curr_qh) { 1067 /* update QH element link */ 1068 qh.el_link = link; 1069 val = cpu_to_le32(qh.el_link); 1070 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1071 1072 if (!depth_first(link)) { 1073 /* done with this QH */ 1074 curr_qh = 0; 1075 link = qh.link; 1076 } 1077 } 1078 break; 1079 1080 default: 1081 assert(!"unknown return code"); 1082 } 1083 1084 /* go to the next entry */ 1085 } 1086 1087 out: 1088 s->pending_int_mask |= int_mask; 1089 } 1090 1091 static void uhci_bh(void *opaque) 1092 { 1093 UHCIState *s = opaque; 1094 uhci_process_frame(s); 1095 } 1096 1097 static void uhci_frame_timer(void *opaque) 1098 { 1099 UHCIState *s = opaque; 1100 1101 /* prepare the timer for the next frame */ 1102 s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); 1103 s->frame_bytes = 0; 1104 qemu_bh_cancel(s->bh); 1105 1106 if (!(s->cmd & UHCI_CMD_RS)) { 1107 /* Full stop */ 1108 trace_usb_uhci_schedule_stop(); 1109 qemu_del_timer(s->frame_timer); 1110 uhci_async_cancel_all(s); 1111 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1112 s->status |= UHCI_STS_HCHALTED; 1113 return; 1114 } 1115 1116 /* Complete the previous frame */ 1117 if (s->pending_int_mask) { 1118 s->status2 |= s->pending_int_mask; 1119 s->status |= UHCI_STS_USBINT; 1120 uhci_update_irq(s); 1121 } 1122 s->pending_int_mask = 0; 1123 1124 /* Start new frame */ 1125 s->frnum = (s->frnum + 1) & 0x7ff; 1126 1127 trace_usb_uhci_frame_start(s->frnum); 1128 1129 uhci_async_validate_begin(s); 1130 1131 uhci_process_frame(s); 1132 1133 uhci_async_validate_end(s); 1134 1135 qemu_mod_timer(s->frame_timer, s->expire_time); 1136 } 1137 1138 static const MemoryRegionPortio uhci_portio[] = { 1139 { 0, 32, 2, .write = uhci_ioport_writew, }, 1140 { 0, 32, 2, .read = uhci_ioport_readw, }, 1141 { 0, 32, 4, .write = uhci_ioport_writel, }, 1142 { 0, 32, 4, .read = uhci_ioport_readl, }, 1143 { 0, 32, 1, .write = uhci_ioport_writeb, }, 1144 { 0, 32, 1, .read = uhci_ioport_readb, }, 1145 PORTIO_END_OF_LIST() 1146 }; 1147 1148 static const MemoryRegionOps uhci_ioport_ops = { 1149 .old_portio = uhci_portio, 1150 }; 1151 1152 static USBPortOps uhci_port_ops = { 1153 .attach = uhci_attach, 1154 .detach = uhci_detach, 1155 .child_detach = uhci_child_detach, 1156 .wakeup = uhci_wakeup, 1157 .complete = uhci_async_complete, 1158 }; 1159 1160 static USBBusOps uhci_bus_ops = { 1161 }; 1162 1163 static int usb_uhci_common_initfn(PCIDevice *dev) 1164 { 1165 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1166 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1167 uint8_t *pci_conf = s->dev.config; 1168 int i; 1169 1170 pci_conf[PCI_CLASS_PROG] = 0x00; 1171 /* TODO: reset value should be 0. */ 1172 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1173 1174 switch (pc->device_id) { 1175 case PCI_DEVICE_ID_INTEL_82801I_UHCI1: 1176 s->irq_pin = 0; /* A */ 1177 break; 1178 case PCI_DEVICE_ID_INTEL_82801I_UHCI2: 1179 s->irq_pin = 1; /* B */ 1180 break; 1181 case PCI_DEVICE_ID_INTEL_82801I_UHCI3: 1182 s->irq_pin = 2; /* C */ 1183 break; 1184 default: 1185 s->irq_pin = 3; /* D */ 1186 break; 1187 } 1188 pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1); 1189 1190 if (s->masterbus) { 1191 USBPort *ports[NB_PORTS]; 1192 for(i = 0; i < NB_PORTS; i++) { 1193 ports[i] = &s->ports[i].port; 1194 } 1195 if (usb_register_companion(s->masterbus, ports, NB_PORTS, 1196 s->firstport, s, &uhci_port_ops, 1197 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1198 return -1; 1199 } 1200 } else { 1201 usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); 1202 for (i = 0; i < NB_PORTS; i++) { 1203 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1204 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1205 } 1206 } 1207 s->bh = qemu_bh_new(uhci_bh, s); 1208 s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); 1209 s->num_ports_vmstate = NB_PORTS; 1210 QTAILQ_INIT(&s->queues); 1211 1212 qemu_register_reset(uhci_reset, s); 1213 1214 memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); 1215 /* Use region 4 for consistency with real hardware. BSD guests seem 1216 to rely on this. */ 1217 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1218 1219 return 0; 1220 } 1221 1222 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) 1223 { 1224 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1225 uint8_t *pci_conf = s->dev.config; 1226 1227 /* USB misc control 1/2 */ 1228 pci_set_long(pci_conf + 0x40,0x00001000); 1229 /* PM capability */ 1230 pci_set_long(pci_conf + 0x80,0x00020001); 1231 /* USB legacy support */ 1232 pci_set_long(pci_conf + 0xc0,0x00002000); 1233 1234 return usb_uhci_common_initfn(dev); 1235 } 1236 1237 static void usb_uhci_exit(PCIDevice *dev) 1238 { 1239 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1240 1241 memory_region_destroy(&s->io_bar); 1242 } 1243 1244 static Property uhci_properties[] = { 1245 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1246 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1247 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1248 DEFINE_PROP_END_OF_LIST(), 1249 }; 1250 1251 static void piix3_uhci_class_init(ObjectClass *klass, void *data) 1252 { 1253 DeviceClass *dc = DEVICE_CLASS(klass); 1254 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1255 1256 k->init = usb_uhci_common_initfn; 1257 k->exit = usb_uhci_exit; 1258 k->vendor_id = PCI_VENDOR_ID_INTEL; 1259 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; 1260 k->revision = 0x01; 1261 k->class_id = PCI_CLASS_SERIAL_USB; 1262 dc->vmsd = &vmstate_uhci; 1263 dc->props = uhci_properties; 1264 } 1265 1266 static TypeInfo piix3_uhci_info = { 1267 .name = "piix3-usb-uhci", 1268 .parent = TYPE_PCI_DEVICE, 1269 .instance_size = sizeof(UHCIState), 1270 .class_init = piix3_uhci_class_init, 1271 }; 1272 1273 static void piix4_uhci_class_init(ObjectClass *klass, void *data) 1274 { 1275 DeviceClass *dc = DEVICE_CLASS(klass); 1276 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1277 1278 k->init = usb_uhci_common_initfn; 1279 k->exit = usb_uhci_exit; 1280 k->vendor_id = PCI_VENDOR_ID_INTEL; 1281 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; 1282 k->revision = 0x01; 1283 k->class_id = PCI_CLASS_SERIAL_USB; 1284 dc->vmsd = &vmstate_uhci; 1285 dc->props = uhci_properties; 1286 } 1287 1288 static TypeInfo piix4_uhci_info = { 1289 .name = "piix4-usb-uhci", 1290 .parent = TYPE_PCI_DEVICE, 1291 .instance_size = sizeof(UHCIState), 1292 .class_init = piix4_uhci_class_init, 1293 }; 1294 1295 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) 1296 { 1297 DeviceClass *dc = DEVICE_CLASS(klass); 1298 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1299 1300 k->init = usb_uhci_vt82c686b_initfn; 1301 k->exit = usb_uhci_exit; 1302 k->vendor_id = PCI_VENDOR_ID_VIA; 1303 k->device_id = PCI_DEVICE_ID_VIA_UHCI; 1304 k->revision = 0x01; 1305 k->class_id = PCI_CLASS_SERIAL_USB; 1306 dc->vmsd = &vmstate_uhci; 1307 dc->props = uhci_properties; 1308 } 1309 1310 static TypeInfo vt82c686b_uhci_info = { 1311 .name = "vt82c686b-usb-uhci", 1312 .parent = TYPE_PCI_DEVICE, 1313 .instance_size = sizeof(UHCIState), 1314 .class_init = vt82c686b_uhci_class_init, 1315 }; 1316 1317 static void ich9_uhci1_class_init(ObjectClass *klass, void *data) 1318 { 1319 DeviceClass *dc = DEVICE_CLASS(klass); 1320 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1321 1322 k->init = usb_uhci_common_initfn; 1323 k->vendor_id = PCI_VENDOR_ID_INTEL; 1324 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; 1325 k->revision = 0x03; 1326 k->class_id = PCI_CLASS_SERIAL_USB; 1327 dc->vmsd = &vmstate_uhci; 1328 dc->props = uhci_properties; 1329 } 1330 1331 static TypeInfo ich9_uhci1_info = { 1332 .name = "ich9-usb-uhci1", 1333 .parent = TYPE_PCI_DEVICE, 1334 .instance_size = sizeof(UHCIState), 1335 .class_init = ich9_uhci1_class_init, 1336 }; 1337 1338 static void ich9_uhci2_class_init(ObjectClass *klass, void *data) 1339 { 1340 DeviceClass *dc = DEVICE_CLASS(klass); 1341 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1342 1343 k->init = usb_uhci_common_initfn; 1344 k->vendor_id = PCI_VENDOR_ID_INTEL; 1345 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; 1346 k->revision = 0x03; 1347 k->class_id = PCI_CLASS_SERIAL_USB; 1348 dc->vmsd = &vmstate_uhci; 1349 dc->props = uhci_properties; 1350 } 1351 1352 static TypeInfo ich9_uhci2_info = { 1353 .name = "ich9-usb-uhci2", 1354 .parent = TYPE_PCI_DEVICE, 1355 .instance_size = sizeof(UHCIState), 1356 .class_init = ich9_uhci2_class_init, 1357 }; 1358 1359 static void ich9_uhci3_class_init(ObjectClass *klass, void *data) 1360 { 1361 DeviceClass *dc = DEVICE_CLASS(klass); 1362 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1363 1364 k->init = usb_uhci_common_initfn; 1365 k->vendor_id = PCI_VENDOR_ID_INTEL; 1366 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; 1367 k->revision = 0x03; 1368 k->class_id = PCI_CLASS_SERIAL_USB; 1369 dc->vmsd = &vmstate_uhci; 1370 dc->props = uhci_properties; 1371 } 1372 1373 static TypeInfo ich9_uhci3_info = { 1374 .name = "ich9-usb-uhci3", 1375 .parent = TYPE_PCI_DEVICE, 1376 .instance_size = sizeof(UHCIState), 1377 .class_init = ich9_uhci3_class_init, 1378 }; 1379 1380 static void uhci_register_types(void) 1381 { 1382 type_register_static(&piix3_uhci_info); 1383 type_register_static(&piix4_uhci_info); 1384 type_register_static(&vt82c686b_uhci_info); 1385 type_register_static(&ich9_uhci1_info); 1386 type_register_static(&ich9_uhci2_info); 1387 type_register_static(&ich9_uhci3_info); 1388 } 1389 1390 type_init(uhci_register_types) 1391