1 /* 2 * USB UHCI controller emulation 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Copyright (c) 2008 Max Krasnyansky 7 * Magor rewrite of the UHCI data structures parser and frame processor 8 * Support for fully async operation and multiple outstanding transactions 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 #include "hw/hw.h" 29 #include "hw/usb.h" 30 #include "hw/pci.h" 31 #include "qemu-timer.h" 32 #include "iov.h" 33 #include "dma.h" 34 #include "trace.h" 35 36 //#define DEBUG 37 //#define DEBUG_DUMP_DATA 38 39 #define UHCI_CMD_FGR (1 << 4) 40 #define UHCI_CMD_EGSM (1 << 3) 41 #define UHCI_CMD_GRESET (1 << 2) 42 #define UHCI_CMD_HCRESET (1 << 1) 43 #define UHCI_CMD_RS (1 << 0) 44 45 #define UHCI_STS_HCHALTED (1 << 5) 46 #define UHCI_STS_HCPERR (1 << 4) 47 #define UHCI_STS_HSERR (1 << 3) 48 #define UHCI_STS_RD (1 << 2) 49 #define UHCI_STS_USBERR (1 << 1) 50 #define UHCI_STS_USBINT (1 << 0) 51 52 #define TD_CTRL_SPD (1 << 29) 53 #define TD_CTRL_ERROR_SHIFT 27 54 #define TD_CTRL_IOS (1 << 25) 55 #define TD_CTRL_IOC (1 << 24) 56 #define TD_CTRL_ACTIVE (1 << 23) 57 #define TD_CTRL_STALL (1 << 22) 58 #define TD_CTRL_BABBLE (1 << 20) 59 #define TD_CTRL_NAK (1 << 19) 60 #define TD_CTRL_TIMEOUT (1 << 18) 61 62 #define UHCI_PORT_SUSPEND (1 << 12) 63 #define UHCI_PORT_RESET (1 << 9) 64 #define UHCI_PORT_LSDA (1 << 8) 65 #define UHCI_PORT_RD (1 << 6) 66 #define UHCI_PORT_ENC (1 << 3) 67 #define UHCI_PORT_EN (1 << 2) 68 #define UHCI_PORT_CSC (1 << 1) 69 #define UHCI_PORT_CCS (1 << 0) 70 71 #define UHCI_PORT_READ_ONLY (0x1bb) 72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) 73 74 #define FRAME_TIMER_FREQ 1000 75 76 #define FRAME_MAX_LOOPS 256 77 78 #define NB_PORTS 2 79 80 enum { 81 TD_RESULT_STOP_FRAME = 10, 82 TD_RESULT_COMPLETE, 83 TD_RESULT_NEXT_QH, 84 TD_RESULT_ASYNC_START, 85 TD_RESULT_ASYNC_CONT, 86 }; 87 88 typedef struct UHCIState UHCIState; 89 typedef struct UHCIAsync UHCIAsync; 90 typedef struct UHCIQueue UHCIQueue; 91 92 /* 93 * Pending async transaction. 94 * 'packet' must be the first field because completion 95 * handler does "(UHCIAsync *) pkt" cast. 96 */ 97 98 struct UHCIAsync { 99 USBPacket packet; 100 QEMUSGList sgl; 101 UHCIQueue *queue; 102 QTAILQ_ENTRY(UHCIAsync) next; 103 uint32_t td; 104 uint8_t done; 105 }; 106 107 struct UHCIQueue { 108 uint32_t token; 109 UHCIState *uhci; 110 QTAILQ_ENTRY(UHCIQueue) next; 111 QTAILQ_HEAD(, UHCIAsync) asyncs; 112 int8_t valid; 113 }; 114 115 typedef struct UHCIPort { 116 USBPort port; 117 uint16_t ctrl; 118 } UHCIPort; 119 120 struct UHCIState { 121 PCIDevice dev; 122 MemoryRegion io_bar; 123 USBBus bus; /* Note unused when we're a companion controller */ 124 uint16_t cmd; /* cmd register */ 125 uint16_t status; 126 uint16_t intr; /* interrupt enable register */ 127 uint16_t frnum; /* frame number */ 128 uint32_t fl_base_addr; /* frame list base address */ 129 uint8_t sof_timing; 130 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ 131 int64_t expire_time; 132 QEMUTimer *frame_timer; 133 QEMUBH *bh; 134 uint32_t frame_bytes; 135 uint32_t frame_bandwidth; 136 UHCIPort ports[NB_PORTS]; 137 138 /* Interrupts that should be raised at the end of the current frame. */ 139 uint32_t pending_int_mask; 140 int irq_pin; 141 142 /* Active packets */ 143 QTAILQ_HEAD(, UHCIQueue) queues; 144 uint8_t num_ports_vmstate; 145 146 /* Properties */ 147 char *masterbus; 148 uint32_t firstport; 149 }; 150 151 typedef struct UHCI_TD { 152 uint32_t link; 153 uint32_t ctrl; /* see TD_CTRL_xxx */ 154 uint32_t token; 155 uint32_t buffer; 156 } UHCI_TD; 157 158 typedef struct UHCI_QH { 159 uint32_t link; 160 uint32_t el_link; 161 } UHCI_QH; 162 163 static inline int32_t uhci_queue_token(UHCI_TD *td) 164 { 165 /* covers ep, dev, pid -> identifies the endpoint */ 166 return td->token & 0x7ffff; 167 } 168 169 static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td) 170 { 171 uint32_t token = uhci_queue_token(td); 172 UHCIQueue *queue; 173 174 QTAILQ_FOREACH(queue, &s->queues, next) { 175 if (queue->token == token) { 176 return queue; 177 } 178 } 179 180 queue = g_new0(UHCIQueue, 1); 181 queue->uhci = s; 182 queue->token = token; 183 QTAILQ_INIT(&queue->asyncs); 184 QTAILQ_INSERT_HEAD(&s->queues, queue, next); 185 trace_usb_uhci_queue_add(queue->token); 186 return queue; 187 } 188 189 static void uhci_queue_free(UHCIQueue *queue) 190 { 191 UHCIState *s = queue->uhci; 192 193 trace_usb_uhci_queue_del(queue->token); 194 QTAILQ_REMOVE(&s->queues, queue, next); 195 g_free(queue); 196 } 197 198 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr) 199 { 200 UHCIAsync *async = g_new0(UHCIAsync, 1); 201 202 async->queue = queue; 203 async->td = addr; 204 usb_packet_init(&async->packet); 205 pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1); 206 trace_usb_uhci_packet_add(async->queue->token, async->td); 207 208 return async; 209 } 210 211 static void uhci_async_free(UHCIAsync *async) 212 { 213 trace_usb_uhci_packet_del(async->queue->token, async->td); 214 usb_packet_cleanup(&async->packet); 215 qemu_sglist_destroy(&async->sgl); 216 g_free(async); 217 } 218 219 static void uhci_async_link(UHCIAsync *async) 220 { 221 UHCIQueue *queue = async->queue; 222 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); 223 trace_usb_uhci_packet_link_async(async->queue->token, async->td); 224 } 225 226 static void uhci_async_unlink(UHCIAsync *async) 227 { 228 UHCIQueue *queue = async->queue; 229 QTAILQ_REMOVE(&queue->asyncs, async, next); 230 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td); 231 } 232 233 static void uhci_async_cancel(UHCIAsync *async) 234 { 235 uhci_async_unlink(async); 236 trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done); 237 if (!async->done) 238 usb_cancel_packet(&async->packet); 239 usb_packet_unmap(&async->packet, &async->sgl); 240 uhci_async_free(async); 241 } 242 243 /* 244 * Mark all outstanding async packets as invalid. 245 * This is used for canceling them when TDs are removed by the HCD. 246 */ 247 static void uhci_async_validate_begin(UHCIState *s) 248 { 249 UHCIQueue *queue; 250 251 QTAILQ_FOREACH(queue, &s->queues, next) { 252 queue->valid--; 253 } 254 } 255 256 /* 257 * Cancel async packets that are no longer valid 258 */ 259 static void uhci_async_validate_end(UHCIState *s) 260 { 261 UHCIQueue *queue, *n; 262 UHCIAsync *async; 263 264 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { 265 if (queue->valid > 0) { 266 continue; 267 } 268 while (!QTAILQ_EMPTY(&queue->asyncs)) { 269 async = QTAILQ_FIRST(&queue->asyncs); 270 uhci_async_cancel(async); 271 } 272 uhci_queue_free(queue); 273 } 274 } 275 276 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) 277 { 278 UHCIQueue *queue; 279 UHCIAsync *curr, *n; 280 281 QTAILQ_FOREACH(queue, &s->queues, next) { 282 QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { 283 if (!usb_packet_is_inflight(&curr->packet) || 284 curr->packet.ep->dev != dev) { 285 continue; 286 } 287 uhci_async_cancel(curr); 288 } 289 } 290 } 291 292 static void uhci_async_cancel_all(UHCIState *s) 293 { 294 UHCIQueue *queue, *nq; 295 UHCIAsync *curr, *n; 296 297 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) { 298 QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { 299 uhci_async_cancel(curr); 300 } 301 uhci_queue_free(queue); 302 } 303 } 304 305 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td) 306 { 307 uint32_t token = uhci_queue_token(td); 308 UHCIQueue *queue; 309 UHCIAsync *async; 310 311 QTAILQ_FOREACH(queue, &s->queues, next) { 312 if (queue->token == token) { 313 break; 314 } 315 } 316 if (queue == NULL) { 317 return NULL; 318 } 319 320 QTAILQ_FOREACH(async, &queue->asyncs, next) { 321 if (async->td == addr) { 322 return async; 323 } 324 } 325 326 return NULL; 327 } 328 329 static void uhci_update_irq(UHCIState *s) 330 { 331 int level; 332 if (((s->status2 & 1) && (s->intr & (1 << 2))) || 333 ((s->status2 & 2) && (s->intr & (1 << 3))) || 334 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || 335 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || 336 (s->status & UHCI_STS_HSERR) || 337 (s->status & UHCI_STS_HCPERR)) { 338 level = 1; 339 } else { 340 level = 0; 341 } 342 qemu_set_irq(s->dev.irq[s->irq_pin], level); 343 } 344 345 static void uhci_reset(void *opaque) 346 { 347 UHCIState *s = opaque; 348 uint8_t *pci_conf; 349 int i; 350 UHCIPort *port; 351 352 trace_usb_uhci_reset(); 353 354 pci_conf = s->dev.config; 355 356 pci_conf[0x6a] = 0x01; /* usb clock */ 357 pci_conf[0x6b] = 0x00; 358 s->cmd = 0; 359 s->status = 0; 360 s->status2 = 0; 361 s->intr = 0; 362 s->fl_base_addr = 0; 363 s->sof_timing = 64; 364 365 for(i = 0; i < NB_PORTS; i++) { 366 port = &s->ports[i]; 367 port->ctrl = 0x0080; 368 if (port->port.dev && port->port.dev->attached) { 369 usb_port_reset(&port->port); 370 } 371 } 372 373 uhci_async_cancel_all(s); 374 qemu_bh_cancel(s->bh); 375 uhci_update_irq(s); 376 } 377 378 static const VMStateDescription vmstate_uhci_port = { 379 .name = "uhci port", 380 .version_id = 1, 381 .minimum_version_id = 1, 382 .minimum_version_id_old = 1, 383 .fields = (VMStateField []) { 384 VMSTATE_UINT16(ctrl, UHCIPort), 385 VMSTATE_END_OF_LIST() 386 } 387 }; 388 389 static int uhci_post_load(void *opaque, int version_id) 390 { 391 UHCIState *s = opaque; 392 393 if (version_id < 2) { 394 s->expire_time = qemu_get_clock_ns(vm_clock) + 395 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 396 } 397 return 0; 398 } 399 400 static const VMStateDescription vmstate_uhci = { 401 .name = "uhci", 402 .version_id = 2, 403 .minimum_version_id = 1, 404 .minimum_version_id_old = 1, 405 .post_load = uhci_post_load, 406 .fields = (VMStateField []) { 407 VMSTATE_PCI_DEVICE(dev, UHCIState), 408 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), 409 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, 410 vmstate_uhci_port, UHCIPort), 411 VMSTATE_UINT16(cmd, UHCIState), 412 VMSTATE_UINT16(status, UHCIState), 413 VMSTATE_UINT16(intr, UHCIState), 414 VMSTATE_UINT16(frnum, UHCIState), 415 VMSTATE_UINT32(fl_base_addr, UHCIState), 416 VMSTATE_UINT8(sof_timing, UHCIState), 417 VMSTATE_UINT8(status2, UHCIState), 418 VMSTATE_TIMER(frame_timer, UHCIState), 419 VMSTATE_INT64_V(expire_time, UHCIState, 2), 420 VMSTATE_END_OF_LIST() 421 } 422 }; 423 424 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) 425 { 426 UHCIState *s = opaque; 427 428 addr &= 0x1f; 429 switch(addr) { 430 case 0x0c: 431 s->sof_timing = val; 432 break; 433 } 434 } 435 436 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) 437 { 438 UHCIState *s = opaque; 439 uint32_t val; 440 441 addr &= 0x1f; 442 switch(addr) { 443 case 0x0c: 444 val = s->sof_timing; 445 break; 446 default: 447 val = 0xff; 448 break; 449 } 450 return val; 451 } 452 453 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) 454 { 455 UHCIState *s = opaque; 456 457 addr &= 0x1f; 458 trace_usb_uhci_mmio_writew(addr, val); 459 460 switch(addr) { 461 case 0x00: 462 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { 463 /* start frame processing */ 464 trace_usb_uhci_schedule_start(); 465 s->expire_time = qemu_get_clock_ns(vm_clock) + 466 (get_ticks_per_sec() / FRAME_TIMER_FREQ); 467 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); 468 s->status &= ~UHCI_STS_HCHALTED; 469 } else if (!(val & UHCI_CMD_RS)) { 470 s->status |= UHCI_STS_HCHALTED; 471 } 472 if (val & UHCI_CMD_GRESET) { 473 UHCIPort *port; 474 int i; 475 476 /* send reset on the USB bus */ 477 for(i = 0; i < NB_PORTS; i++) { 478 port = &s->ports[i]; 479 usb_device_reset(port->port.dev); 480 } 481 uhci_reset(s); 482 return; 483 } 484 if (val & UHCI_CMD_HCRESET) { 485 uhci_reset(s); 486 return; 487 } 488 s->cmd = val; 489 break; 490 case 0x02: 491 s->status &= ~val; 492 /* XXX: the chip spec is not coherent, so we add a hidden 493 register to distinguish between IOC and SPD */ 494 if (val & UHCI_STS_USBINT) 495 s->status2 = 0; 496 uhci_update_irq(s); 497 break; 498 case 0x04: 499 s->intr = val; 500 uhci_update_irq(s); 501 break; 502 case 0x06: 503 if (s->status & UHCI_STS_HCHALTED) 504 s->frnum = val & 0x7ff; 505 break; 506 case 0x10 ... 0x1f: 507 { 508 UHCIPort *port; 509 USBDevice *dev; 510 int n; 511 512 n = (addr >> 1) & 7; 513 if (n >= NB_PORTS) 514 return; 515 port = &s->ports[n]; 516 dev = port->port.dev; 517 if (dev && dev->attached) { 518 /* port reset */ 519 if ( (val & UHCI_PORT_RESET) && 520 !(port->ctrl & UHCI_PORT_RESET) ) { 521 usb_device_reset(dev); 522 } 523 } 524 port->ctrl &= UHCI_PORT_READ_ONLY; 525 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); 526 /* some bits are reset when a '1' is written to them */ 527 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); 528 } 529 break; 530 } 531 } 532 533 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) 534 { 535 UHCIState *s = opaque; 536 uint32_t val; 537 538 addr &= 0x1f; 539 switch(addr) { 540 case 0x00: 541 val = s->cmd; 542 break; 543 case 0x02: 544 val = s->status; 545 break; 546 case 0x04: 547 val = s->intr; 548 break; 549 case 0x06: 550 val = s->frnum; 551 break; 552 case 0x10 ... 0x1f: 553 { 554 UHCIPort *port; 555 int n; 556 n = (addr >> 1) & 7; 557 if (n >= NB_PORTS) 558 goto read_default; 559 port = &s->ports[n]; 560 val = port->ctrl; 561 } 562 break; 563 default: 564 read_default: 565 val = 0xff7f; /* disabled port */ 566 break; 567 } 568 569 trace_usb_uhci_mmio_readw(addr, val); 570 571 return val; 572 } 573 574 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) 575 { 576 UHCIState *s = opaque; 577 578 addr &= 0x1f; 579 trace_usb_uhci_mmio_writel(addr, val); 580 581 switch(addr) { 582 case 0x08: 583 s->fl_base_addr = val & ~0xfff; 584 break; 585 } 586 } 587 588 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) 589 { 590 UHCIState *s = opaque; 591 uint32_t val; 592 593 addr &= 0x1f; 594 switch(addr) { 595 case 0x08: 596 val = s->fl_base_addr; 597 break; 598 default: 599 val = 0xffffffff; 600 break; 601 } 602 trace_usb_uhci_mmio_readl(addr, val); 603 return val; 604 } 605 606 /* signal resume if controller suspended */ 607 static void uhci_resume (void *opaque) 608 { 609 UHCIState *s = (UHCIState *)opaque; 610 611 if (!s) 612 return; 613 614 if (s->cmd & UHCI_CMD_EGSM) { 615 s->cmd |= UHCI_CMD_FGR; 616 s->status |= UHCI_STS_RD; 617 uhci_update_irq(s); 618 } 619 } 620 621 static void uhci_attach(USBPort *port1) 622 { 623 UHCIState *s = port1->opaque; 624 UHCIPort *port = &s->ports[port1->index]; 625 626 /* set connect status */ 627 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; 628 629 /* update speed */ 630 if (port->port.dev->speed == USB_SPEED_LOW) { 631 port->ctrl |= UHCI_PORT_LSDA; 632 } else { 633 port->ctrl &= ~UHCI_PORT_LSDA; 634 } 635 636 uhci_resume(s); 637 } 638 639 static void uhci_detach(USBPort *port1) 640 { 641 UHCIState *s = port1->opaque; 642 UHCIPort *port = &s->ports[port1->index]; 643 644 uhci_async_cancel_device(s, port1->dev); 645 646 /* set connect status */ 647 if (port->ctrl & UHCI_PORT_CCS) { 648 port->ctrl &= ~UHCI_PORT_CCS; 649 port->ctrl |= UHCI_PORT_CSC; 650 } 651 /* disable port */ 652 if (port->ctrl & UHCI_PORT_EN) { 653 port->ctrl &= ~UHCI_PORT_EN; 654 port->ctrl |= UHCI_PORT_ENC; 655 } 656 657 uhci_resume(s); 658 } 659 660 static void uhci_child_detach(USBPort *port1, USBDevice *child) 661 { 662 UHCIState *s = port1->opaque; 663 664 uhci_async_cancel_device(s, child); 665 } 666 667 static void uhci_wakeup(USBPort *port1) 668 { 669 UHCIState *s = port1->opaque; 670 UHCIPort *port = &s->ports[port1->index]; 671 672 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { 673 port->ctrl |= UHCI_PORT_RD; 674 uhci_resume(s); 675 } 676 } 677 678 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) 679 { 680 USBDevice *dev; 681 int i; 682 683 for (i = 0; i < NB_PORTS; i++) { 684 UHCIPort *port = &s->ports[i]; 685 if (!(port->ctrl & UHCI_PORT_EN)) { 686 continue; 687 } 688 dev = usb_find_device(&port->port, addr); 689 if (dev != NULL) { 690 return dev; 691 } 692 } 693 return NULL; 694 } 695 696 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) 697 { 698 int len = 0, max_len, err, ret; 699 uint8_t pid; 700 701 max_len = ((td->token >> 21) + 1) & 0x7ff; 702 pid = td->token & 0xff; 703 704 ret = async->packet.result; 705 706 if (td->ctrl & TD_CTRL_IOS) 707 td->ctrl &= ~TD_CTRL_ACTIVE; 708 709 if (ret < 0) 710 goto out; 711 712 len = async->packet.result; 713 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); 714 715 /* The NAK bit may have been set by a previous frame, so clear it 716 here. The docs are somewhat unclear, but win2k relies on this 717 behavior. */ 718 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); 719 if (td->ctrl & TD_CTRL_IOC) 720 *int_mask |= 0x01; 721 722 if (pid == USB_TOKEN_IN) { 723 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { 724 *int_mask |= 0x02; 725 /* short packet: do not update QH */ 726 trace_usb_uhci_packet_complete_shortxfer(async->queue->token, 727 async->td); 728 return TD_RESULT_NEXT_QH; 729 } 730 } 731 732 /* success */ 733 trace_usb_uhci_packet_complete_success(async->queue->token, async->td); 734 return TD_RESULT_COMPLETE; 735 736 out: 737 switch(ret) { 738 case USB_RET_NAK: 739 td->ctrl |= TD_CTRL_NAK; 740 return TD_RESULT_NEXT_QH; 741 742 case USB_RET_STALL: 743 td->ctrl |= TD_CTRL_STALL; 744 trace_usb_uhci_packet_complete_stall(async->queue->token, async->td); 745 err = TD_RESULT_NEXT_QH; 746 break; 747 748 case USB_RET_BABBLE: 749 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; 750 /* frame interrupted */ 751 trace_usb_uhci_packet_complete_babble(async->queue->token, async->td); 752 err = TD_RESULT_STOP_FRAME; 753 break; 754 755 case USB_RET_IOERROR: 756 case USB_RET_NODEV: 757 default: 758 td->ctrl |= TD_CTRL_TIMEOUT; 759 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); 760 trace_usb_uhci_packet_complete_error(async->queue->token, async->td); 761 err = TD_RESULT_NEXT_QH; 762 break; 763 } 764 765 td->ctrl &= ~TD_CTRL_ACTIVE; 766 s->status |= UHCI_STS_USBERR; 767 if (td->ctrl & TD_CTRL_IOC) { 768 *int_mask |= 0x01; 769 } 770 uhci_update_irq(s); 771 return err; 772 } 773 774 static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, 775 uint32_t *int_mask, bool queuing, 776 struct USBEndpoint **ep_ret) 777 { 778 UHCIAsync *async; 779 int len = 0, max_len; 780 uint8_t pid; 781 bool spd; 782 USBDevice *dev; 783 USBEndpoint *ep; 784 785 /* Is active ? */ 786 if (!(td->ctrl & TD_CTRL_ACTIVE)) { 787 /* 788 * ehci11d spec page 22: "Even if the Active bit in the TD is already 789 * cleared when the TD is fetched ... an IOC interrupt is generated" 790 */ 791 if (td->ctrl & TD_CTRL_IOC) { 792 *int_mask |= 0x01; 793 } 794 return TD_RESULT_NEXT_QH; 795 } 796 797 async = uhci_async_find_td(s, addr, td); 798 if (async) { 799 /* Already submitted */ 800 async->queue->valid = 32; 801 802 if (!async->done) 803 return TD_RESULT_ASYNC_CONT; 804 if (queuing) { 805 /* we are busy filling the queue, we are not prepared 806 to consume completed packages then, just leave them 807 in async state */ 808 return TD_RESULT_ASYNC_CONT; 809 } 810 811 uhci_async_unlink(async); 812 goto done; 813 } 814 815 /* Allocate new packet */ 816 async = uhci_async_alloc(uhci_queue_get(s, td), addr); 817 818 /* valid needs to be large enough to handle 10 frame delay 819 * for initial isochronous requests 820 */ 821 async->queue->valid = 32; 822 823 max_len = ((td->token >> 21) + 1) & 0x7ff; 824 pid = td->token & 0xff; 825 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0); 826 827 dev = uhci_find_device(s, (td->token >> 8) & 0x7f); 828 ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); 829 if (ep_ret) { 830 *ep_ret = ep; 831 } 832 usb_packet_setup(&async->packet, pid, ep, addr, spd, 833 (td->ctrl & TD_CTRL_IOC) != 0); 834 qemu_sglist_add(&async->sgl, td->buffer, max_len); 835 usb_packet_map(&async->packet, &async->sgl); 836 837 switch(pid) { 838 case USB_TOKEN_OUT: 839 case USB_TOKEN_SETUP: 840 len = usb_handle_packet(dev, &async->packet); 841 if (len >= 0) 842 len = max_len; 843 break; 844 845 case USB_TOKEN_IN: 846 len = usb_handle_packet(dev, &async->packet); 847 break; 848 849 default: 850 /* invalid pid : frame interrupted */ 851 usb_packet_unmap(&async->packet, &async->sgl); 852 uhci_async_free(async); 853 s->status |= UHCI_STS_HCPERR; 854 uhci_update_irq(s); 855 return TD_RESULT_STOP_FRAME; 856 } 857 858 if (len == USB_RET_ASYNC) { 859 uhci_async_link(async); 860 return TD_RESULT_ASYNC_START; 861 } 862 863 async->packet.result = len; 864 865 done: 866 len = uhci_complete_td(s, td, async, int_mask); 867 usb_packet_unmap(&async->packet, &async->sgl); 868 uhci_async_free(async); 869 return len; 870 } 871 872 static void uhci_async_complete(USBPort *port, USBPacket *packet) 873 { 874 UHCIAsync *async = container_of(packet, UHCIAsync, packet); 875 UHCIState *s = async->queue->uhci; 876 877 if (packet->result == USB_RET_REMOVE_FROM_QUEUE) { 878 uhci_async_unlink(async); 879 uhci_async_cancel(async); 880 return; 881 } 882 883 async->done = 1; 884 if (s->frame_bytes < s->frame_bandwidth) { 885 qemu_bh_schedule(s->bh); 886 } 887 } 888 889 static int is_valid(uint32_t link) 890 { 891 return (link & 1) == 0; 892 } 893 894 static int is_qh(uint32_t link) 895 { 896 return (link & 2) != 0; 897 } 898 899 static int depth_first(uint32_t link) 900 { 901 return (link & 4) != 0; 902 } 903 904 /* QH DB used for detecting QH loops */ 905 #define UHCI_MAX_QUEUES 128 906 typedef struct { 907 uint32_t addr[UHCI_MAX_QUEUES]; 908 int count; 909 } QhDb; 910 911 static void qhdb_reset(QhDb *db) 912 { 913 db->count = 0; 914 } 915 916 /* Add QH to DB. Returns 1 if already present or DB is full. */ 917 static int qhdb_insert(QhDb *db, uint32_t addr) 918 { 919 int i; 920 for (i = 0; i < db->count; i++) 921 if (db->addr[i] == addr) 922 return 1; 923 924 if (db->count >= UHCI_MAX_QUEUES) 925 return 1; 926 927 db->addr[db->count++] = addr; 928 return 0; 929 } 930 931 static void uhci_fill_queue(UHCIState *s, UHCI_TD *td, struct USBEndpoint *ep) 932 { 933 uint32_t int_mask = 0; 934 uint32_t plink = td->link; 935 uint32_t token = uhci_queue_token(td); 936 UHCI_TD ptd; 937 int ret; 938 939 while (is_valid(plink)) { 940 pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd)); 941 le32_to_cpus(&ptd.link); 942 le32_to_cpus(&ptd.ctrl); 943 le32_to_cpus(&ptd.token); 944 le32_to_cpus(&ptd.buffer); 945 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { 946 break; 947 } 948 if (uhci_queue_token(&ptd) != token) { 949 break; 950 } 951 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); 952 ret = uhci_handle_td(s, plink, &ptd, &int_mask, true, NULL); 953 if (ret == TD_RESULT_ASYNC_CONT) { 954 break; 955 } 956 assert(ret == TD_RESULT_ASYNC_START); 957 assert(int_mask == 0); 958 plink = ptd.link; 959 } 960 usb_device_flush_ep_queue(ep->dev, ep); 961 } 962 963 static void uhci_process_frame(UHCIState *s) 964 { 965 uint32_t frame_addr, link, old_td_ctrl, val, int_mask; 966 uint32_t curr_qh, td_count = 0; 967 struct USBEndpoint *curr_ep; 968 int cnt, ret; 969 UHCI_TD td; 970 UHCI_QH qh; 971 QhDb qhdb; 972 973 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); 974 975 pci_dma_read(&s->dev, frame_addr, &link, 4); 976 le32_to_cpus(&link); 977 978 int_mask = 0; 979 curr_qh = 0; 980 981 qhdb_reset(&qhdb); 982 983 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { 984 if (s->frame_bytes >= s->frame_bandwidth) { 985 /* We've reached the usb 1.1 bandwidth, which is 986 1280 bytes/frame, stop processing */ 987 trace_usb_uhci_frame_stop_bandwidth(); 988 break; 989 } 990 if (is_qh(link)) { 991 /* QH */ 992 trace_usb_uhci_qh_load(link & ~0xf); 993 994 if (qhdb_insert(&qhdb, link)) { 995 /* 996 * We're going in circles. Which is not a bug because 997 * HCD is allowed to do that as part of the BW management. 998 * 999 * Stop processing here if no transaction has been done 1000 * since we've been here last time. 1001 */ 1002 if (td_count == 0) { 1003 trace_usb_uhci_frame_loop_stop_idle(); 1004 break; 1005 } else { 1006 trace_usb_uhci_frame_loop_continue(); 1007 td_count = 0; 1008 qhdb_reset(&qhdb); 1009 qhdb_insert(&qhdb, link); 1010 } 1011 } 1012 1013 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); 1014 le32_to_cpus(&qh.link); 1015 le32_to_cpus(&qh.el_link); 1016 1017 if (!is_valid(qh.el_link)) { 1018 /* QH w/o elements */ 1019 curr_qh = 0; 1020 link = qh.link; 1021 } else { 1022 /* QH with elements */ 1023 curr_qh = link; 1024 link = qh.el_link; 1025 } 1026 continue; 1027 } 1028 1029 /* TD */ 1030 pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); 1031 le32_to_cpus(&td.link); 1032 le32_to_cpus(&td.ctrl); 1033 le32_to_cpus(&td.token); 1034 le32_to_cpus(&td.buffer); 1035 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); 1036 1037 old_td_ctrl = td.ctrl; 1038 ret = uhci_handle_td(s, link, &td, &int_mask, false, &curr_ep); 1039 if (old_td_ctrl != td.ctrl) { 1040 /* update the status bits of the TD */ 1041 val = cpu_to_le32(td.ctrl); 1042 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); 1043 } 1044 1045 switch (ret) { 1046 case TD_RESULT_STOP_FRAME: /* interrupted frame */ 1047 goto out; 1048 1049 case TD_RESULT_NEXT_QH: 1050 case TD_RESULT_ASYNC_CONT: 1051 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); 1052 link = curr_qh ? qh.link : td.link; 1053 continue; 1054 1055 case TD_RESULT_ASYNC_START: 1056 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); 1057 uhci_fill_queue(s, &td, curr_ep); 1058 link = curr_qh ? qh.link : td.link; 1059 continue; 1060 1061 case TD_RESULT_COMPLETE: 1062 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); 1063 link = td.link; 1064 td_count++; 1065 s->frame_bytes += (td.ctrl & 0x7ff) + 1; 1066 1067 if (curr_qh) { 1068 /* update QH element link */ 1069 qh.el_link = link; 1070 val = cpu_to_le32(qh.el_link); 1071 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); 1072 1073 if (!depth_first(link)) { 1074 /* done with this QH */ 1075 curr_qh = 0; 1076 link = qh.link; 1077 } 1078 } 1079 break; 1080 1081 default: 1082 assert(!"unknown return code"); 1083 } 1084 1085 /* go to the next entry */ 1086 } 1087 1088 out: 1089 s->pending_int_mask |= int_mask; 1090 } 1091 1092 static void uhci_bh(void *opaque) 1093 { 1094 UHCIState *s = opaque; 1095 uhci_process_frame(s); 1096 } 1097 1098 static void uhci_frame_timer(void *opaque) 1099 { 1100 UHCIState *s = opaque; 1101 1102 /* prepare the timer for the next frame */ 1103 s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); 1104 s->frame_bytes = 0; 1105 qemu_bh_cancel(s->bh); 1106 1107 if (!(s->cmd & UHCI_CMD_RS)) { 1108 /* Full stop */ 1109 trace_usb_uhci_schedule_stop(); 1110 qemu_del_timer(s->frame_timer); 1111 uhci_async_cancel_all(s); 1112 /* set hchalted bit in status - UHCI11D 2.1.2 */ 1113 s->status |= UHCI_STS_HCHALTED; 1114 return; 1115 } 1116 1117 /* Complete the previous frame */ 1118 if (s->pending_int_mask) { 1119 s->status2 |= s->pending_int_mask; 1120 s->status |= UHCI_STS_USBINT; 1121 uhci_update_irq(s); 1122 } 1123 s->pending_int_mask = 0; 1124 1125 /* Start new frame */ 1126 s->frnum = (s->frnum + 1) & 0x7ff; 1127 1128 trace_usb_uhci_frame_start(s->frnum); 1129 1130 uhci_async_validate_begin(s); 1131 1132 uhci_process_frame(s); 1133 1134 uhci_async_validate_end(s); 1135 1136 qemu_mod_timer(s->frame_timer, s->expire_time); 1137 } 1138 1139 static const MemoryRegionPortio uhci_portio[] = { 1140 { 0, 32, 2, .write = uhci_ioport_writew, }, 1141 { 0, 32, 2, .read = uhci_ioport_readw, }, 1142 { 0, 32, 4, .write = uhci_ioport_writel, }, 1143 { 0, 32, 4, .read = uhci_ioport_readl, }, 1144 { 0, 32, 1, .write = uhci_ioport_writeb, }, 1145 { 0, 32, 1, .read = uhci_ioport_readb, }, 1146 PORTIO_END_OF_LIST() 1147 }; 1148 1149 static const MemoryRegionOps uhci_ioport_ops = { 1150 .old_portio = uhci_portio, 1151 }; 1152 1153 static USBPortOps uhci_port_ops = { 1154 .attach = uhci_attach, 1155 .detach = uhci_detach, 1156 .child_detach = uhci_child_detach, 1157 .wakeup = uhci_wakeup, 1158 .complete = uhci_async_complete, 1159 }; 1160 1161 static USBBusOps uhci_bus_ops = { 1162 }; 1163 1164 static int usb_uhci_common_initfn(PCIDevice *dev) 1165 { 1166 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1167 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1168 uint8_t *pci_conf = s->dev.config; 1169 int i; 1170 1171 pci_conf[PCI_CLASS_PROG] = 0x00; 1172 /* TODO: reset value should be 0. */ 1173 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number 1174 1175 switch (pc->device_id) { 1176 case PCI_DEVICE_ID_INTEL_82801I_UHCI1: 1177 s->irq_pin = 0; /* A */ 1178 break; 1179 case PCI_DEVICE_ID_INTEL_82801I_UHCI2: 1180 s->irq_pin = 1; /* B */ 1181 break; 1182 case PCI_DEVICE_ID_INTEL_82801I_UHCI3: 1183 s->irq_pin = 2; /* C */ 1184 break; 1185 default: 1186 s->irq_pin = 3; /* D */ 1187 break; 1188 } 1189 pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1); 1190 1191 if (s->masterbus) { 1192 USBPort *ports[NB_PORTS]; 1193 for(i = 0; i < NB_PORTS; i++) { 1194 ports[i] = &s->ports[i].port; 1195 } 1196 if (usb_register_companion(s->masterbus, ports, NB_PORTS, 1197 s->firstport, s, &uhci_port_ops, 1198 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { 1199 return -1; 1200 } 1201 } else { 1202 usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); 1203 for (i = 0; i < NB_PORTS; i++) { 1204 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, 1205 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1206 } 1207 } 1208 s->bh = qemu_bh_new(uhci_bh, s); 1209 s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); 1210 s->num_ports_vmstate = NB_PORTS; 1211 QTAILQ_INIT(&s->queues); 1212 1213 qemu_register_reset(uhci_reset, s); 1214 1215 memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); 1216 /* Use region 4 for consistency with real hardware. BSD guests seem 1217 to rely on this. */ 1218 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); 1219 1220 return 0; 1221 } 1222 1223 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) 1224 { 1225 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1226 uint8_t *pci_conf = s->dev.config; 1227 1228 /* USB misc control 1/2 */ 1229 pci_set_long(pci_conf + 0x40,0x00001000); 1230 /* PM capability */ 1231 pci_set_long(pci_conf + 0x80,0x00020001); 1232 /* USB legacy support */ 1233 pci_set_long(pci_conf + 0xc0,0x00002000); 1234 1235 return usb_uhci_common_initfn(dev); 1236 } 1237 1238 static void usb_uhci_exit(PCIDevice *dev) 1239 { 1240 UHCIState *s = DO_UPCAST(UHCIState, dev, dev); 1241 1242 memory_region_destroy(&s->io_bar); 1243 } 1244 1245 static Property uhci_properties[] = { 1246 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), 1247 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), 1248 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), 1249 DEFINE_PROP_END_OF_LIST(), 1250 }; 1251 1252 static void piix3_uhci_class_init(ObjectClass *klass, void *data) 1253 { 1254 DeviceClass *dc = DEVICE_CLASS(klass); 1255 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1256 1257 k->init = usb_uhci_common_initfn; 1258 k->exit = usb_uhci_exit; 1259 k->vendor_id = PCI_VENDOR_ID_INTEL; 1260 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; 1261 k->revision = 0x01; 1262 k->class_id = PCI_CLASS_SERIAL_USB; 1263 dc->vmsd = &vmstate_uhci; 1264 dc->props = uhci_properties; 1265 } 1266 1267 static TypeInfo piix3_uhci_info = { 1268 .name = "piix3-usb-uhci", 1269 .parent = TYPE_PCI_DEVICE, 1270 .instance_size = sizeof(UHCIState), 1271 .class_init = piix3_uhci_class_init, 1272 }; 1273 1274 static void piix4_uhci_class_init(ObjectClass *klass, void *data) 1275 { 1276 DeviceClass *dc = DEVICE_CLASS(klass); 1277 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1278 1279 k->init = usb_uhci_common_initfn; 1280 k->exit = usb_uhci_exit; 1281 k->vendor_id = PCI_VENDOR_ID_INTEL; 1282 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; 1283 k->revision = 0x01; 1284 k->class_id = PCI_CLASS_SERIAL_USB; 1285 dc->vmsd = &vmstate_uhci; 1286 dc->props = uhci_properties; 1287 } 1288 1289 static TypeInfo piix4_uhci_info = { 1290 .name = "piix4-usb-uhci", 1291 .parent = TYPE_PCI_DEVICE, 1292 .instance_size = sizeof(UHCIState), 1293 .class_init = piix4_uhci_class_init, 1294 }; 1295 1296 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) 1297 { 1298 DeviceClass *dc = DEVICE_CLASS(klass); 1299 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1300 1301 k->init = usb_uhci_vt82c686b_initfn; 1302 k->exit = usb_uhci_exit; 1303 k->vendor_id = PCI_VENDOR_ID_VIA; 1304 k->device_id = PCI_DEVICE_ID_VIA_UHCI; 1305 k->revision = 0x01; 1306 k->class_id = PCI_CLASS_SERIAL_USB; 1307 dc->vmsd = &vmstate_uhci; 1308 dc->props = uhci_properties; 1309 } 1310 1311 static TypeInfo vt82c686b_uhci_info = { 1312 .name = "vt82c686b-usb-uhci", 1313 .parent = TYPE_PCI_DEVICE, 1314 .instance_size = sizeof(UHCIState), 1315 .class_init = vt82c686b_uhci_class_init, 1316 }; 1317 1318 static void ich9_uhci1_class_init(ObjectClass *klass, void *data) 1319 { 1320 DeviceClass *dc = DEVICE_CLASS(klass); 1321 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1322 1323 k->init = usb_uhci_common_initfn; 1324 k->vendor_id = PCI_VENDOR_ID_INTEL; 1325 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; 1326 k->revision = 0x03; 1327 k->class_id = PCI_CLASS_SERIAL_USB; 1328 dc->vmsd = &vmstate_uhci; 1329 dc->props = uhci_properties; 1330 } 1331 1332 static TypeInfo ich9_uhci1_info = { 1333 .name = "ich9-usb-uhci1", 1334 .parent = TYPE_PCI_DEVICE, 1335 .instance_size = sizeof(UHCIState), 1336 .class_init = ich9_uhci1_class_init, 1337 }; 1338 1339 static void ich9_uhci2_class_init(ObjectClass *klass, void *data) 1340 { 1341 DeviceClass *dc = DEVICE_CLASS(klass); 1342 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1343 1344 k->init = usb_uhci_common_initfn; 1345 k->vendor_id = PCI_VENDOR_ID_INTEL; 1346 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; 1347 k->revision = 0x03; 1348 k->class_id = PCI_CLASS_SERIAL_USB; 1349 dc->vmsd = &vmstate_uhci; 1350 dc->props = uhci_properties; 1351 } 1352 1353 static TypeInfo ich9_uhci2_info = { 1354 .name = "ich9-usb-uhci2", 1355 .parent = TYPE_PCI_DEVICE, 1356 .instance_size = sizeof(UHCIState), 1357 .class_init = ich9_uhci2_class_init, 1358 }; 1359 1360 static void ich9_uhci3_class_init(ObjectClass *klass, void *data) 1361 { 1362 DeviceClass *dc = DEVICE_CLASS(klass); 1363 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1364 1365 k->init = usb_uhci_common_initfn; 1366 k->vendor_id = PCI_VENDOR_ID_INTEL; 1367 k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; 1368 k->revision = 0x03; 1369 k->class_id = PCI_CLASS_SERIAL_USB; 1370 dc->vmsd = &vmstate_uhci; 1371 dc->props = uhci_properties; 1372 } 1373 1374 static TypeInfo ich9_uhci3_info = { 1375 .name = "ich9-usb-uhci3", 1376 .parent = TYPE_PCI_DEVICE, 1377 .instance_size = sizeof(UHCIState), 1378 .class_init = ich9_uhci3_class_init, 1379 }; 1380 1381 static void uhci_register_types(void) 1382 { 1383 type_register_static(&piix3_uhci_info); 1384 type_register_static(&piix4_uhci_info); 1385 type_register_static(&vt82c686b_uhci_info); 1386 type_register_static(&ich9_uhci1_info); 1387 type_register_static(&ich9_uhci2_info); 1388 type_register_static(&ich9_uhci3_info); 1389 } 1390 1391 type_init(uhci_register_types) 1392