1*bc4e68d3SJeuk Kim /* 2*bc4e68d3SJeuk Kim * QEMU UFS 3*bc4e68d3SJeuk Kim * 4*bc4e68d3SJeuk Kim * Copyright (c) 2023 Samsung Electronics Co., Ltd. All rights reserved. 5*bc4e68d3SJeuk Kim * 6*bc4e68d3SJeuk Kim * Written by Jeuk Kim <jeuk20.kim@samsung.com> 7*bc4e68d3SJeuk Kim * 8*bc4e68d3SJeuk Kim * SPDX-License-Identifier: GPL-2.0-or-later 9*bc4e68d3SJeuk Kim */ 10*bc4e68d3SJeuk Kim 11*bc4e68d3SJeuk Kim #ifndef HW_UFS_UFS_H 12*bc4e68d3SJeuk Kim #define HW_UFS_UFS_H 13*bc4e68d3SJeuk Kim 14*bc4e68d3SJeuk Kim #include "hw/pci/pci_device.h" 15*bc4e68d3SJeuk Kim #include "hw/scsi/scsi.h" 16*bc4e68d3SJeuk Kim #include "block/ufs.h" 17*bc4e68d3SJeuk Kim 18*bc4e68d3SJeuk Kim #define UFS_MAX_LUS 32 19*bc4e68d3SJeuk Kim #define UFS_BLOCK_SIZE 4096 20*bc4e68d3SJeuk Kim 21*bc4e68d3SJeuk Kim typedef struct UfsParams { 22*bc4e68d3SJeuk Kim char *serial; 23*bc4e68d3SJeuk Kim uint8_t nutrs; /* Number of UTP Transfer Request Slots */ 24*bc4e68d3SJeuk Kim uint8_t nutmrs; /* Number of UTP Task Management Request Slots */ 25*bc4e68d3SJeuk Kim } UfsParams; 26*bc4e68d3SJeuk Kim 27*bc4e68d3SJeuk Kim typedef struct UfsHc { 28*bc4e68d3SJeuk Kim PCIDevice parent_obj; 29*bc4e68d3SJeuk Kim MemoryRegion iomem; 30*bc4e68d3SJeuk Kim UfsReg reg; 31*bc4e68d3SJeuk Kim UfsParams params; 32*bc4e68d3SJeuk Kim uint32_t reg_size; 33*bc4e68d3SJeuk Kim 34*bc4e68d3SJeuk Kim qemu_irq irq; 35*bc4e68d3SJeuk Kim QEMUBH *doorbell_bh; 36*bc4e68d3SJeuk Kim QEMUBH *complete_bh; 37*bc4e68d3SJeuk Kim } UfsHc; 38*bc4e68d3SJeuk Kim 39*bc4e68d3SJeuk Kim #define TYPE_UFS "ufs" 40*bc4e68d3SJeuk Kim #define UFS(obj) OBJECT_CHECK(UfsHc, (obj), TYPE_UFS) 41*bc4e68d3SJeuk Kim 42*bc4e68d3SJeuk Kim #endif /* HW_UFS_UFS_H */ 43