1 /* 2 * ARM PrimeCell Timer modules. 3 * 4 * Copyright (c) 2005-2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "hw/sysbus.h" 12 #include "qemu/timer.h" 13 #include "hw/qdev.h" 14 #include "hw/irq.h" 15 #include "hw/ptimer.h" 16 #include "qemu/main-loop.h" 17 #include "qemu/module.h" 18 #include "qemu/log.h" 19 20 /* Common timer implementation. */ 21 22 #define TIMER_CTRL_ONESHOT (1 << 0) 23 #define TIMER_CTRL_32BIT (1 << 1) 24 #define TIMER_CTRL_DIV1 (0 << 2) 25 #define TIMER_CTRL_DIV16 (1 << 2) 26 #define TIMER_CTRL_DIV256 (2 << 2) 27 #define TIMER_CTRL_IE (1 << 5) 28 #define TIMER_CTRL_PERIODIC (1 << 6) 29 #define TIMER_CTRL_ENABLE (1 << 7) 30 31 typedef struct { 32 ptimer_state *timer; 33 uint32_t control; 34 uint32_t limit; 35 int freq; 36 int int_level; 37 qemu_irq irq; 38 } arm_timer_state; 39 40 /* Check all active timers, and schedule the next timer interrupt. */ 41 42 static void arm_timer_update(arm_timer_state *s) 43 { 44 /* Update interrupts. */ 45 if (s->int_level && (s->control & TIMER_CTRL_IE)) { 46 qemu_irq_raise(s->irq); 47 } else { 48 qemu_irq_lower(s->irq); 49 } 50 } 51 52 static uint32_t arm_timer_read(void *opaque, hwaddr offset) 53 { 54 arm_timer_state *s = (arm_timer_state *)opaque; 55 56 switch (offset >> 2) { 57 case 0: /* TimerLoad */ 58 case 6: /* TimerBGLoad */ 59 return s->limit; 60 case 1: /* TimerValue */ 61 return ptimer_get_count(s->timer); 62 case 2: /* TimerControl */ 63 return s->control; 64 case 4: /* TimerRIS */ 65 return s->int_level; 66 case 5: /* TimerMIS */ 67 if ((s->control & TIMER_CTRL_IE) == 0) 68 return 0; 69 return s->int_level; 70 default: 71 qemu_log_mask(LOG_GUEST_ERROR, 72 "%s: Bad offset %x\n", __func__, (int)offset); 73 return 0; 74 } 75 } 76 77 /* Reset the timer limit after settings have changed. */ 78 static void arm_timer_recalibrate(arm_timer_state *s, int reload) 79 { 80 uint32_t limit; 81 82 if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { 83 /* Free running. */ 84 if (s->control & TIMER_CTRL_32BIT) 85 limit = 0xffffffff; 86 else 87 limit = 0xffff; 88 } else { 89 /* Periodic. */ 90 limit = s->limit; 91 } 92 ptimer_set_limit(s->timer, limit, reload); 93 } 94 95 static void arm_timer_write(void *opaque, hwaddr offset, 96 uint32_t value) 97 { 98 arm_timer_state *s = (arm_timer_state *)opaque; 99 int freq; 100 101 switch (offset >> 2) { 102 case 0: /* TimerLoad */ 103 s->limit = value; 104 arm_timer_recalibrate(s, 1); 105 break; 106 case 1: /* TimerValue */ 107 /* ??? Linux seems to want to write to this readonly register. 108 Ignore it. */ 109 break; 110 case 2: /* TimerControl */ 111 if (s->control & TIMER_CTRL_ENABLE) { 112 /* Pause the timer if it is running. This may cause some 113 inaccuracy dure to rounding, but avoids a whole lot of other 114 messyness. */ 115 ptimer_stop(s->timer); 116 } 117 s->control = value; 118 freq = s->freq; 119 /* ??? Need to recalculate expiry time after changing divisor. */ 120 switch ((value >> 2) & 3) { 121 case 1: freq >>= 4; break; 122 case 2: freq >>= 8; break; 123 } 124 arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); 125 ptimer_set_freq(s->timer, freq); 126 if (s->control & TIMER_CTRL_ENABLE) { 127 /* Restart the timer if still enabled. */ 128 ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); 129 } 130 break; 131 case 3: /* TimerIntClr */ 132 s->int_level = 0; 133 break; 134 case 6: /* TimerBGLoad */ 135 s->limit = value; 136 arm_timer_recalibrate(s, 0); 137 break; 138 default: 139 qemu_log_mask(LOG_GUEST_ERROR, 140 "%s: Bad offset %x\n", __func__, (int)offset); 141 } 142 arm_timer_update(s); 143 } 144 145 static void arm_timer_tick(void *opaque) 146 { 147 arm_timer_state *s = (arm_timer_state *)opaque; 148 s->int_level = 1; 149 arm_timer_update(s); 150 } 151 152 static const VMStateDescription vmstate_arm_timer = { 153 .name = "arm_timer", 154 .version_id = 1, 155 .minimum_version_id = 1, 156 .fields = (VMStateField[]) { 157 VMSTATE_UINT32(control, arm_timer_state), 158 VMSTATE_UINT32(limit, arm_timer_state), 159 VMSTATE_INT32(int_level, arm_timer_state), 160 VMSTATE_PTIMER(timer, arm_timer_state), 161 VMSTATE_END_OF_LIST() 162 } 163 }; 164 165 static arm_timer_state *arm_timer_init(uint32_t freq) 166 { 167 arm_timer_state *s; 168 QEMUBH *bh; 169 170 s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); 171 s->freq = freq; 172 s->control = TIMER_CTRL_IE; 173 174 bh = qemu_bh_new(arm_timer_tick, s); 175 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 176 vmstate_register(NULL, -1, &vmstate_arm_timer, s); 177 return s; 178 } 179 180 /* ARM PrimeCell SP804 dual timer module. 181 * Docs at 182 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html 183 */ 184 185 #define TYPE_SP804 "sp804" 186 #define SP804(obj) OBJECT_CHECK(SP804State, (obj), TYPE_SP804) 187 188 typedef struct SP804State { 189 SysBusDevice parent_obj; 190 191 MemoryRegion iomem; 192 arm_timer_state *timer[2]; 193 uint32_t freq0, freq1; 194 int level[2]; 195 qemu_irq irq; 196 } SP804State; 197 198 static const uint8_t sp804_ids[] = { 199 /* Timer ID */ 200 0x04, 0x18, 0x14, 0, 201 /* PrimeCell ID */ 202 0xd, 0xf0, 0x05, 0xb1 203 }; 204 205 /* Merge the IRQs from the two component devices. */ 206 static void sp804_set_irq(void *opaque, int irq, int level) 207 { 208 SP804State *s = (SP804State *)opaque; 209 210 s->level[irq] = level; 211 qemu_set_irq(s->irq, s->level[0] || s->level[1]); 212 } 213 214 static uint64_t sp804_read(void *opaque, hwaddr offset, 215 unsigned size) 216 { 217 SP804State *s = (SP804State *)opaque; 218 219 if (offset < 0x20) { 220 return arm_timer_read(s->timer[0], offset); 221 } 222 if (offset < 0x40) { 223 return arm_timer_read(s->timer[1], offset - 0x20); 224 } 225 226 /* TimerPeriphID */ 227 if (offset >= 0xfe0 && offset <= 0xffc) { 228 return sp804_ids[(offset - 0xfe0) >> 2]; 229 } 230 231 switch (offset) { 232 /* Integration Test control registers, which we won't support */ 233 case 0xf00: /* TimerITCR */ 234 case 0xf04: /* TimerITOP (strictly write only but..) */ 235 qemu_log_mask(LOG_UNIMP, 236 "%s: integration test registers unimplemented\n", 237 __func__); 238 return 0; 239 } 240 241 qemu_log_mask(LOG_GUEST_ERROR, 242 "%s: Bad offset %x\n", __func__, (int)offset); 243 return 0; 244 } 245 246 static void sp804_write(void *opaque, hwaddr offset, 247 uint64_t value, unsigned size) 248 { 249 SP804State *s = (SP804State *)opaque; 250 251 if (offset < 0x20) { 252 arm_timer_write(s->timer[0], offset, value); 253 return; 254 } 255 256 if (offset < 0x40) { 257 arm_timer_write(s->timer[1], offset - 0x20, value); 258 return; 259 } 260 261 /* Technically we could be writing to the Test Registers, but not likely */ 262 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", 263 __func__, (int)offset); 264 } 265 266 static const MemoryRegionOps sp804_ops = { 267 .read = sp804_read, 268 .write = sp804_write, 269 .endianness = DEVICE_NATIVE_ENDIAN, 270 }; 271 272 static const VMStateDescription vmstate_sp804 = { 273 .name = "sp804", 274 .version_id = 1, 275 .minimum_version_id = 1, 276 .fields = (VMStateField[]) { 277 VMSTATE_INT32_ARRAY(level, SP804State, 2), 278 VMSTATE_END_OF_LIST() 279 } 280 }; 281 282 static void sp804_init(Object *obj) 283 { 284 SP804State *s = SP804(obj); 285 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 286 287 sysbus_init_irq(sbd, &s->irq); 288 memory_region_init_io(&s->iomem, obj, &sp804_ops, s, 289 "sp804", 0x1000); 290 sysbus_init_mmio(sbd, &s->iomem); 291 } 292 293 static void sp804_realize(DeviceState *dev, Error **errp) 294 { 295 SP804State *s = SP804(dev); 296 297 s->timer[0] = arm_timer_init(s->freq0); 298 s->timer[1] = arm_timer_init(s->freq1); 299 s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); 300 s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); 301 } 302 303 /* Integrator/CP timer module. */ 304 305 #define TYPE_INTEGRATOR_PIT "integrator_pit" 306 #define INTEGRATOR_PIT(obj) \ 307 OBJECT_CHECK(icp_pit_state, (obj), TYPE_INTEGRATOR_PIT) 308 309 typedef struct { 310 SysBusDevice parent_obj; 311 312 MemoryRegion iomem; 313 arm_timer_state *timer[3]; 314 } icp_pit_state; 315 316 static uint64_t icp_pit_read(void *opaque, hwaddr offset, 317 unsigned size) 318 { 319 icp_pit_state *s = (icp_pit_state *)opaque; 320 int n; 321 322 /* ??? Don't know the PrimeCell ID for this device. */ 323 n = offset >> 8; 324 if (n > 2) { 325 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); 326 return 0; 327 } 328 329 return arm_timer_read(s->timer[n], offset & 0xff); 330 } 331 332 static void icp_pit_write(void *opaque, hwaddr offset, 333 uint64_t value, unsigned size) 334 { 335 icp_pit_state *s = (icp_pit_state *)opaque; 336 int n; 337 338 n = offset >> 8; 339 if (n > 2) { 340 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); 341 return; 342 } 343 344 arm_timer_write(s->timer[n], offset & 0xff, value); 345 } 346 347 static const MemoryRegionOps icp_pit_ops = { 348 .read = icp_pit_read, 349 .write = icp_pit_write, 350 .endianness = DEVICE_NATIVE_ENDIAN, 351 }; 352 353 static void icp_pit_init(Object *obj) 354 { 355 icp_pit_state *s = INTEGRATOR_PIT(obj); 356 SysBusDevice *dev = SYS_BUS_DEVICE(obj); 357 358 /* Timer 0 runs at the system clock speed (40MHz). */ 359 s->timer[0] = arm_timer_init(40000000); 360 /* The other two timers run at 1MHz. */ 361 s->timer[1] = arm_timer_init(1000000); 362 s->timer[2] = arm_timer_init(1000000); 363 364 sysbus_init_irq(dev, &s->timer[0]->irq); 365 sysbus_init_irq(dev, &s->timer[1]->irq); 366 sysbus_init_irq(dev, &s->timer[2]->irq); 367 368 memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, 369 "icp_pit", 0x1000); 370 sysbus_init_mmio(dev, &s->iomem); 371 /* This device has no state to save/restore. The component timers will 372 save themselves. */ 373 } 374 375 static const TypeInfo icp_pit_info = { 376 .name = TYPE_INTEGRATOR_PIT, 377 .parent = TYPE_SYS_BUS_DEVICE, 378 .instance_size = sizeof(icp_pit_state), 379 .instance_init = icp_pit_init, 380 }; 381 382 static Property sp804_properties[] = { 383 DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), 384 DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), 385 DEFINE_PROP_END_OF_LIST(), 386 }; 387 388 static void sp804_class_init(ObjectClass *klass, void *data) 389 { 390 DeviceClass *k = DEVICE_CLASS(klass); 391 392 k->realize = sp804_realize; 393 k->props = sp804_properties; 394 k->vmsd = &vmstate_sp804; 395 } 396 397 static const TypeInfo sp804_info = { 398 .name = TYPE_SP804, 399 .parent = TYPE_SYS_BUS_DEVICE, 400 .instance_size = sizeof(SP804State), 401 .instance_init = sp804_init, 402 .class_init = sp804_class_init, 403 }; 404 405 static void arm_timer_register_types(void) 406 { 407 type_register_static(&icp_pit_info); 408 type_register_static(&sp804_info); 409 } 410 411 type_init(arm_timer_register_types) 412