1 /* 2 * ARM PrimeCell Timer modules. 3 * 4 * Copyright (c) 2005-2006 CodeSourcery. 5 * Written by Paul Brook 6 * 7 * This code is licensed under the GPL. 8 */ 9 10 #include "hw/sysbus.h" 11 #include "qemu/timer.h" 12 #include "qemu-common.h" 13 #include "hw/qdev.h" 14 #include "hw/ptimer.h" 15 16 /* Common timer implementation. */ 17 18 #define TIMER_CTRL_ONESHOT (1 << 0) 19 #define TIMER_CTRL_32BIT (1 << 1) 20 #define TIMER_CTRL_DIV1 (0 << 2) 21 #define TIMER_CTRL_DIV16 (1 << 2) 22 #define TIMER_CTRL_DIV256 (2 << 2) 23 #define TIMER_CTRL_IE (1 << 5) 24 #define TIMER_CTRL_PERIODIC (1 << 6) 25 #define TIMER_CTRL_ENABLE (1 << 7) 26 27 typedef struct { 28 ptimer_state *timer; 29 uint32_t control; 30 uint32_t limit; 31 int freq; 32 int int_level; 33 qemu_irq irq; 34 } arm_timer_state; 35 36 /* Check all active timers, and schedule the next timer interrupt. */ 37 38 static void arm_timer_update(arm_timer_state *s) 39 { 40 /* Update interrupts. */ 41 if (s->int_level && (s->control & TIMER_CTRL_IE)) { 42 qemu_irq_raise(s->irq); 43 } else { 44 qemu_irq_lower(s->irq); 45 } 46 } 47 48 static uint32_t arm_timer_read(void *opaque, hwaddr offset) 49 { 50 arm_timer_state *s = (arm_timer_state *)opaque; 51 52 switch (offset >> 2) { 53 case 0: /* TimerLoad */ 54 case 6: /* TimerBGLoad */ 55 return s->limit; 56 case 1: /* TimerValue */ 57 return ptimer_get_count(s->timer); 58 case 2: /* TimerControl */ 59 return s->control; 60 case 4: /* TimerRIS */ 61 return s->int_level; 62 case 5: /* TimerMIS */ 63 if ((s->control & TIMER_CTRL_IE) == 0) 64 return 0; 65 return s->int_level; 66 default: 67 qemu_log_mask(LOG_GUEST_ERROR, 68 "%s: Bad offset %x\n", __func__, (int)offset); 69 return 0; 70 } 71 } 72 73 /* Reset the timer limit after settings have changed. */ 74 static void arm_timer_recalibrate(arm_timer_state *s, int reload) 75 { 76 uint32_t limit; 77 78 if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { 79 /* Free running. */ 80 if (s->control & TIMER_CTRL_32BIT) 81 limit = 0xffffffff; 82 else 83 limit = 0xffff; 84 } else { 85 /* Periodic. */ 86 limit = s->limit; 87 } 88 ptimer_set_limit(s->timer, limit, reload); 89 } 90 91 static void arm_timer_write(void *opaque, hwaddr offset, 92 uint32_t value) 93 { 94 arm_timer_state *s = (arm_timer_state *)opaque; 95 int freq; 96 97 switch (offset >> 2) { 98 case 0: /* TimerLoad */ 99 s->limit = value; 100 arm_timer_recalibrate(s, 1); 101 break; 102 case 1: /* TimerValue */ 103 /* ??? Linux seems to want to write to this readonly register. 104 Ignore it. */ 105 break; 106 case 2: /* TimerControl */ 107 if (s->control & TIMER_CTRL_ENABLE) { 108 /* Pause the timer if it is running. This may cause some 109 inaccuracy dure to rounding, but avoids a whole lot of other 110 messyness. */ 111 ptimer_stop(s->timer); 112 } 113 s->control = value; 114 freq = s->freq; 115 /* ??? Need to recalculate expiry time after changing divisor. */ 116 switch ((value >> 2) & 3) { 117 case 1: freq >>= 4; break; 118 case 2: freq >>= 8; break; 119 } 120 arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); 121 ptimer_set_freq(s->timer, freq); 122 if (s->control & TIMER_CTRL_ENABLE) { 123 /* Restart the timer if still enabled. */ 124 ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); 125 } 126 break; 127 case 3: /* TimerIntClr */ 128 s->int_level = 0; 129 break; 130 case 6: /* TimerBGLoad */ 131 s->limit = value; 132 arm_timer_recalibrate(s, 0); 133 break; 134 default: 135 qemu_log_mask(LOG_GUEST_ERROR, 136 "%s: Bad offset %x\n", __func__, (int)offset); 137 } 138 arm_timer_update(s); 139 } 140 141 static void arm_timer_tick(void *opaque) 142 { 143 arm_timer_state *s = (arm_timer_state *)opaque; 144 s->int_level = 1; 145 arm_timer_update(s); 146 } 147 148 static const VMStateDescription vmstate_arm_timer = { 149 .name = "arm_timer", 150 .version_id = 1, 151 .minimum_version_id = 1, 152 .minimum_version_id_old = 1, 153 .fields = (VMStateField[]) { 154 VMSTATE_UINT32(control, arm_timer_state), 155 VMSTATE_UINT32(limit, arm_timer_state), 156 VMSTATE_INT32(int_level, arm_timer_state), 157 VMSTATE_PTIMER(timer, arm_timer_state), 158 VMSTATE_END_OF_LIST() 159 } 160 }; 161 162 static arm_timer_state *arm_timer_init(uint32_t freq) 163 { 164 arm_timer_state *s; 165 QEMUBH *bh; 166 167 s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); 168 s->freq = freq; 169 s->control = TIMER_CTRL_IE; 170 171 bh = qemu_bh_new(arm_timer_tick, s); 172 s->timer = ptimer_init(bh); 173 vmstate_register(NULL, -1, &vmstate_arm_timer, s); 174 return s; 175 } 176 177 /* ARM PrimeCell SP804 dual timer module. 178 * Docs at 179 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html 180 */ 181 182 #define TYPE_SP804 "sp804" 183 #define SP804(obj) OBJECT_CHECK(SP804State, (obj), TYPE_SP804) 184 185 typedef struct SP804State { 186 SysBusDevice parent_obj; 187 188 MemoryRegion iomem; 189 arm_timer_state *timer[2]; 190 uint32_t freq0, freq1; 191 int level[2]; 192 qemu_irq irq; 193 } SP804State; 194 195 static const uint8_t sp804_ids[] = { 196 /* Timer ID */ 197 0x04, 0x18, 0x14, 0, 198 /* PrimeCell ID */ 199 0xd, 0xf0, 0x05, 0xb1 200 }; 201 202 /* Merge the IRQs from the two component devices. */ 203 static void sp804_set_irq(void *opaque, int irq, int level) 204 { 205 SP804State *s = (SP804State *)opaque; 206 207 s->level[irq] = level; 208 qemu_set_irq(s->irq, s->level[0] || s->level[1]); 209 } 210 211 static uint64_t sp804_read(void *opaque, hwaddr offset, 212 unsigned size) 213 { 214 SP804State *s = (SP804State *)opaque; 215 216 if (offset < 0x20) { 217 return arm_timer_read(s->timer[0], offset); 218 } 219 if (offset < 0x40) { 220 return arm_timer_read(s->timer[1], offset - 0x20); 221 } 222 223 /* TimerPeriphID */ 224 if (offset >= 0xfe0 && offset <= 0xffc) { 225 return sp804_ids[(offset - 0xfe0) >> 2]; 226 } 227 228 switch (offset) { 229 /* Integration Test control registers, which we won't support */ 230 case 0xf00: /* TimerITCR */ 231 case 0xf04: /* TimerITOP (strictly write only but..) */ 232 qemu_log_mask(LOG_UNIMP, 233 "%s: integration test registers unimplemented\n", 234 __func__); 235 return 0; 236 } 237 238 qemu_log_mask(LOG_GUEST_ERROR, 239 "%s: Bad offset %x\n", __func__, (int)offset); 240 return 0; 241 } 242 243 static void sp804_write(void *opaque, hwaddr offset, 244 uint64_t value, unsigned size) 245 { 246 SP804State *s = (SP804State *)opaque; 247 248 if (offset < 0x20) { 249 arm_timer_write(s->timer[0], offset, value); 250 return; 251 } 252 253 if (offset < 0x40) { 254 arm_timer_write(s->timer[1], offset - 0x20, value); 255 return; 256 } 257 258 /* Technically we could be writing to the Test Registers, but not likely */ 259 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", 260 __func__, (int)offset); 261 } 262 263 static const MemoryRegionOps sp804_ops = { 264 .read = sp804_read, 265 .write = sp804_write, 266 .endianness = DEVICE_NATIVE_ENDIAN, 267 }; 268 269 static const VMStateDescription vmstate_sp804 = { 270 .name = "sp804", 271 .version_id = 1, 272 .minimum_version_id = 1, 273 .minimum_version_id_old = 1, 274 .fields = (VMStateField[]) { 275 VMSTATE_INT32_ARRAY(level, SP804State, 2), 276 VMSTATE_END_OF_LIST() 277 } 278 }; 279 280 static int sp804_init(SysBusDevice *sbd) 281 { 282 DeviceState *dev = DEVICE(sbd); 283 SP804State *s = SP804(dev); 284 qemu_irq *qi; 285 286 qi = qemu_allocate_irqs(sp804_set_irq, s, 2); 287 sysbus_init_irq(sbd, &s->irq); 288 s->timer[0] = arm_timer_init(s->freq0); 289 s->timer[1] = arm_timer_init(s->freq1); 290 s->timer[0]->irq = qi[0]; 291 s->timer[1]->irq = qi[1]; 292 memory_region_init_io(&s->iomem, OBJECT(s), &sp804_ops, s, 293 "sp804", 0x1000); 294 sysbus_init_mmio(sbd, &s->iomem); 295 vmstate_register(dev, -1, &vmstate_sp804, s); 296 return 0; 297 } 298 299 /* Integrator/CP timer module. */ 300 301 typedef struct { 302 SysBusDevice busdev; 303 MemoryRegion iomem; 304 arm_timer_state *timer[3]; 305 } icp_pit_state; 306 307 static uint64_t icp_pit_read(void *opaque, hwaddr offset, 308 unsigned size) 309 { 310 icp_pit_state *s = (icp_pit_state *)opaque; 311 int n; 312 313 /* ??? Don't know the PrimeCell ID for this device. */ 314 n = offset >> 8; 315 if (n > 2) { 316 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); 317 } 318 319 return arm_timer_read(s->timer[n], offset & 0xff); 320 } 321 322 static void icp_pit_write(void *opaque, hwaddr offset, 323 uint64_t value, unsigned size) 324 { 325 icp_pit_state *s = (icp_pit_state *)opaque; 326 int n; 327 328 n = offset >> 8; 329 if (n > 2) { 330 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); 331 } 332 333 arm_timer_write(s->timer[n], offset & 0xff, value); 334 } 335 336 static const MemoryRegionOps icp_pit_ops = { 337 .read = icp_pit_read, 338 .write = icp_pit_write, 339 .endianness = DEVICE_NATIVE_ENDIAN, 340 }; 341 342 static int icp_pit_init(SysBusDevice *dev) 343 { 344 icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev); 345 346 /* Timer 0 runs at the system clock speed (40MHz). */ 347 s->timer[0] = arm_timer_init(40000000); 348 /* The other two timers run at 1MHz. */ 349 s->timer[1] = arm_timer_init(1000000); 350 s->timer[2] = arm_timer_init(1000000); 351 352 sysbus_init_irq(dev, &s->timer[0]->irq); 353 sysbus_init_irq(dev, &s->timer[1]->irq); 354 sysbus_init_irq(dev, &s->timer[2]->irq); 355 356 memory_region_init_io(&s->iomem, OBJECT(s), &icp_pit_ops, s, 357 "icp_pit", 0x1000); 358 sysbus_init_mmio(dev, &s->iomem); 359 /* This device has no state to save/restore. The component timers will 360 save themselves. */ 361 return 0; 362 } 363 364 static void icp_pit_class_init(ObjectClass *klass, void *data) 365 { 366 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 367 368 sdc->init = icp_pit_init; 369 } 370 371 static const TypeInfo icp_pit_info = { 372 .name = "integrator_pit", 373 .parent = TYPE_SYS_BUS_DEVICE, 374 .instance_size = sizeof(icp_pit_state), 375 .class_init = icp_pit_class_init, 376 }; 377 378 static Property sp804_properties[] = { 379 DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), 380 DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), 381 DEFINE_PROP_END_OF_LIST(), 382 }; 383 384 static void sp804_class_init(ObjectClass *klass, void *data) 385 { 386 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); 387 DeviceClass *k = DEVICE_CLASS(klass); 388 389 sdc->init = sp804_init; 390 k->props = sp804_properties; 391 } 392 393 static const TypeInfo sp804_info = { 394 .name = TYPE_SP804, 395 .parent = TYPE_SYS_BUS_DEVICE, 396 .instance_size = sizeof(SP804State), 397 .class_init = sp804_class_init, 398 }; 399 400 static void arm_timer_register_types(void) 401 { 402 type_register_static(&icp_pit_info); 403 type_register_static(&sp804_info); 404 } 405 406 type_init(arm_timer_register_types) 407