1 /* 2 * SH7750 device 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Copyright (c) 2005 Samuel Tardieu 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/irq.h" 28 #include "hw/sh4/sh.h" 29 #include "sysemu/sysemu.h" 30 #include "sh7750_regs.h" 31 #include "sh7750_regnames.h" 32 #include "hw/sh4/sh_intc.h" 33 #include "hw/timer/tmu012.h" 34 #include "exec/exec-all.h" 35 #include "trace.h" 36 37 #define NB_DEVICES 4 38 39 typedef struct SH7750State { 40 MemoryRegion iomem; 41 MemoryRegion iomem_1f0; 42 MemoryRegion iomem_ff0; 43 MemoryRegion iomem_1f8; 44 MemoryRegion iomem_ff8; 45 MemoryRegion iomem_1fc; 46 MemoryRegion iomem_ffc; 47 MemoryRegion mmct_iomem; 48 /* CPU */ 49 SuperHCPU *cpu; 50 /* Peripheral frequency in Hz */ 51 uint32_t periph_freq; 52 /* SDRAM controller */ 53 uint32_t bcr1; 54 uint16_t bcr2; 55 uint16_t bcr3; 56 uint32_t bcr4; 57 uint16_t rfcr; 58 /* PCMCIA controller */ 59 uint16_t pcr; 60 /* IO ports */ 61 uint16_t gpioic; 62 uint32_t pctra; 63 uint32_t pctrb; 64 uint16_t portdira; /* Cached */ 65 uint16_t portpullupa; /* Cached */ 66 uint16_t portdirb; /* Cached */ 67 uint16_t portpullupb; /* Cached */ 68 uint16_t pdtra; 69 uint16_t pdtrb; 70 uint16_t periph_pdtra; /* Imposed by the peripherals */ 71 uint16_t periph_portdira; /* Direction seen from the peripherals */ 72 uint16_t periph_pdtrb; /* Imposed by the peripherals */ 73 uint16_t periph_portdirb; /* Direction seen from the peripherals */ 74 sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */ 75 76 /* Cache */ 77 uint32_t ccr; 78 79 struct intc_desc intc; 80 } SH7750State; 81 82 static inline int has_bcr3_and_bcr4(SH7750State *s) 83 { 84 return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4; 85 } 86 87 /* 88 * I/O ports 89 */ 90 91 int sh7750_register_io_device(SH7750State *s, sh7750_io_device *device) 92 { 93 int i; 94 95 for (i = 0; i < NB_DEVICES; i++) { 96 if (s->devices[i] == NULL) { 97 s->devices[i] = device; 98 return 0; 99 } 100 } 101 return -1; 102 } 103 104 static uint16_t portdir(uint32_t v) 105 { 106 #define EVENPORTMASK(n) ((v & (1 << ((n) << 1))) >> (n)) 107 return 108 EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | 109 EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | 110 EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | 111 EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | 112 EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | 113 EVENPORTMASK(0); 114 } 115 116 static uint16_t portpullup(uint32_t v) 117 { 118 #define ODDPORTMASK(n) ((v & (1 << (((n) << 1) + 1))) >> (n)) 119 return 120 ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | 121 ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | 122 ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | 123 ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | 124 ODDPORTMASK(1) | ODDPORTMASK(0); 125 } 126 127 static uint16_t porta_lines(SH7750State *s) 128 { 129 return (s->portdira & s->pdtra) | /* CPU */ 130 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ 131 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ 132 } 133 134 static uint16_t portb_lines(SH7750State *s) 135 { 136 return (s->portdirb & s->pdtrb) | /* CPU */ 137 (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ 138 (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ 139 } 140 141 static void gen_port_interrupts(SH7750State *s) 142 { 143 /* XXXXX interrupts not generated */ 144 } 145 146 static void porta_changed(SH7750State *s, uint16_t prev) 147 { 148 uint16_t currenta, changes; 149 int i, r = 0; 150 151 currenta = porta_lines(s); 152 if (currenta == prev) { 153 return; 154 } 155 trace_sh7750_porta(prev, currenta, s->pdtra, s->pctra); 156 changes = currenta ^ prev; 157 158 for (i = 0; i < NB_DEVICES; i++) { 159 if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) { 160 r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), 161 &s->periph_pdtra, 162 &s->periph_portdira, 163 &s->periph_pdtrb, 164 &s->periph_portdirb); 165 } 166 } 167 168 if (r) { 169 gen_port_interrupts(s); 170 } 171 } 172 173 static void portb_changed(SH7750State *s, uint16_t prev) 174 { 175 uint16_t currentb, changes; 176 int i, r = 0; 177 178 currentb = portb_lines(s); 179 if (currentb == prev) { 180 return; 181 } 182 trace_sh7750_portb(prev, currentb, s->pdtrb, s->pctrb); 183 changes = currentb ^ prev; 184 185 for (i = 0; i < NB_DEVICES; i++) { 186 if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) { 187 r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, 188 &s->periph_pdtra, 189 &s->periph_portdira, 190 &s->periph_pdtrb, 191 &s->periph_portdirb); 192 } 193 } 194 195 if (r) { 196 gen_port_interrupts(s); 197 } 198 } 199 200 /* 201 * Memory 202 */ 203 204 static void error_access(const char *kind, hwaddr addr) 205 { 206 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", 207 kind, regname(addr), addr); 208 } 209 210 static void ignore_access(const char *kind, hwaddr addr) 211 { 212 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", 213 kind, regname(addr), addr); 214 } 215 216 static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr) 217 { 218 switch (addr) { 219 default: 220 error_access("byte read", addr); 221 abort(); 222 } 223 } 224 225 static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) 226 { 227 SH7750State *s = opaque; 228 229 switch (addr) { 230 case SH7750_BCR2_A7: 231 return s->bcr2; 232 case SH7750_BCR3_A7: 233 if (!has_bcr3_and_bcr4(s)) { 234 error_access("word read", addr); 235 } 236 return s->bcr3; 237 case SH7750_FRQCR_A7: 238 return 0; 239 case SH7750_PCR_A7: 240 return s->pcr; 241 case SH7750_RFCR_A7: 242 fprintf(stderr, 243 "Read access to refresh count register, incrementing\n"); 244 return s->rfcr++; 245 case SH7750_PDTRA_A7: 246 return porta_lines(s); 247 case SH7750_PDTRB_A7: 248 return portb_lines(s); 249 case SH7750_RTCOR_A7: 250 case SH7750_RTCNT_A7: 251 case SH7750_RTCSR_A7: 252 ignore_access("word read", addr); 253 return 0; 254 default: 255 error_access("word read", addr); 256 abort(); 257 } 258 } 259 260 static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) 261 { 262 SH7750State *s = opaque; 263 SuperHCPUClass *scc; 264 265 switch (addr) { 266 case SH7750_BCR1_A7: 267 return s->bcr1; 268 case SH7750_BCR4_A7: 269 if (!has_bcr3_and_bcr4(s)) { 270 error_access("long read", addr); 271 } 272 return s->bcr4; 273 case SH7750_WCR1_A7: 274 case SH7750_WCR2_A7: 275 case SH7750_WCR3_A7: 276 case SH7750_MCR_A7: 277 ignore_access("long read", addr); 278 return 0; 279 case SH7750_MMUCR_A7: 280 return s->cpu->env.mmucr; 281 case SH7750_PTEH_A7: 282 return s->cpu->env.pteh; 283 case SH7750_PTEL_A7: 284 return s->cpu->env.ptel; 285 case SH7750_TTB_A7: 286 return s->cpu->env.ttb; 287 case SH7750_TEA_A7: 288 return s->cpu->env.tea; 289 case SH7750_TRA_A7: 290 return s->cpu->env.tra; 291 case SH7750_EXPEVT_A7: 292 return s->cpu->env.expevt; 293 case SH7750_INTEVT_A7: 294 return s->cpu->env.intevt; 295 case SH7750_CCR_A7: 296 return s->ccr; 297 case 0x1f000030: /* Processor version */ 298 scc = SUPERH_CPU_GET_CLASS(s->cpu); 299 return scc->pvr; 300 case 0x1f000040: /* Cache version */ 301 scc = SUPERH_CPU_GET_CLASS(s->cpu); 302 return scc->cvr; 303 case 0x1f000044: /* Processor revision */ 304 scc = SUPERH_CPU_GET_CLASS(s->cpu); 305 return scc->prr; 306 default: 307 error_access("long read", addr); 308 abort(); 309 } 310 } 311 312 #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ 313 && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) 314 static void sh7750_mem_writeb(void *opaque, hwaddr addr, 315 uint32_t mem_value) 316 { 317 318 if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { 319 ignore_access("byte write", addr); 320 return; 321 } 322 323 error_access("byte write", addr); 324 abort(); 325 } 326 327 static void sh7750_mem_writew(void *opaque, hwaddr addr, 328 uint32_t mem_value) 329 { 330 SH7750State *s = opaque; 331 uint16_t temp; 332 333 switch (addr) { 334 /* SDRAM controller */ 335 case SH7750_BCR2_A7: 336 s->bcr2 = mem_value; 337 return; 338 case SH7750_BCR3_A7: 339 if (!has_bcr3_and_bcr4(s)) { 340 error_access("word write", addr); 341 } 342 s->bcr3 = mem_value; 343 return; 344 case SH7750_PCR_A7: 345 s->pcr = mem_value; 346 return; 347 case SH7750_RTCNT_A7: 348 case SH7750_RTCOR_A7: 349 case SH7750_RTCSR_A7: 350 ignore_access("word write", addr); 351 return; 352 /* IO ports */ 353 case SH7750_PDTRA_A7: 354 temp = porta_lines(s); 355 s->pdtra = mem_value; 356 porta_changed(s, temp); 357 return; 358 case SH7750_PDTRB_A7: 359 temp = portb_lines(s); 360 s->pdtrb = mem_value; 361 portb_changed(s, temp); 362 return; 363 case SH7750_RFCR_A7: 364 fprintf(stderr, "Write access to refresh count register\n"); 365 s->rfcr = mem_value; 366 return; 367 case SH7750_GPIOIC_A7: 368 s->gpioic = mem_value; 369 if (mem_value != 0) { 370 fprintf(stderr, "I/O interrupts not implemented\n"); 371 abort(); 372 } 373 return; 374 default: 375 error_access("word write", addr); 376 abort(); 377 } 378 } 379 380 static void sh7750_mem_writel(void *opaque, hwaddr addr, 381 uint32_t mem_value) 382 { 383 SH7750State *s = opaque; 384 uint16_t temp; 385 386 switch (addr) { 387 /* SDRAM controller */ 388 case SH7750_BCR1_A7: 389 s->bcr1 = mem_value; 390 return; 391 case SH7750_BCR4_A7: 392 if (!has_bcr3_and_bcr4(s)) { 393 error_access("long write", addr); 394 } 395 s->bcr4 = mem_value; 396 return; 397 case SH7750_WCR1_A7: 398 case SH7750_WCR2_A7: 399 case SH7750_WCR3_A7: 400 case SH7750_MCR_A7: 401 ignore_access("long write", addr); 402 return; 403 /* IO ports */ 404 case SH7750_PCTRA_A7: 405 temp = porta_lines(s); 406 s->pctra = mem_value; 407 s->portdira = portdir(mem_value); 408 s->portpullupa = portpullup(mem_value); 409 porta_changed(s, temp); 410 return; 411 case SH7750_PCTRB_A7: 412 temp = portb_lines(s); 413 s->pctrb = mem_value; 414 s->portdirb = portdir(mem_value); 415 s->portpullupb = portpullup(mem_value); 416 portb_changed(s, temp); 417 return; 418 case SH7750_MMUCR_A7: 419 if (mem_value & MMUCR_TI) { 420 cpu_sh4_invalidate_tlb(&s->cpu->env); 421 } 422 s->cpu->env.mmucr = mem_value & ~MMUCR_TI; 423 return; 424 case SH7750_PTEH_A7: 425 /* If asid changes, clear all registered tlb entries. */ 426 if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) { 427 tlb_flush(CPU(s->cpu)); 428 } 429 s->cpu->env.pteh = mem_value; 430 return; 431 case SH7750_PTEL_A7: 432 s->cpu->env.ptel = mem_value; 433 return; 434 case SH7750_PTEA_A7: 435 s->cpu->env.ptea = mem_value & 0x0000000f; 436 return; 437 case SH7750_TTB_A7: 438 s->cpu->env.ttb = mem_value; 439 return; 440 case SH7750_TEA_A7: 441 s->cpu->env.tea = mem_value; 442 return; 443 case SH7750_TRA_A7: 444 s->cpu->env.tra = mem_value & 0x000007ff; 445 return; 446 case SH7750_EXPEVT_A7: 447 s->cpu->env.expevt = mem_value & 0x000007ff; 448 return; 449 case SH7750_INTEVT_A7: 450 s->cpu->env.intevt = mem_value & 0x000007ff; 451 return; 452 case SH7750_CCR_A7: 453 s->ccr = mem_value; 454 return; 455 default: 456 error_access("long write", addr); 457 abort(); 458 } 459 } 460 461 static uint64_t sh7750_mem_readfn(void *opaque, hwaddr addr, unsigned size) 462 { 463 switch (size) { 464 case 1: 465 return sh7750_mem_readb(opaque, addr); 466 case 2: 467 return sh7750_mem_readw(opaque, addr); 468 case 4: 469 return sh7750_mem_readl(opaque, addr); 470 default: 471 g_assert_not_reached(); 472 } 473 } 474 475 static void sh7750_mem_writefn(void *opaque, hwaddr addr, 476 uint64_t value, unsigned size) 477 { 478 switch (size) { 479 case 1: 480 sh7750_mem_writeb(opaque, addr, value); 481 break; 482 case 2: 483 sh7750_mem_writew(opaque, addr, value); 484 break; 485 case 4: 486 sh7750_mem_writel(opaque, addr, value); 487 break; 488 default: 489 g_assert_not_reached(); 490 } 491 } 492 493 static const MemoryRegionOps sh7750_mem_ops = { 494 .read = sh7750_mem_readfn, 495 .write = sh7750_mem_writefn, 496 .valid.min_access_size = 1, 497 .valid.max_access_size = 4, 498 .endianness = DEVICE_NATIVE_ENDIAN, 499 }; 500 501 /* 502 * sh775x interrupt controller tables for sh_intc.c 503 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c 504 */ 505 506 enum { 507 UNUSED = 0, 508 509 /* interrupt sources */ 510 IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, 511 IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, 512 IRL0, IRL1, IRL2, IRL3, 513 HUDI, GPIOI, 514 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, 515 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, 516 DMAC_DMAE, 517 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 518 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 519 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 520 RTC_ATI, RTC_PRI, RTC_CUI, 521 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, 522 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, 523 WDT, 524 REF_RCMI, REF_ROVI, 525 526 /* interrupt groups */ 527 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, 528 /* irl bundle */ 529 IRL, 530 531 NR_SOURCES, 532 }; 533 534 static struct intc_vect vectors[] = { 535 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 536 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 537 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 538 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 539 INTC_VECT(RTC_CUI, 0x4c0), 540 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), 541 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), 542 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), 543 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), 544 INTC_VECT(WDT, 0x560), 545 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 546 }; 547 548 static struct intc_group groups[] = { 549 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), 550 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 551 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), 552 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), 553 INTC_GROUP(REF, REF_RCMI, REF_ROVI), 554 }; 555 556 static struct intc_prio_reg prio_registers[] = { 557 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 558 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 559 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 560 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 561 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, TMU4, TMU3, 562 PCIC1, PCIC0_PCISERR } }, 563 }; 564 565 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 566 567 static struct intc_vect vectors_dma4[] = { 568 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 569 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 570 INTC_VECT(DMAC_DMAE, 0x6c0), 571 }; 572 573 static struct intc_group groups_dma4[] = { 574 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 575 DMAC_DMTE3, DMAC_DMAE), 576 }; 577 578 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 579 580 static struct intc_vect vectors_dma8[] = { 581 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 582 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 583 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 584 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 585 INTC_VECT(DMAC_DMAE, 0x6c0), 586 }; 587 588 static struct intc_group groups_dma8[] = { 589 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 590 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, 591 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), 592 }; 593 594 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 595 596 static struct intc_vect vectors_tmu34[] = { 597 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 598 }; 599 600 static struct intc_mask_reg mask_registers[] = { 601 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 602 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 603 0, 0, 0, 0, 0, 0, TMU4, TMU3, 604 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 605 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 606 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 607 }; 608 609 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 610 611 static struct intc_vect vectors_irlm[] = { 612 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 613 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 614 }; 615 616 /* SH7751 and SH7751R both have PCI */ 617 618 static struct intc_vect vectors_pci[] = { 619 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 620 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 621 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 622 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 623 }; 624 625 static struct intc_group groups_pci[] = { 626 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 627 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 628 }; 629 630 static struct intc_vect vectors_irl[] = { 631 INTC_VECT(IRL_0, 0x200), 632 INTC_VECT(IRL_1, 0x220), 633 INTC_VECT(IRL_2, 0x240), 634 INTC_VECT(IRL_3, 0x260), 635 INTC_VECT(IRL_4, 0x280), 636 INTC_VECT(IRL_5, 0x2a0), 637 INTC_VECT(IRL_6, 0x2c0), 638 INTC_VECT(IRL_7, 0x2e0), 639 INTC_VECT(IRL_8, 0x300), 640 INTC_VECT(IRL_9, 0x320), 641 INTC_VECT(IRL_A, 0x340), 642 INTC_VECT(IRL_B, 0x360), 643 INTC_VECT(IRL_C, 0x380), 644 INTC_VECT(IRL_D, 0x3a0), 645 INTC_VECT(IRL_E, 0x3c0), 646 }; 647 648 static struct intc_group groups_irl[] = { 649 INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, 650 IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), 651 }; 652 653 /* 654 * Memory mapped cache and TLB 655 */ 656 657 #define MM_REGION_MASK 0x07000000 658 #define MM_ICACHE_ADDR (0) 659 #define MM_ICACHE_DATA (1) 660 #define MM_ITLB_ADDR (2) 661 #define MM_ITLB_DATA (3) 662 #define MM_OCACHE_ADDR (4) 663 #define MM_OCACHE_DATA (5) 664 #define MM_UTLB_ADDR (6) 665 #define MM_UTLB_DATA (7) 666 #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) 667 668 static uint64_t invalid_read(void *opaque, hwaddr addr) 669 { 670 abort(); 671 672 return 0; 673 } 674 675 static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr, 676 unsigned size) 677 { 678 SH7750State *s = opaque; 679 uint32_t ret = 0; 680 681 if (size != 4) { 682 return invalid_read(opaque, addr); 683 } 684 685 switch (MM_REGION_TYPE(addr)) { 686 case MM_ICACHE_ADDR: 687 case MM_ICACHE_DATA: 688 /* do nothing */ 689 break; 690 case MM_ITLB_ADDR: 691 ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr); 692 break; 693 case MM_ITLB_DATA: 694 ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr); 695 break; 696 case MM_OCACHE_ADDR: 697 case MM_OCACHE_DATA: 698 /* do nothing */ 699 break; 700 case MM_UTLB_ADDR: 701 ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr); 702 break; 703 case MM_UTLB_DATA: 704 ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr); 705 break; 706 default: 707 abort(); 708 } 709 710 return ret; 711 } 712 713 static void invalid_write(void *opaque, hwaddr addr, 714 uint64_t mem_value) 715 { 716 abort(); 717 } 718 719 static void sh7750_mmct_write(void *opaque, hwaddr addr, 720 uint64_t mem_value, unsigned size) 721 { 722 SH7750State *s = opaque; 723 724 if (size != 4) { 725 invalid_write(opaque, addr, mem_value); 726 } 727 728 switch (MM_REGION_TYPE(addr)) { 729 case MM_ICACHE_ADDR: 730 case MM_ICACHE_DATA: 731 /* do nothing */ 732 break; 733 case MM_ITLB_ADDR: 734 cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value); 735 break; 736 case MM_ITLB_DATA: 737 cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value); 738 abort(); 739 break; 740 case MM_OCACHE_ADDR: 741 case MM_OCACHE_DATA: 742 /* do nothing */ 743 break; 744 case MM_UTLB_ADDR: 745 cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value); 746 break; 747 case MM_UTLB_DATA: 748 cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value); 749 break; 750 default: 751 abort(); 752 break; 753 } 754 } 755 756 static const MemoryRegionOps sh7750_mmct_ops = { 757 .read = sh7750_mmct_read, 758 .write = sh7750_mmct_write, 759 .endianness = DEVICE_NATIVE_ENDIAN, 760 }; 761 762 SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) 763 { 764 SH7750State *s; 765 766 s = g_malloc0(sizeof(SH7750State)); 767 s->cpu = cpu; 768 s->periph_freq = 60000000; /* 60MHz */ 769 memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s, 770 "memory", 0x1fc01000); 771 772 memory_region_init_alias(&s->iomem_1f0, NULL, "memory-1f0", 773 &s->iomem, 0x1f000000, 0x1000); 774 memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0); 775 776 memory_region_init_alias(&s->iomem_ff0, NULL, "memory-ff0", 777 &s->iomem, 0x1f000000, 0x1000); 778 memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0); 779 780 memory_region_init_alias(&s->iomem_1f8, NULL, "memory-1f8", 781 &s->iomem, 0x1f800000, 0x1000); 782 memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8); 783 784 memory_region_init_alias(&s->iomem_ff8, NULL, "memory-ff8", 785 &s->iomem, 0x1f800000, 0x1000); 786 memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8); 787 788 memory_region_init_alias(&s->iomem_1fc, NULL, "memory-1fc", 789 &s->iomem, 0x1fc00000, 0x1000); 790 memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc); 791 792 memory_region_init_alias(&s->iomem_ffc, NULL, "memory-ffc", 793 &s->iomem, 0x1fc00000, 0x1000); 794 memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc); 795 796 memory_region_init_io(&s->mmct_iomem, NULL, &sh7750_mmct_ops, s, 797 "cache-and-tlb", 0x08000000); 798 memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem); 799 800 sh_intc_init(sysmem, &s->intc, NR_SOURCES, 801 _INTC_ARRAY(mask_registers), 802 _INTC_ARRAY(prio_registers)); 803 804 sh_intc_register_sources(&s->intc, 805 _INTC_ARRAY(vectors), 806 _INTC_ARRAY(groups)); 807 808 cpu->env.intc_handle = &s->intc; 809 810 sh_serial_init(sysmem, 0x1fe00000, 811 0, s->periph_freq, serial_hd(0), 812 s->intc.irqs[SCI1_ERI], 813 s->intc.irqs[SCI1_RXI], 814 s->intc.irqs[SCI1_TXI], 815 s->intc.irqs[SCI1_TEI], 816 NULL); 817 sh_serial_init(sysmem, 0x1fe80000, 818 SH_SERIAL_FEAT_SCIF, 819 s->periph_freq, serial_hd(1), 820 s->intc.irqs[SCIF_ERI], 821 s->intc.irqs[SCIF_RXI], 822 s->intc.irqs[SCIF_TXI], 823 NULL, 824 s->intc.irqs[SCIF_BRI]); 825 826 tmu012_init(sysmem, 0x1fd80000, 827 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, 828 s->periph_freq, 829 s->intc.irqs[TMU0], 830 s->intc.irqs[TMU1], 831 s->intc.irqs[TMU2_TUNI], 832 s->intc.irqs[TMU2_TICPI]); 833 834 if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { 835 sh_intc_register_sources(&s->intc, 836 _INTC_ARRAY(vectors_dma4), 837 _INTC_ARRAY(groups_dma4)); 838 } 839 840 if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { 841 sh_intc_register_sources(&s->intc, 842 _INTC_ARRAY(vectors_dma8), 843 _INTC_ARRAY(groups_dma8)); 844 } 845 846 if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) { 847 sh_intc_register_sources(&s->intc, 848 _INTC_ARRAY(vectors_tmu34), 849 NULL, 0); 850 tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, 851 s->intc.irqs[TMU3], 852 s->intc.irqs[TMU4], 853 NULL, NULL); 854 } 855 856 if (cpu->env.id & (SH_CPU_SH7751_ALL)) { 857 sh_intc_register_sources(&s->intc, 858 _INTC_ARRAY(vectors_pci), 859 _INTC_ARRAY(groups_pci)); 860 } 861 862 if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) { 863 sh_intc_register_sources(&s->intc, 864 _INTC_ARRAY(vectors_irlm), 865 NULL, 0); 866 } 867 868 sh_intc_register_sources(&s->intc, 869 _INTC_ARRAY(vectors_irl), 870 _INTC_ARRAY(groups_irl)); 871 return s; 872 } 873 874 qemu_irq sh7750_irl(SH7750State *s) 875 { 876 sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */ 877 return qemu_allocate_irq(sh_intc_set_irl, sh_intc_source(&s->intc, IRL), 0); 878 } 879