1 /* 2 * Raspberry Pi (BCM2835) SD Host Controller 3 * 4 * Copyright (c) 2017 Antfield SAS 5 * 6 * Authors: 7 * Clement Deschamps <clement.deschamps@antfield.fr> 8 * Luc Michel <luc.michel@antfield.fr> 9 * 10 * This work is licensed under the terms of the GNU GPL, version 2 or later. 11 * See the COPYING file in the top-level directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu/log.h" 16 #include "qemu/module.h" 17 #include "sysemu/blockdev.h" 18 #include "hw/irq.h" 19 #include "hw/sd/bcm2835_sdhost.h" 20 #include "migration/vmstate.h" 21 #include "trace.h" 22 #include "qom/object.h" 23 24 #define TYPE_BCM2835_SDHOST_BUS "bcm2835-sdhost-bus" 25 #define BCM2835_SDHOST_BUS(obj) \ 26 OBJECT_CHECK(SDBus, (obj), TYPE_BCM2835_SDHOST_BUS) 27 28 #define SDCMD 0x00 /* Command to SD card - 16 R/W */ 29 #define SDARG 0x04 /* Argument to SD card - 32 R/W */ 30 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ 31 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ 32 #define SDRSP0 0x10 /* SD card rsp (31:0) - 32 R */ 33 #define SDRSP1 0x14 /* SD card rsp (63:32) - 32 R */ 34 #define SDRSP2 0x18 /* SD card rsp (95:64) - 32 R */ 35 #define SDRSP3 0x1c /* SD card rsp (127:96) - 32 R */ 36 #define SDHSTS 0x20 /* SD host status - 11 R */ 37 #define SDVDD 0x30 /* SD card power control - 1 R/W */ 38 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ 39 #define SDHCFG 0x38 /* Host configuration - 2 R/W */ 40 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ 41 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ 42 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ 43 44 #define SDCMD_NEW_FLAG 0x8000 45 #define SDCMD_FAIL_FLAG 0x4000 46 #define SDCMD_BUSYWAIT 0x800 47 #define SDCMD_NO_RESPONSE 0x400 48 #define SDCMD_LONG_RESPONSE 0x200 49 #define SDCMD_WRITE_CMD 0x80 50 #define SDCMD_READ_CMD 0x40 51 #define SDCMD_CMD_MASK 0x3f 52 53 #define SDCDIV_MAX_CDIV 0x7ff 54 55 #define SDHSTS_BUSY_IRPT 0x400 56 #define SDHSTS_BLOCK_IRPT 0x200 57 #define SDHSTS_SDIO_IRPT 0x100 58 #define SDHSTS_REW_TIME_OUT 0x80 59 #define SDHSTS_CMD_TIME_OUT 0x40 60 #define SDHSTS_CRC16_ERROR 0x20 61 #define SDHSTS_CRC7_ERROR 0x10 62 #define SDHSTS_FIFO_ERROR 0x08 63 /* Reserved */ 64 /* Reserved */ 65 #define SDHSTS_DATA_FLAG 0x01 66 67 #define SDHCFG_BUSY_IRPT_EN (1 << 10) 68 #define SDHCFG_BLOCK_IRPT_EN (1 << 8) 69 #define SDHCFG_SDIO_IRPT_EN (1 << 5) 70 #define SDHCFG_DATA_IRPT_EN (1 << 4) 71 #define SDHCFG_SLOW_CARD (1 << 3) 72 #define SDHCFG_WIDE_EXT_BUS (1 << 2) 73 #define SDHCFG_WIDE_INT_BUS (1 << 1) 74 #define SDHCFG_REL_CMD_LINE (1 << 0) 75 76 #define SDEDM_FORCE_DATA_MODE (1 << 19) 77 #define SDEDM_CLOCK_PULSE (1 << 20) 78 #define SDEDM_BYPASS (1 << 21) 79 80 #define SDEDM_WRITE_THRESHOLD_SHIFT 9 81 #define SDEDM_READ_THRESHOLD_SHIFT 14 82 #define SDEDM_THRESHOLD_MASK 0x1f 83 84 #define SDEDM_FSM_MASK 0xf 85 #define SDEDM_FSM_IDENTMODE 0x0 86 #define SDEDM_FSM_DATAMODE 0x1 87 #define SDEDM_FSM_READDATA 0x2 88 #define SDEDM_FSM_WRITEDATA 0x3 89 #define SDEDM_FSM_READWAIT 0x4 90 #define SDEDM_FSM_READCRC 0x5 91 #define SDEDM_FSM_WRITECRC 0x6 92 #define SDEDM_FSM_WRITEWAIT1 0x7 93 #define SDEDM_FSM_POWERDOWN 0x8 94 #define SDEDM_FSM_POWERUP 0x9 95 #define SDEDM_FSM_WRITESTART1 0xa 96 #define SDEDM_FSM_WRITESTART2 0xb 97 #define SDEDM_FSM_GENPULSES 0xc 98 #define SDEDM_FSM_WRITEWAIT2 0xd 99 #define SDEDM_FSM_STARTPOWDOWN 0xf 100 101 #define SDDATA_FIFO_WORDS 16 102 103 static void bcm2835_sdhost_update_irq(BCM2835SDHostState *s) 104 { 105 uint32_t irq = s->status & 106 (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | SDHSTS_SDIO_IRPT); 107 trace_bcm2835_sdhost_update_irq(irq); 108 qemu_set_irq(s->irq, !!irq); 109 } 110 111 static void bcm2835_sdhost_send_command(BCM2835SDHostState *s) 112 { 113 SDRequest request; 114 uint8_t rsp[16]; 115 int rlen; 116 117 request.cmd = s->cmd & SDCMD_CMD_MASK; 118 request.arg = s->cmdarg; 119 120 rlen = sdbus_do_command(&s->sdbus, &request, rsp); 121 if (rlen < 0) { 122 goto error; 123 } 124 if (!(s->cmd & SDCMD_NO_RESPONSE)) { 125 if (rlen == 0 || (rlen == 4 && (s->cmd & SDCMD_LONG_RESPONSE))) { 126 goto error; 127 } 128 if (rlen != 4 && rlen != 16) { 129 goto error; 130 } 131 if (rlen == 4) { 132 s->rsp[0] = ldl_be_p(&rsp[0]); 133 s->rsp[1] = s->rsp[2] = s->rsp[3] = 0; 134 } else { 135 s->rsp[0] = ldl_be_p(&rsp[12]); 136 s->rsp[1] = ldl_be_p(&rsp[8]); 137 s->rsp[2] = ldl_be_p(&rsp[4]); 138 s->rsp[3] = ldl_be_p(&rsp[0]); 139 } 140 } 141 /* We never really delay commands, so if this was a 'busywait' command 142 * then we've completed it now and can raise the interrupt. 143 */ 144 if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) { 145 s->status |= SDHSTS_BUSY_IRPT; 146 } 147 return; 148 149 error: 150 s->cmd |= SDCMD_FAIL_FLAG; 151 s->status |= SDHSTS_CMD_TIME_OUT; 152 } 153 154 static void bcm2835_sdhost_fifo_push(BCM2835SDHostState *s, uint32_t value) 155 { 156 int n; 157 158 if (s->fifo_len == BCM2835_SDHOST_FIFO_LEN) { 159 /* FIFO overflow */ 160 return; 161 } 162 n = (s->fifo_pos + s->fifo_len) & (BCM2835_SDHOST_FIFO_LEN - 1); 163 s->fifo_len++; 164 s->fifo[n] = value; 165 } 166 167 static uint32_t bcm2835_sdhost_fifo_pop(BCM2835SDHostState *s) 168 { 169 uint32_t value; 170 171 if (s->fifo_len == 0) { 172 /* FIFO underflow */ 173 return 0; 174 } 175 value = s->fifo[s->fifo_pos]; 176 s->fifo_len--; 177 s->fifo_pos = (s->fifo_pos + 1) & (BCM2835_SDHOST_FIFO_LEN - 1); 178 return value; 179 } 180 181 static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s) 182 { 183 uint32_t value = 0; 184 int n; 185 int is_read; 186 int is_write; 187 188 is_read = (s->cmd & SDCMD_READ_CMD) != 0; 189 is_write = (s->cmd & SDCMD_WRITE_CMD) != 0; 190 if (s->datacnt != 0 && (is_write || sdbus_data_ready(&s->sdbus))) { 191 if (is_read) { 192 n = 0; 193 while (s->datacnt && s->fifo_len < BCM2835_SDHOST_FIFO_LEN) { 194 value |= (uint32_t)sdbus_read_byte(&s->sdbus) << (n * 8); 195 s->datacnt--; 196 n++; 197 if (n == 4) { 198 bcm2835_sdhost_fifo_push(s, value); 199 s->status |= SDHSTS_DATA_FLAG; 200 if (s->config & SDHCFG_DATA_IRPT_EN) { 201 s->status |= SDHSTS_SDIO_IRPT; 202 } 203 n = 0; 204 value = 0; 205 } 206 } 207 if (n != 0) { 208 bcm2835_sdhost_fifo_push(s, value); 209 s->status |= SDHSTS_DATA_FLAG; 210 if (s->config & SDHCFG_DATA_IRPT_EN) { 211 s->status |= SDHSTS_SDIO_IRPT; 212 } 213 } 214 } else if (is_write) { /* write */ 215 n = 0; 216 while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) { 217 if (n == 0) { 218 value = bcm2835_sdhost_fifo_pop(s); 219 s->status |= SDHSTS_DATA_FLAG; 220 if (s->config & SDHCFG_DATA_IRPT_EN) { 221 s->status |= SDHSTS_SDIO_IRPT; 222 } 223 n = 4; 224 } 225 n--; 226 s->datacnt--; 227 sdbus_write_byte(&s->sdbus, value & 0xff); 228 value >>= 8; 229 } 230 } 231 if (s->datacnt == 0) { 232 s->edm &= ~SDEDM_FSM_MASK; 233 s->edm |= SDEDM_FSM_DATAMODE; 234 trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm); 235 } 236 if (is_write) { 237 /* set block interrupt at end of each block transfer */ 238 if (s->hbct && s->datacnt % s->hbct == 0 && 239 (s->config & SDHCFG_BLOCK_IRPT_EN)) { 240 s->status |= SDHSTS_BLOCK_IRPT; 241 } 242 /* set data interrupt after each transfer */ 243 s->status |= SDHSTS_DATA_FLAG; 244 if (s->config & SDHCFG_DATA_IRPT_EN) { 245 s->status |= SDHSTS_SDIO_IRPT; 246 } 247 } 248 } 249 250 bcm2835_sdhost_update_irq(s); 251 252 s->edm &= ~(0x1f << 4); 253 s->edm |= ((s->fifo_len & 0x1f) << 4); 254 trace_bcm2835_sdhost_edm_change("fifo run", s->edm); 255 } 256 257 static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset, 258 unsigned size) 259 { 260 BCM2835SDHostState *s = (BCM2835SDHostState *)opaque; 261 uint32_t res = 0; 262 263 switch (offset) { 264 case SDCMD: 265 res = s->cmd; 266 break; 267 case SDHSTS: 268 res = s->status; 269 break; 270 case SDRSP0: 271 res = s->rsp[0]; 272 break; 273 case SDRSP1: 274 res = s->rsp[1]; 275 break; 276 case SDRSP2: 277 res = s->rsp[2]; 278 break; 279 case SDRSP3: 280 res = s->rsp[3]; 281 break; 282 case SDEDM: 283 res = s->edm; 284 break; 285 case SDVDD: 286 res = s->vdd; 287 break; 288 case SDDATA: 289 res = bcm2835_sdhost_fifo_pop(s); 290 bcm2835_sdhost_fifo_run(s); 291 break; 292 case SDHBCT: 293 res = s->hbct; 294 break; 295 case SDHBLC: 296 res = s->hblc; 297 break; 298 299 default: 300 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 301 __func__, offset); 302 res = 0; 303 break; 304 } 305 306 trace_bcm2835_sdhost_read(offset, res, size); 307 308 return res; 309 } 310 311 static void bcm2835_sdhost_write(void *opaque, hwaddr offset, 312 uint64_t value, unsigned size) 313 { 314 BCM2835SDHostState *s = (BCM2835SDHostState *)opaque; 315 316 trace_bcm2835_sdhost_write(offset, value, size); 317 318 switch (offset) { 319 case SDCMD: 320 s->cmd = value; 321 if (value & SDCMD_NEW_FLAG) { 322 bcm2835_sdhost_send_command(s); 323 bcm2835_sdhost_fifo_run(s); 324 s->cmd &= ~SDCMD_NEW_FLAG; 325 } 326 break; 327 case SDTOUT: 328 break; 329 case SDCDIV: 330 break; 331 case SDHSTS: 332 s->status &= ~value; 333 bcm2835_sdhost_update_irq(s); 334 break; 335 case SDARG: 336 s->cmdarg = value; 337 break; 338 case SDEDM: 339 if ((value & 0xf) == 0xf) { 340 /* power down */ 341 value &= ~0xf; 342 } 343 s->edm = value; 344 trace_bcm2835_sdhost_edm_change("guest register write", s->edm); 345 break; 346 case SDHCFG: 347 s->config = value; 348 bcm2835_sdhost_fifo_run(s); 349 break; 350 case SDVDD: 351 s->vdd = value; 352 break; 353 case SDDATA: 354 bcm2835_sdhost_fifo_push(s, value); 355 bcm2835_sdhost_fifo_run(s); 356 break; 357 case SDHBCT: 358 s->hbct = value; 359 break; 360 case SDHBLC: 361 s->hblc = value; 362 s->datacnt = s->hblc * s->hbct; 363 bcm2835_sdhost_fifo_run(s); 364 break; 365 366 default: 367 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", 368 __func__, offset); 369 break; 370 } 371 } 372 373 static const MemoryRegionOps bcm2835_sdhost_ops = { 374 .read = bcm2835_sdhost_read, 375 .write = bcm2835_sdhost_write, 376 .endianness = DEVICE_NATIVE_ENDIAN, 377 }; 378 379 static const VMStateDescription vmstate_bcm2835_sdhost = { 380 .name = TYPE_BCM2835_SDHOST, 381 .version_id = 1, 382 .minimum_version_id = 1, 383 .fields = (VMStateField[]) { 384 VMSTATE_UINT32(cmd, BCM2835SDHostState), 385 VMSTATE_UINT32(cmdarg, BCM2835SDHostState), 386 VMSTATE_UINT32(status, BCM2835SDHostState), 387 VMSTATE_UINT32_ARRAY(rsp, BCM2835SDHostState, 4), 388 VMSTATE_UINT32(config, BCM2835SDHostState), 389 VMSTATE_UINT32(edm, BCM2835SDHostState), 390 VMSTATE_UINT32(vdd, BCM2835SDHostState), 391 VMSTATE_UINT32(hbct, BCM2835SDHostState), 392 VMSTATE_UINT32(hblc, BCM2835SDHostState), 393 VMSTATE_INT32(fifo_pos, BCM2835SDHostState), 394 VMSTATE_INT32(fifo_len, BCM2835SDHostState), 395 VMSTATE_UINT32_ARRAY(fifo, BCM2835SDHostState, BCM2835_SDHOST_FIFO_LEN), 396 VMSTATE_UINT32(datacnt, BCM2835SDHostState), 397 VMSTATE_END_OF_LIST() 398 } 399 }; 400 401 static void bcm2835_sdhost_init(Object *obj) 402 { 403 BCM2835SDHostState *s = BCM2835_SDHOST(obj); 404 405 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 406 TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus"); 407 408 memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s, 409 TYPE_BCM2835_SDHOST, 0x1000); 410 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); 411 sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); 412 } 413 414 static void bcm2835_sdhost_reset(DeviceState *dev) 415 { 416 BCM2835SDHostState *s = BCM2835_SDHOST(dev); 417 418 s->cmd = 0; 419 s->cmdarg = 0; 420 s->edm = 0x0000c60f; 421 trace_bcm2835_sdhost_edm_change("device reset", s->edm); 422 s->config = 0; 423 s->hbct = 0; 424 s->hblc = 0; 425 s->datacnt = 0; 426 s->fifo_pos = 0; 427 s->fifo_len = 0; 428 } 429 430 static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data) 431 { 432 DeviceClass *dc = DEVICE_CLASS(klass); 433 434 dc->reset = bcm2835_sdhost_reset; 435 dc->vmsd = &vmstate_bcm2835_sdhost; 436 } 437 438 static TypeInfo bcm2835_sdhost_info = { 439 .name = TYPE_BCM2835_SDHOST, 440 .parent = TYPE_SYS_BUS_DEVICE, 441 .instance_size = sizeof(BCM2835SDHostState), 442 .class_init = bcm2835_sdhost_class_init, 443 .instance_init = bcm2835_sdhost_init, 444 }; 445 446 static const TypeInfo bcm2835_sdhost_bus_info = { 447 .name = TYPE_BCM2835_SDHOST_BUS, 448 .parent = TYPE_SD_BUS, 449 .instance_size = sizeof(SDBus), 450 }; 451 452 static void bcm2835_sdhost_register_types(void) 453 { 454 type_register_static(&bcm2835_sdhost_info); 455 type_register_static(&bcm2835_sdhost_bus_info); 456 } 457 458 type_init(bcm2835_sdhost_register_types) 459