1 /* 2 * Aspeed SD Host Controller 3 * Eddie James <eajames@linux.ibm.com> 4 * 5 * Copyright (C) 2019 IBM Corp 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/error-report.h" 12 #include "hw/sd/aspeed_sdhci.h" 13 #include "qapi/error.h" 14 #include "hw/irq.h" 15 #include "migration/vmstate.h" 16 #include "hw/qdev-properties.h" 17 #include "trace.h" 18 19 #define ASPEED_SDHCI_INFO 0x00 20 #define ASPEED_SDHCI_INFO_SLOT1 (1 << 17) 21 #define ASPEED_SDHCI_INFO_SLOT0 (1 << 16) 22 #define ASPEED_SDHCI_INFO_RESET (1 << 0) 23 #define ASPEED_SDHCI_DEBOUNCE 0x04 24 #define ASPEED_SDHCI_DEBOUNCE_RESET 0x00000005 25 #define ASPEED_SDHCI_BUS 0x08 26 #define ASPEED_SDHCI_SDIO_140 0x10 27 #define ASPEED_SDHCI_SDIO_144 0x14 28 #define ASPEED_SDHCI_SDIO_148 0x18 29 #define ASPEED_SDHCI_SDIO_240 0x20 30 #define ASPEED_SDHCI_SDIO_244 0x24 31 #define ASPEED_SDHCI_SDIO_248 0x28 32 #define ASPEED_SDHCI_WP_POL 0xec 33 #define ASPEED_SDHCI_CARD_DET 0xf0 34 #define ASPEED_SDHCI_IRQ_STAT 0xfc 35 36 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) 37 38 static uint64_t aspeed_sdhci_read(void *opaque, hwaddr addr, unsigned int size) 39 { 40 uint64_t val = 0; 41 AspeedSDHCIState *sdhci = opaque; 42 43 switch (addr) { 44 case ASPEED_SDHCI_SDIO_140: 45 val = extract64(sdhci->slots[0].capareg, 0, 32); 46 break; 47 case ASPEED_SDHCI_SDIO_144: 48 val = extract64(sdhci->slots[0].capareg, 32, 32); 49 break; 50 case ASPEED_SDHCI_SDIO_148: 51 val = extract64(sdhci->slots[0].maxcurr, 0, 32); 52 break; 53 case ASPEED_SDHCI_SDIO_240: 54 val = extract64(sdhci->slots[1].capareg, 0, 32); 55 break; 56 case ASPEED_SDHCI_SDIO_244: 57 val = extract64(sdhci->slots[1].capareg, 32, 32); 58 break; 59 case ASPEED_SDHCI_SDIO_248: 60 val = extract64(sdhci->slots[1].maxcurr, 0, 32); 61 break; 62 default: 63 if (addr < ASPEED_SDHCI_REG_SIZE) { 64 val = sdhci->regs[TO_REG(addr)]; 65 } else { 66 qemu_log_mask(LOG_GUEST_ERROR, 67 "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n", 68 __func__, addr); 69 } 70 } 71 72 trace_aspeed_sdhci_read(addr, size, val); 73 74 return val; 75 } 76 77 static void aspeed_sdhci_write(void *opaque, hwaddr addr, uint64_t val, 78 unsigned int size) 79 { 80 AspeedSDHCIState *sdhci = opaque; 81 82 trace_aspeed_sdhci_write(addr, size, val); 83 84 switch (addr) { 85 case ASPEED_SDHCI_INFO: 86 /* The RESET bit automatically clears. */ 87 sdhci->regs[TO_REG(addr)] = (uint32_t)val & ~ASPEED_SDHCI_INFO_RESET; 88 break; 89 case ASPEED_SDHCI_SDIO_140: 90 sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 91 0, 32, val); 92 break; 93 case ASPEED_SDHCI_SDIO_144: 94 sdhci->slots[0].capareg = deposit64(sdhci->slots[0].capareg, 95 32, 32, val); 96 break; 97 case ASPEED_SDHCI_SDIO_148: 98 sdhci->slots[0].maxcurr = deposit64(sdhci->slots[0].maxcurr, 99 0, 32, val); 100 break; 101 case ASPEED_SDHCI_SDIO_240: 102 sdhci->slots[1].capareg = deposit64(sdhci->slots[1].capareg, 103 0, 32, val); 104 break; 105 case ASPEED_SDHCI_SDIO_244: 106 sdhci->slots[1].capareg = deposit64(sdhci->slots[1].capareg, 107 32, 32, val); 108 break; 109 case ASPEED_SDHCI_SDIO_248: 110 sdhci->slots[1].maxcurr = deposit64(sdhci->slots[0].maxcurr, 111 0, 32, val); 112 break; 113 default: 114 if (addr < ASPEED_SDHCI_REG_SIZE) { 115 sdhci->regs[TO_REG(addr)] = (uint32_t)val; 116 } else { 117 qemu_log_mask(LOG_GUEST_ERROR, 118 "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n", 119 __func__, addr); 120 } 121 } 122 } 123 124 static const MemoryRegionOps aspeed_sdhci_ops = { 125 .read = aspeed_sdhci_read, 126 .write = aspeed_sdhci_write, 127 .endianness = DEVICE_NATIVE_ENDIAN, 128 .valid.min_access_size = 1, 129 .valid.max_access_size = 4, 130 }; 131 132 static void aspeed_sdhci_set_irq(void *opaque, int n, int level) 133 { 134 AspeedSDHCIState *sdhci = opaque; 135 136 if (level) { 137 sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] |= BIT(n); 138 139 qemu_irq_raise(sdhci->irq); 140 } else { 141 sdhci->regs[TO_REG(ASPEED_SDHCI_IRQ_STAT)] &= ~BIT(n); 142 143 qemu_irq_lower(sdhci->irq); 144 } 145 } 146 147 static void aspeed_sdhci_realize(DeviceState *dev, Error **errp) 148 { 149 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 150 AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev); 151 AspeedSDHCIClass *asc = ASPEED_SDHCI_GET_CLASS(sdhci); 152 153 /* Create input irqs for the slots */ 154 qdev_init_gpio_in_named_with_opaque(DEVICE(sbd), aspeed_sdhci_set_irq, 155 sdhci, NULL, sdhci->num_slots); 156 157 sysbus_init_irq(sbd, &sdhci->irq); 158 memory_region_init_io(&sdhci->iomem, OBJECT(sdhci), &aspeed_sdhci_ops, 159 sdhci, TYPE_ASPEED_SDHCI, 0x1000); 160 sysbus_init_mmio(sbd, &sdhci->iomem); 161 162 for (int i = 0; i < sdhci->num_slots; ++i) { 163 Object *sdhci_slot = OBJECT(&sdhci->slots[i]); 164 SysBusDevice *sbd_slot = SYS_BUS_DEVICE(&sdhci->slots[i]); 165 166 if (!object_property_set_int(sdhci_slot, "sd-spec-version", 2, errp)) { 167 return; 168 } 169 170 if (!object_property_set_uint(sdhci_slot, "capareg", 171 asc->capareg, errp)) { 172 return; 173 } 174 175 if (!sysbus_realize(sbd_slot, errp)) { 176 return; 177 } 178 179 sysbus_connect_irq(sbd_slot, 0, qdev_get_gpio_in(DEVICE(sbd), i)); 180 memory_region_add_subregion(&sdhci->iomem, (i + 1) * 0x100, 181 &sdhci->slots[i].iomem); 182 } 183 } 184 185 static void aspeed_sdhci_reset(DeviceState *dev) 186 { 187 AspeedSDHCIState *sdhci = ASPEED_SDHCI(dev); 188 189 memset(sdhci->regs, 0, ASPEED_SDHCI_REG_SIZE); 190 191 sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] = ASPEED_SDHCI_INFO_SLOT0; 192 if (sdhci->num_slots == 2) { 193 sdhci->regs[TO_REG(ASPEED_SDHCI_INFO)] |= ASPEED_SDHCI_INFO_SLOT1; 194 } 195 sdhci->regs[TO_REG(ASPEED_SDHCI_DEBOUNCE)] = ASPEED_SDHCI_DEBOUNCE_RESET; 196 } 197 198 static const VMStateDescription vmstate_aspeed_sdhci = { 199 .name = TYPE_ASPEED_SDHCI, 200 .version_id = 1, 201 .fields = (const VMStateField[]) { 202 VMSTATE_UINT32_ARRAY(regs, AspeedSDHCIState, ASPEED_SDHCI_NUM_REGS), 203 VMSTATE_END_OF_LIST(), 204 }, 205 }; 206 207 static Property aspeed_sdhci_properties[] = { 208 DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), 209 DEFINE_PROP_END_OF_LIST(), 210 }; 211 212 static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) 213 { 214 DeviceClass *dc = DEVICE_CLASS(classp); 215 216 dc->realize = aspeed_sdhci_realize; 217 device_class_set_legacy_reset(dc, aspeed_sdhci_reset); 218 dc->vmsd = &vmstate_aspeed_sdhci; 219 device_class_set_props(dc, aspeed_sdhci_properties); 220 } 221 222 static void aspeed_2400_sdhci_class_init(ObjectClass *klass, void *data) 223 { 224 DeviceClass *dc = DEVICE_CLASS(klass); 225 AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass); 226 227 dc->desc = "ASPEED 2400 SDHCI Controller"; 228 asc->capareg = 0x0000000001e80080; 229 } 230 231 static void aspeed_2500_sdhci_class_init(ObjectClass *klass, void *data) 232 { 233 DeviceClass *dc = DEVICE_CLASS(klass); 234 AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass); 235 236 dc->desc = "ASPEED 2500 SDHCI Controller"; 237 asc->capareg = 0x0000000001e80080; 238 } 239 240 static void aspeed_2600_sdhci_class_init(ObjectClass *klass, void *data) 241 { 242 DeviceClass *dc = DEVICE_CLASS(klass); 243 AspeedSDHCIClass *asc = ASPEED_SDHCI_CLASS(klass); 244 245 dc->desc = "ASPEED 2600 SDHCI Controller"; 246 asc->capareg = 0x0000000701f80080; 247 } 248 249 static const TypeInfo aspeed_sdhci_types[] = { 250 { 251 .name = TYPE_ASPEED_SDHCI, 252 .parent = TYPE_SYS_BUS_DEVICE, 253 .instance_size = sizeof(AspeedSDHCIState), 254 .class_init = aspeed_sdhci_class_init, 255 .class_size = sizeof(AspeedSDHCIClass), 256 .abstract = true, 257 }, 258 { 259 .name = TYPE_ASPEED_2400_SDHCI, 260 .parent = TYPE_ASPEED_SDHCI, 261 .class_init = aspeed_2400_sdhci_class_init, 262 }, 263 { 264 .name = TYPE_ASPEED_2500_SDHCI, 265 .parent = TYPE_ASPEED_SDHCI, 266 .class_init = aspeed_2500_sdhci_class_init, 267 }, 268 { 269 .name = TYPE_ASPEED_2600_SDHCI, 270 .parent = TYPE_ASPEED_SDHCI, 271 .class_init = aspeed_2600_sdhci_class_init, 272 }, 273 }; 274 275 DEFINE_TYPES(aspeed_sdhci_types) 276