1e351b826SPaolo Bonzini #ifndef MPTSAS_H 2e351b826SPaolo Bonzini #define MPTSAS_H 3e351b826SPaolo Bonzini 4e351b826SPaolo Bonzini #include "mpi.h" 5*edf5ca5dSMarkus Armbruster #include "hw/pci/pci_device.h" 6e351b826SPaolo Bonzini 7e351b826SPaolo Bonzini #define MPTSAS_NUM_PORTS 8 8e351b826SPaolo Bonzini #define MPTSAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ 9e351b826SPaolo Bonzini 10e351b826SPaolo Bonzini #define MPTSAS_REQUEST_QUEUE_DEPTH 128 11e351b826SPaolo Bonzini #define MPTSAS_REPLY_QUEUE_DEPTH 128 12e351b826SPaolo Bonzini 13e351b826SPaolo Bonzini #define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22 14e351b826SPaolo Bonzini 15e351b826SPaolo Bonzini typedef struct MPTSASRequest MPTSASRequest; 16e351b826SPaolo Bonzini 17040c1fd3SEduardo Habkost #define TYPE_MPTSAS1068 "mptsas1068" 18040c1fd3SEduardo Habkost typedef struct MPTSASState MPTSASState; 198110fa1dSEduardo Habkost DECLARE_INSTANCE_CHECKER(MPTSASState, MPT_SAS, 208110fa1dSEduardo Habkost TYPE_MPTSAS1068) 21040c1fd3SEduardo Habkost 22e351b826SPaolo Bonzini enum { 23e351b826SPaolo Bonzini DOORBELL_NONE, 24e351b826SPaolo Bonzini DOORBELL_WRITE, 25e351b826SPaolo Bonzini DOORBELL_READ 26e351b826SPaolo Bonzini }; 27e351b826SPaolo Bonzini 28e351b826SPaolo Bonzini struct MPTSASState { 29e351b826SPaolo Bonzini PCIDevice dev; 30e351b826SPaolo Bonzini MemoryRegion mmio_io; 31e351b826SPaolo Bonzini MemoryRegion port_io; 32e351b826SPaolo Bonzini MemoryRegion diag_io; 33e351b826SPaolo Bonzini QEMUBH *request_bh; 34e351b826SPaolo Bonzini 35444dd1afSCao jin /* properties */ 36444dd1afSCao jin OnOffAuto msi; 37e351b826SPaolo Bonzini uint64_t sas_addr; 38e351b826SPaolo Bonzini 390b646f44SPaolo Bonzini bool msi_in_use; 400b646f44SPaolo Bonzini 41e351b826SPaolo Bonzini /* Doorbell register */ 42e351b826SPaolo Bonzini uint32_t state; 43e351b826SPaolo Bonzini uint8_t who_init; 44e351b826SPaolo Bonzini uint8_t doorbell_state; 45e351b826SPaolo Bonzini 46e351b826SPaolo Bonzini /* Buffer for requests that are sent through the doorbell register. */ 47e351b826SPaolo Bonzini uint32_t doorbell_msg[256]; 48e351b826SPaolo Bonzini int doorbell_idx; 49e351b826SPaolo Bonzini int doorbell_cnt; 50e351b826SPaolo Bonzini 51e351b826SPaolo Bonzini uint16_t doorbell_reply[256]; 52e351b826SPaolo Bonzini int doorbell_reply_idx; 53e351b826SPaolo Bonzini int doorbell_reply_size; 54e351b826SPaolo Bonzini 55e351b826SPaolo Bonzini /* Other registers */ 56e351b826SPaolo Bonzini uint8_t diagnostic_idx; 57e351b826SPaolo Bonzini uint32_t diagnostic; 58e351b826SPaolo Bonzini uint32_t intr_mask; 59e351b826SPaolo Bonzini uint32_t intr_status; 60e351b826SPaolo Bonzini 61e351b826SPaolo Bonzini /* Request queues */ 62e351b826SPaolo Bonzini uint32_t request_post[MPTSAS_REQUEST_QUEUE_DEPTH + 1]; 63e351b826SPaolo Bonzini uint16_t request_post_head; 64e351b826SPaolo Bonzini uint16_t request_post_tail; 65e351b826SPaolo Bonzini 66e351b826SPaolo Bonzini uint32_t reply_post[MPTSAS_REPLY_QUEUE_DEPTH + 1]; 67e351b826SPaolo Bonzini uint16_t reply_post_head; 68e351b826SPaolo Bonzini uint16_t reply_post_tail; 69e351b826SPaolo Bonzini 70e351b826SPaolo Bonzini uint32_t reply_free[MPTSAS_REPLY_QUEUE_DEPTH + 1]; 71e351b826SPaolo Bonzini uint16_t reply_free_head; 72e351b826SPaolo Bonzini uint16_t reply_free_tail; 73e351b826SPaolo Bonzini 74e351b826SPaolo Bonzini /* IOC Facts */ 75e351b826SPaolo Bonzini hwaddr host_mfa_high_addr; 76e351b826SPaolo Bonzini hwaddr sense_buffer_high_addr; 77e351b826SPaolo Bonzini uint16_t max_devices; 78e351b826SPaolo Bonzini uint16_t max_buses; 79e351b826SPaolo Bonzini uint16_t reply_frame_size; 80e351b826SPaolo Bonzini 81e351b826SPaolo Bonzini SCSIBus bus; 82e351b826SPaolo Bonzini }; 83e351b826SPaolo Bonzini 84e351b826SPaolo Bonzini void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req); 85e351b826SPaolo Bonzini void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply); 86e351b826SPaolo Bonzini void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req); 87e351b826SPaolo Bonzini void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply); 88e351b826SPaolo Bonzini void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req); 89e351b826SPaolo Bonzini void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply); 90e351b826SPaolo Bonzini void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req); 91e351b826SPaolo Bonzini void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply); 92e351b826SPaolo Bonzini void mptsas_fix_config_endianness(MPIMsgConfig *req); 93e351b826SPaolo Bonzini void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply); 94e351b826SPaolo Bonzini void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req); 95e351b826SPaolo Bonzini void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply); 96e351b826SPaolo Bonzini void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req); 97e351b826SPaolo Bonzini void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply); 98e351b826SPaolo Bonzini void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req); 99e351b826SPaolo Bonzini void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply); 100e351b826SPaolo Bonzini 101e351b826SPaolo Bonzini void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply); 102e351b826SPaolo Bonzini 103e351b826SPaolo Bonzini void mptsas_process_config(MPTSASState *s, MPIMsgConfig *req); 104e351b826SPaolo Bonzini 105e351b826SPaolo Bonzini #endif /* MPTSAS_H */ 106