1 /* 2 * s390 PCI instructions 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu-common.h" 16 #include "cpu.h" 17 #include "s390-pci-inst.h" 18 #include "s390-pci-bus.h" 19 #include "exec/memory-internal.h" 20 #include "qemu/error-report.h" 21 #include "sysemu/hw_accel.h" 22 23 #ifndef DEBUG_S390PCI_INST 24 #define DEBUG_S390PCI_INST 0 25 #endif 26 27 #define DPRINTF(fmt, ...) \ 28 do { \ 29 if (DEBUG_S390PCI_INST) { \ 30 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \ 31 } \ 32 } while (0) 33 34 static void s390_set_status_code(CPUS390XState *env, 35 uint8_t r, uint64_t status_code) 36 { 37 env->regs[r] &= ~0xff000000ULL; 38 env->regs[r] |= (status_code & 0xff) << 24; 39 } 40 41 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) 42 { 43 S390PCIBusDevice *pbdev = NULL; 44 S390pciState *s = s390_get_phb(); 45 uint32_t res_code, initial_l2, g_l2; 46 int rc, i; 47 uint64_t resume_token; 48 49 rc = 0; 50 if (lduw_p(&rrb->request.hdr.len) != 32) { 51 res_code = CLP_RC_LEN; 52 rc = -EINVAL; 53 goto out; 54 } 55 56 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { 57 res_code = CLP_RC_FMT; 58 rc = -EINVAL; 59 goto out; 60 } 61 62 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || 63 ldq_p(&rrb->request.reserved1) != 0) { 64 res_code = CLP_RC_RESNOT0; 65 rc = -EINVAL; 66 goto out; 67 } 68 69 resume_token = ldq_p(&rrb->request.resume_token); 70 71 if (resume_token) { 72 pbdev = s390_pci_find_dev_by_idx(s, resume_token); 73 if (!pbdev) { 74 res_code = CLP_RC_LISTPCI_BADRT; 75 rc = -EINVAL; 76 goto out; 77 } 78 } else { 79 pbdev = s390_pci_find_next_avail_dev(s, NULL); 80 } 81 82 if (lduw_p(&rrb->response.hdr.len) < 48) { 83 res_code = CLP_RC_8K; 84 rc = -EINVAL; 85 goto out; 86 } 87 88 initial_l2 = lduw_p(&rrb->response.hdr.len); 89 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry) 90 != 0) { 91 res_code = CLP_RC_LEN; 92 rc = -EINVAL; 93 *cc = 3; 94 goto out; 95 } 96 97 stl_p(&rrb->response.fmt, 0); 98 stq_p(&rrb->response.reserved1, 0); 99 stl_p(&rrb->response.mdd, FH_MASK_SHM); 100 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); 101 rrb->response.flags = UID_CHECKING_ENABLED; 102 rrb->response.entry_size = sizeof(ClpFhListEntry); 103 104 i = 0; 105 g_l2 = LIST_PCI_HDR_LEN; 106 while (g_l2 < initial_l2 && pbdev) { 107 stw_p(&rrb->response.fh_list[i].device_id, 108 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID)); 109 stw_p(&rrb->response.fh_list[i].vendor_id, 110 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID)); 111 /* Ignore RESERVED devices. */ 112 stl_p(&rrb->response.fh_list[i].config, 113 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31); 114 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid); 115 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh); 116 117 g_l2 += sizeof(ClpFhListEntry); 118 /* Add endian check for DPRINTF? */ 119 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n", 120 g_l2, 121 lduw_p(&rrb->response.fh_list[i].vendor_id), 122 lduw_p(&rrb->response.fh_list[i].device_id), 123 ldl_p(&rrb->response.fh_list[i].fid), 124 ldl_p(&rrb->response.fh_list[i].fh)); 125 pbdev = s390_pci_find_next_avail_dev(s, pbdev); 126 i++; 127 } 128 129 if (!pbdev) { 130 resume_token = 0; 131 } else { 132 resume_token = pbdev->fh & FH_MASK_INDEX; 133 } 134 stq_p(&rrb->response.resume_token, resume_token); 135 stw_p(&rrb->response.hdr.len, g_l2); 136 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK); 137 out: 138 if (rc) { 139 DPRINTF("list pci failed rc 0x%x\n", rc); 140 stw_p(&rrb->response.hdr.rsp, res_code); 141 } 142 return rc; 143 } 144 145 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) 146 { 147 ClpReqHdr *reqh; 148 ClpRspHdr *resh; 149 S390PCIBusDevice *pbdev; 150 uint32_t req_len; 151 uint32_t res_len; 152 uint8_t buffer[4096 * 2]; 153 uint8_t cc = 0; 154 CPUS390XState *env = &cpu->env; 155 S390pciState *s = s390_get_phb(); 156 int i; 157 158 cpu_synchronize_state(CPU(cpu)); 159 160 if (env->psw.mask & PSW_MASK_PSTATE) { 161 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 162 return 0; 163 } 164 165 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) { 166 s390_cpu_virt_mem_handle_exc(cpu, ra); 167 return 0; 168 } 169 reqh = (ClpReqHdr *)buffer; 170 req_len = lduw_p(&reqh->len); 171 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) { 172 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 173 return 0; 174 } 175 176 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 177 req_len + sizeof(*resh))) { 178 s390_cpu_virt_mem_handle_exc(cpu, ra); 179 return 0; 180 } 181 resh = (ClpRspHdr *)(buffer + req_len); 182 res_len = lduw_p(&resh->len); 183 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) { 184 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 185 return 0; 186 } 187 if ((req_len + res_len) > 8192) { 188 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 189 return 0; 190 } 191 192 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 193 req_len + res_len)) { 194 s390_cpu_virt_mem_handle_exc(cpu, ra); 195 return 0; 196 } 197 198 if (req_len != 32) { 199 stw_p(&resh->rsp, CLP_RC_LEN); 200 goto out; 201 } 202 203 switch (lduw_p(&reqh->cmd)) { 204 case CLP_LIST_PCI: { 205 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer; 206 list_pci(rrb, &cc); 207 break; 208 } 209 case CLP_SET_PCI_FN: { 210 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh; 211 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh; 212 213 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh)); 214 if (!pbdev) { 215 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); 216 goto out; 217 } 218 219 switch (reqsetpci->oc) { 220 case CLP_SET_ENABLE_PCI_FN: 221 switch (reqsetpci->ndas) { 222 case 0: 223 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); 224 goto out; 225 case 1: 226 break; 227 default: 228 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); 229 goto out; 230 } 231 232 if (pbdev->fh & FH_MASK_ENABLE) { 233 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 234 goto out; 235 } 236 237 pbdev->fh |= FH_MASK_ENABLE; 238 pbdev->state = ZPCI_FS_ENABLED; 239 stl_p(&ressetpci->fh, pbdev->fh); 240 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 241 break; 242 case CLP_SET_DISABLE_PCI_FN: 243 if (!(pbdev->fh & FH_MASK_ENABLE)) { 244 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 245 goto out; 246 } 247 device_reset(DEVICE(pbdev)); 248 pbdev->fh &= ~FH_MASK_ENABLE; 249 pbdev->state = ZPCI_FS_DISABLED; 250 stl_p(&ressetpci->fh, pbdev->fh); 251 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 252 break; 253 default: 254 DPRINTF("unknown set pci command\n"); 255 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 256 break; 257 } 258 break; 259 } 260 case CLP_QUERY_PCI_FN: { 261 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh; 262 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh; 263 264 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh)); 265 if (!pbdev) { 266 DPRINTF("query pci no pci dev\n"); 267 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); 268 goto out; 269 } 270 271 for (i = 0; i < PCI_BAR_COUNT; i++) { 272 uint32_t data = pci_get_long(pbdev->pdev->config + 273 PCI_BASE_ADDRESS_0 + (i * 4)); 274 275 stl_p(&resquery->bar[i], data); 276 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ? 277 ctz64(pbdev->pdev->io_regions[i].size) : 0; 278 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i, 279 ldl_p(&resquery->bar[i]), 280 pbdev->pdev->io_regions[i].size, 281 resquery->bar_size[i]); 282 } 283 284 stq_p(&resquery->sdma, ZPCI_SDMA_ADDR); 285 stq_p(&resquery->edma, ZPCI_EDMA_ADDR); 286 stl_p(&resquery->fid, pbdev->fid); 287 stw_p(&resquery->pchid, 0); 288 stw_p(&resquery->ug, 1); 289 stl_p(&resquery->uid, pbdev->uid); 290 stw_p(&resquery->hdr.rsp, CLP_RC_OK); 291 break; 292 } 293 case CLP_QUERY_PCI_FNGRP: { 294 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh; 295 resgrp->fr = 1; 296 stq_p(&resgrp->dasm, 0); 297 stq_p(&resgrp->msia, ZPCI_MSI_ADDR); 298 stw_p(&resgrp->mui, 0); 299 stw_p(&resgrp->i, 128); 300 stw_p(&resgrp->maxstbl, 128); 301 resgrp->version = 0; 302 303 stw_p(&resgrp->hdr.rsp, CLP_RC_OK); 304 break; 305 } 306 default: 307 DPRINTF("unknown clp command\n"); 308 stw_p(&resh->rsp, CLP_RC_CMD); 309 break; 310 } 311 312 out: 313 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer, 314 req_len + res_len)) { 315 s390_cpu_virt_mem_handle_exc(cpu, ra); 316 return 0; 317 } 318 setcc(cpu, cc); 319 return 0; 320 } 321 322 /** 323 * Swap data contained in s390x big endian registers to little endian 324 * PCI bars. 325 * 326 * @ptr: a pointer to a uint64_t data field 327 * @len: the length of the valid data, must be 1,2,4 or 8 328 */ 329 static int zpci_endian_swap(uint64_t *ptr, uint8_t len) 330 { 331 uint64_t data = *ptr; 332 333 switch (len) { 334 case 1: 335 break; 336 case 2: 337 data = bswap16(data); 338 break; 339 case 4: 340 data = bswap32(data); 341 break; 342 case 8: 343 data = bswap64(data); 344 break; 345 default: 346 return -EINVAL; 347 } 348 *ptr = data; 349 return 0; 350 } 351 352 static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 353 uint64_t offset, uint64_t *data, uint8_t len) 354 { 355 MemoryRegion *mr; 356 357 mr = pbdev->pdev->io_regions[pcias].memory; 358 return memory_region_dispatch_read(mr, offset, data, len, 359 MEMTXATTRS_UNSPECIFIED); 360 } 361 362 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 363 { 364 CPUS390XState *env = &cpu->env; 365 S390PCIBusDevice *pbdev; 366 uint64_t offset; 367 uint64_t data; 368 MemTxResult result; 369 uint8_t len; 370 uint32_t fh; 371 uint8_t pcias; 372 373 cpu_synchronize_state(CPU(cpu)); 374 375 if (env->psw.mask & PSW_MASK_PSTATE) { 376 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 377 return 0; 378 } 379 380 if (r2 & 0x1) { 381 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 382 return 0; 383 } 384 385 fh = env->regs[r2] >> 32; 386 pcias = (env->regs[r2] >> 16) & 0xf; 387 len = env->regs[r2] & 0xf; 388 offset = env->regs[r2 + 1]; 389 390 if (!(fh & FH_MASK_ENABLE)) { 391 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 392 return 0; 393 } 394 395 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 396 if (!pbdev) { 397 DPRINTF("pcilg no pci dev\n"); 398 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 399 return 0; 400 } 401 402 switch (pbdev->state) { 403 case ZPCI_FS_PERMANENT_ERROR: 404 case ZPCI_FS_ERROR: 405 setcc(cpu, ZPCI_PCI_LS_ERR); 406 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 407 return 0; 408 default: 409 break; 410 } 411 412 switch (pcias) { 413 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 414 if (!len || (len > (8 - (offset & 0x7)))) { 415 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 416 return 0; 417 } 418 result = zpci_read_bar(pbdev, pcias, offset, &data, len); 419 if (result != MEMTX_OK) { 420 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 421 return 0; 422 } 423 break; 424 case ZPCI_CONFIG_BAR: 425 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 426 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 427 return 0; 428 } 429 data = pci_host_config_read_common( 430 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len); 431 432 if (zpci_endian_swap(&data, len)) { 433 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 434 return 0; 435 } 436 break; 437 default: 438 DPRINTF("pcilg invalid space\n"); 439 setcc(cpu, ZPCI_PCI_LS_ERR); 440 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 441 return 0; 442 } 443 444 env->regs[r1] = data; 445 setcc(cpu, ZPCI_PCI_LS_OK); 446 return 0; 447 } 448 449 static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias) 450 { 451 if (pbdev->msix.available && pbdev->msix.table_bar == pcias && 452 offset >= pbdev->msix.table_offset && 453 offset < (pbdev->msix.table_offset + 454 pbdev->msix.entries * PCI_MSIX_ENTRY_SIZE)) { 455 return 1; 456 } else { 457 return 0; 458 } 459 } 460 461 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 462 { 463 CPUS390XState *env = &cpu->env; 464 uint64_t offset, data; 465 S390PCIBusDevice *pbdev; 466 MemoryRegion *mr; 467 MemTxResult result; 468 uint8_t len; 469 uint32_t fh; 470 uint8_t pcias; 471 472 cpu_synchronize_state(CPU(cpu)); 473 474 if (env->psw.mask & PSW_MASK_PSTATE) { 475 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 476 return 0; 477 } 478 479 if (r2 & 0x1) { 480 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 481 return 0; 482 } 483 484 fh = env->regs[r2] >> 32; 485 pcias = (env->regs[r2] >> 16) & 0xf; 486 len = env->regs[r2] & 0xf; 487 offset = env->regs[r2 + 1]; 488 data = env->regs[r1]; 489 490 if (!(fh & FH_MASK_ENABLE)) { 491 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 492 return 0; 493 } 494 495 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 496 if (!pbdev) { 497 DPRINTF("pcistg no pci dev\n"); 498 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 499 return 0; 500 } 501 502 switch (pbdev->state) { 503 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED 504 * are already covered by the FH_MASK_ENABLE check above 505 */ 506 case ZPCI_FS_PERMANENT_ERROR: 507 case ZPCI_FS_ERROR: 508 setcc(cpu, ZPCI_PCI_LS_ERR); 509 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 510 return 0; 511 default: 512 break; 513 } 514 515 switch (pcias) { 516 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */ 517 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 518 /* Check length: 519 * A length of 0 is invalid and length should not cross a double word 520 */ 521 if (!len || (len > (8 - (offset & 0x7)))) { 522 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 523 return 0; 524 } 525 526 if (trap_msix(pbdev, offset, pcias)) { 527 offset = offset - pbdev->msix.table_offset; 528 mr = &pbdev->pdev->msix_table_mmio; 529 } else { 530 mr = pbdev->pdev->io_regions[pcias].memory; 531 } 532 533 result = memory_region_dispatch_write(mr, offset, data, len, 534 MEMTXATTRS_UNSPECIFIED); 535 if (result != MEMTX_OK) { 536 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 537 return 0; 538 } 539 break; 540 case ZPCI_CONFIG_BAR: 541 /* ZPCI uses the pseudo BAR number 15 as configuration space */ 542 /* possible access lengths are 1,2,4 and must not cross a word */ 543 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 544 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 545 return 0; 546 } 547 /* len = 1,2,4 so we do not need to test */ 548 zpci_endian_swap(&data, len); 549 pci_host_config_write_common(pbdev->pdev, offset, 550 pci_config_size(pbdev->pdev), 551 data, len); 552 break; 553 default: 554 DPRINTF("pcistg invalid space\n"); 555 setcc(cpu, ZPCI_PCI_LS_ERR); 556 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 557 return 0; 558 } 559 560 setcc(cpu, ZPCI_PCI_LS_OK); 561 return 0; 562 } 563 564 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 565 { 566 CPUS390XState *env = &cpu->env; 567 uint32_t fh; 568 S390PCIBusDevice *pbdev; 569 S390PCIIOMMU *iommu; 570 hwaddr start, end; 571 IOMMUTLBEntry entry; 572 IOMMUMemoryRegion *iommu_mr; 573 IOMMUMemoryRegionClass *imrc; 574 575 cpu_synchronize_state(CPU(cpu)); 576 577 if (env->psw.mask & PSW_MASK_PSTATE) { 578 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 579 goto out; 580 } 581 582 if (r2 & 0x1) { 583 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 584 goto out; 585 } 586 587 fh = env->regs[r1] >> 32; 588 start = env->regs[r2]; 589 end = start + env->regs[r2 + 1]; 590 591 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 592 if (!pbdev) { 593 DPRINTF("rpcit no pci dev\n"); 594 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 595 goto out; 596 } 597 598 switch (pbdev->state) { 599 case ZPCI_FS_RESERVED: 600 case ZPCI_FS_STANDBY: 601 case ZPCI_FS_DISABLED: 602 case ZPCI_FS_PERMANENT_ERROR: 603 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 604 return 0; 605 case ZPCI_FS_ERROR: 606 setcc(cpu, ZPCI_PCI_LS_ERR); 607 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER); 608 return 0; 609 default: 610 break; 611 } 612 613 iommu = pbdev->iommu; 614 if (!iommu->g_iota) { 615 pbdev->state = ZPCI_FS_ERROR; 616 setcc(cpu, ZPCI_PCI_LS_ERR); 617 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 618 s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid, 619 start, 0); 620 goto out; 621 } 622 623 if (end < iommu->pba || start > iommu->pal) { 624 pbdev->state = ZPCI_FS_ERROR; 625 setcc(cpu, ZPCI_PCI_LS_ERR); 626 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 627 s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid, 628 start, 0); 629 goto out; 630 } 631 632 iommu_mr = &iommu->iommu_mr; 633 imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); 634 635 while (start < end) { 636 entry = imrc->translate(iommu_mr, start, IOMMU_NONE); 637 638 if (!entry.translated_addr) { 639 pbdev->state = ZPCI_FS_ERROR; 640 setcc(cpu, ZPCI_PCI_LS_ERR); 641 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 642 s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid, 643 start, ERR_EVENT_Q_BIT); 644 goto out; 645 } 646 647 memory_region_notify_iommu(iommu_mr, entry); 648 start += entry.addr_mask + 1; 649 } 650 651 setcc(cpu, ZPCI_PCI_LS_OK); 652 out: 653 return 0; 654 } 655 656 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, 657 uint8_t ar, uintptr_t ra) 658 { 659 CPUS390XState *env = &cpu->env; 660 S390PCIBusDevice *pbdev; 661 MemoryRegion *mr; 662 MemTxResult result; 663 uint64_t offset; 664 int i; 665 uint32_t fh; 666 uint8_t pcias; 667 uint8_t len; 668 uint8_t buffer[128]; 669 670 if (env->psw.mask & PSW_MASK_PSTATE) { 671 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 672 return 0; 673 } 674 675 fh = env->regs[r1] >> 32; 676 pcias = (env->regs[r1] >> 16) & 0xf; 677 len = env->regs[r1] & 0xff; 678 offset = env->regs[r3]; 679 680 if (!(fh & FH_MASK_ENABLE)) { 681 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 682 return 0; 683 } 684 685 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 686 if (!pbdev) { 687 DPRINTF("pcistb no pci dev fh 0x%x\n", fh); 688 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 689 return 0; 690 } 691 692 switch (pbdev->state) { 693 case ZPCI_FS_PERMANENT_ERROR: 694 case ZPCI_FS_ERROR: 695 setcc(cpu, ZPCI_PCI_LS_ERR); 696 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED); 697 return 0; 698 default: 699 break; 700 } 701 702 if (pcias > ZPCI_IO_BAR_MAX) { 703 DPRINTF("pcistb invalid space\n"); 704 setcc(cpu, ZPCI_PCI_LS_ERR); 705 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS); 706 return 0; 707 } 708 709 /* Verify the address, offset and length */ 710 /* offset must be a multiple of 8 */ 711 if (offset % 8) { 712 goto specification_error; 713 } 714 /* Length must be greater than 8, a multiple of 8 */ 715 /* and not greater than maxstbl */ 716 if ((len <= 8) || (len % 8) || (len > pbdev->maxstbl)) { 717 goto specification_error; 718 } 719 /* Do not cross a 4K-byte boundary */ 720 if (((offset & 0xfff) + len) > 0x1000) { 721 goto specification_error; 722 } 723 /* Guest address must be double word aligned */ 724 if (gaddr & 0x07UL) { 725 goto specification_error; 726 } 727 728 mr = pbdev->pdev->io_regions[pcias].memory; 729 if (!memory_region_access_valid(mr, offset, len, true)) { 730 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 731 return 0; 732 } 733 734 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) { 735 s390_cpu_virt_mem_handle_exc(cpu, ra); 736 return 0; 737 } 738 739 for (i = 0; i < len / 8; i++) { 740 result = memory_region_dispatch_write(mr, offset + i * 8, 741 ldq_p(buffer + i * 8), 8, 742 MEMTXATTRS_UNSPECIFIED); 743 if (result != MEMTX_OK) { 744 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 745 return 0; 746 } 747 } 748 749 setcc(cpu, ZPCI_PCI_LS_OK); 750 return 0; 751 752 specification_error: 753 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 754 return 0; 755 } 756 757 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) 758 { 759 int ret, len; 760 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data)); 761 762 pbdev->routes.adapter.adapter_id = css_get_adapter_id( 763 CSS_IO_ADAPTER_PCI, isc); 764 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t)); 765 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long); 766 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len); 767 768 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 769 if (ret) { 770 goto out; 771 } 772 773 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator); 774 if (ret) { 775 goto out; 776 } 777 778 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb); 779 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data)); 780 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv); 781 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data)); 782 pbdev->isc = isc; 783 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data)); 784 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data)); 785 786 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 787 return 0; 788 out: 789 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 790 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 791 pbdev->summary_ind = NULL; 792 pbdev->indicator = NULL; 793 return ret; 794 } 795 796 int pci_dereg_irqs(S390PCIBusDevice *pbdev) 797 { 798 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 799 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 800 801 pbdev->summary_ind = NULL; 802 pbdev->indicator = NULL; 803 pbdev->routes.adapter.summary_addr = 0; 804 pbdev->routes.adapter.summary_offset = 0; 805 pbdev->routes.adapter.ind_addr = 0; 806 pbdev->routes.adapter.ind_offset = 0; 807 pbdev->isc = 0; 808 pbdev->noi = 0; 809 pbdev->sum = 0; 810 811 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 812 return 0; 813 } 814 815 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, 816 uintptr_t ra) 817 { 818 uint64_t pba = ldq_p(&fib.pba); 819 uint64_t pal = ldq_p(&fib.pal); 820 uint64_t g_iota = ldq_p(&fib.iota); 821 uint8_t dt = (g_iota >> 2) & 0x7; 822 uint8_t t = (g_iota >> 11) & 0x1; 823 824 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) { 825 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 826 return -EINVAL; 827 } 828 829 /* currently we only support designation type 1 with translation */ 830 if (!(dt == ZPCI_IOTA_RTTO && t)) { 831 error_report("unsupported ioat dt %d t %d", dt, t); 832 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 833 return -EINVAL; 834 } 835 836 iommu->pba = pba; 837 iommu->pal = pal; 838 iommu->g_iota = g_iota; 839 840 s390_pci_iommu_enable(iommu); 841 842 return 0; 843 } 844 845 void pci_dereg_ioat(S390PCIIOMMU *iommu) 846 { 847 s390_pci_iommu_disable(iommu); 848 iommu->pba = 0; 849 iommu->pal = 0; 850 iommu->g_iota = 0; 851 } 852 853 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 854 uintptr_t ra) 855 { 856 CPUS390XState *env = &cpu->env; 857 uint8_t oc, dmaas; 858 uint32_t fh; 859 ZpciFib fib; 860 S390PCIBusDevice *pbdev; 861 uint64_t cc = ZPCI_PCI_LS_OK; 862 863 if (env->psw.mask & PSW_MASK_PSTATE) { 864 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 865 return 0; 866 } 867 868 oc = env->regs[r1] & 0xff; 869 dmaas = (env->regs[r1] >> 16) & 0xff; 870 fh = env->regs[r1] >> 32; 871 872 if (fiba & 0x7) { 873 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 874 return 0; 875 } 876 877 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 878 if (!pbdev) { 879 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh); 880 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 881 return 0; 882 } 883 884 switch (pbdev->state) { 885 case ZPCI_FS_RESERVED: 886 case ZPCI_FS_STANDBY: 887 case ZPCI_FS_DISABLED: 888 case ZPCI_FS_PERMANENT_ERROR: 889 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 890 return 0; 891 default: 892 break; 893 } 894 895 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 896 s390_cpu_virt_mem_handle_exc(cpu, ra); 897 return 0; 898 } 899 900 if (fib.fmt != 0) { 901 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 902 return 0; 903 } 904 905 switch (oc) { 906 case ZPCI_MOD_FC_REG_INT: 907 if (pbdev->summary_ind) { 908 cc = ZPCI_PCI_LS_ERR; 909 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 910 } else if (reg_irqs(env, pbdev, fib)) { 911 cc = ZPCI_PCI_LS_ERR; 912 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL); 913 } 914 break; 915 case ZPCI_MOD_FC_DEREG_INT: 916 if (!pbdev->summary_ind) { 917 cc = ZPCI_PCI_LS_ERR; 918 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 919 } else { 920 pci_dereg_irqs(pbdev); 921 } 922 break; 923 case ZPCI_MOD_FC_REG_IOAT: 924 if (dmaas != 0) { 925 cc = ZPCI_PCI_LS_ERR; 926 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 927 } else if (pbdev->iommu->enabled) { 928 cc = ZPCI_PCI_LS_ERR; 929 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 930 } else if (reg_ioat(env, pbdev->iommu, fib, ra)) { 931 cc = ZPCI_PCI_LS_ERR; 932 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 933 } 934 break; 935 case ZPCI_MOD_FC_DEREG_IOAT: 936 if (dmaas != 0) { 937 cc = ZPCI_PCI_LS_ERR; 938 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 939 } else if (!pbdev->iommu->enabled) { 940 cc = ZPCI_PCI_LS_ERR; 941 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 942 } else { 943 pci_dereg_ioat(pbdev->iommu); 944 } 945 break; 946 case ZPCI_MOD_FC_REREG_IOAT: 947 if (dmaas != 0) { 948 cc = ZPCI_PCI_LS_ERR; 949 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 950 } else if (!pbdev->iommu->enabled) { 951 cc = ZPCI_PCI_LS_ERR; 952 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 953 } else { 954 pci_dereg_ioat(pbdev->iommu); 955 if (reg_ioat(env, pbdev->iommu, fib, ra)) { 956 cc = ZPCI_PCI_LS_ERR; 957 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 958 } 959 } 960 break; 961 case ZPCI_MOD_FC_RESET_ERROR: 962 switch (pbdev->state) { 963 case ZPCI_FS_BLOCKED: 964 case ZPCI_FS_ERROR: 965 pbdev->state = ZPCI_FS_ENABLED; 966 break; 967 default: 968 cc = ZPCI_PCI_LS_ERR; 969 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 970 } 971 break; 972 case ZPCI_MOD_FC_RESET_BLOCK: 973 switch (pbdev->state) { 974 case ZPCI_FS_ERROR: 975 pbdev->state = ZPCI_FS_BLOCKED; 976 break; 977 default: 978 cc = ZPCI_PCI_LS_ERR; 979 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 980 } 981 break; 982 case ZPCI_MOD_FC_SET_MEASURE: 983 pbdev->fmb_addr = ldq_p(&fib.fmb_addr); 984 break; 985 default: 986 s390_program_interrupt(&cpu->env, PGM_OPERAND, 6, ra); 987 cc = ZPCI_PCI_LS_ERR; 988 } 989 990 setcc(cpu, cc); 991 return 0; 992 } 993 994 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 995 uintptr_t ra) 996 { 997 CPUS390XState *env = &cpu->env; 998 uint8_t dmaas; 999 uint32_t fh; 1000 ZpciFib fib; 1001 S390PCIBusDevice *pbdev; 1002 uint32_t data; 1003 uint64_t cc = ZPCI_PCI_LS_OK; 1004 1005 if (env->psw.mask & PSW_MASK_PSTATE) { 1006 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 1007 return 0; 1008 } 1009 1010 fh = env->regs[r1] >> 32; 1011 dmaas = (env->regs[r1] >> 16) & 0xff; 1012 1013 if (dmaas) { 1014 setcc(cpu, ZPCI_PCI_LS_ERR); 1015 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS); 1016 return 0; 1017 } 1018 1019 if (fiba & 0x7) { 1020 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 1021 return 0; 1022 } 1023 1024 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX); 1025 if (!pbdev) { 1026 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1027 return 0; 1028 } 1029 1030 memset(&fib, 0, sizeof(fib)); 1031 1032 switch (pbdev->state) { 1033 case ZPCI_FS_RESERVED: 1034 case ZPCI_FS_STANDBY: 1035 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1036 return 0; 1037 case ZPCI_FS_DISABLED: 1038 if (fh & FH_MASK_ENABLE) { 1039 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1040 return 0; 1041 } 1042 goto out; 1043 /* BLOCKED bit is set to one coincident with the setting of ERROR bit. 1044 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */ 1045 case ZPCI_FS_ERROR: 1046 fib.fc |= 0x20; 1047 case ZPCI_FS_BLOCKED: 1048 fib.fc |= 0x40; 1049 case ZPCI_FS_ENABLED: 1050 fib.fc |= 0x80; 1051 if (pbdev->iommu->enabled) { 1052 fib.fc |= 0x10; 1053 } 1054 if (!(fh & FH_MASK_ENABLE)) { 1055 env->regs[r1] |= 1ULL << 63; 1056 } 1057 break; 1058 case ZPCI_FS_PERMANENT_ERROR: 1059 setcc(cpu, ZPCI_PCI_LS_ERR); 1060 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR); 1061 return 0; 1062 } 1063 1064 stq_p(&fib.pba, pbdev->iommu->pba); 1065 stq_p(&fib.pal, pbdev->iommu->pal); 1066 stq_p(&fib.iota, pbdev->iommu->g_iota); 1067 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); 1068 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); 1069 stq_p(&fib.fmb_addr, pbdev->fmb_addr); 1070 1071 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | 1072 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | 1073 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; 1074 stl_p(&fib.data, data); 1075 1076 out: 1077 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1078 s390_cpu_virt_mem_handle_exc(cpu, ra); 1079 return 0; 1080 } 1081 1082 setcc(cpu, cc); 1083 return 0; 1084 } 1085