1 /* 2 * s390 PCI instructions 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu-common.h" 16 #include "cpu.h" 17 #include "s390-pci-inst.h" 18 #include "s390-pci-bus.h" 19 #include "exec/memory-internal.h" 20 #include "qemu/error-report.h" 21 #include "sysemu/hw_accel.h" 22 23 #ifndef DEBUG_S390PCI_INST 24 #define DEBUG_S390PCI_INST 0 25 #endif 26 27 #define DPRINTF(fmt, ...) \ 28 do { \ 29 if (DEBUG_S390PCI_INST) { \ 30 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \ 31 } \ 32 } while (0) 33 34 static void s390_set_status_code(CPUS390XState *env, 35 uint8_t r, uint64_t status_code) 36 { 37 env->regs[r] &= ~0xff000000ULL; 38 env->regs[r] |= (status_code & 0xff) << 24; 39 } 40 41 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) 42 { 43 S390PCIBusDevice *pbdev = NULL; 44 S390pciState *s = s390_get_phb(); 45 uint32_t res_code, initial_l2, g_l2; 46 int rc, i; 47 uint64_t resume_token; 48 49 rc = 0; 50 if (lduw_p(&rrb->request.hdr.len) != 32) { 51 res_code = CLP_RC_LEN; 52 rc = -EINVAL; 53 goto out; 54 } 55 56 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { 57 res_code = CLP_RC_FMT; 58 rc = -EINVAL; 59 goto out; 60 } 61 62 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || 63 ldq_p(&rrb->request.reserved1) != 0) { 64 res_code = CLP_RC_RESNOT0; 65 rc = -EINVAL; 66 goto out; 67 } 68 69 resume_token = ldq_p(&rrb->request.resume_token); 70 71 if (resume_token) { 72 pbdev = s390_pci_find_dev_by_idx(s, resume_token); 73 if (!pbdev) { 74 res_code = CLP_RC_LISTPCI_BADRT; 75 rc = -EINVAL; 76 goto out; 77 } 78 } else { 79 pbdev = s390_pci_find_next_avail_dev(s, NULL); 80 } 81 82 if (lduw_p(&rrb->response.hdr.len) < 48) { 83 res_code = CLP_RC_8K; 84 rc = -EINVAL; 85 goto out; 86 } 87 88 initial_l2 = lduw_p(&rrb->response.hdr.len); 89 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry) 90 != 0) { 91 res_code = CLP_RC_LEN; 92 rc = -EINVAL; 93 *cc = 3; 94 goto out; 95 } 96 97 stl_p(&rrb->response.fmt, 0); 98 stq_p(&rrb->response.reserved1, 0); 99 stl_p(&rrb->response.mdd, FH_MASK_SHM); 100 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); 101 rrb->response.flags = UID_CHECKING_ENABLED; 102 rrb->response.entry_size = sizeof(ClpFhListEntry); 103 104 i = 0; 105 g_l2 = LIST_PCI_HDR_LEN; 106 while (g_l2 < initial_l2 && pbdev) { 107 stw_p(&rrb->response.fh_list[i].device_id, 108 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID)); 109 stw_p(&rrb->response.fh_list[i].vendor_id, 110 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID)); 111 /* Ignore RESERVED devices. */ 112 stl_p(&rrb->response.fh_list[i].config, 113 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31); 114 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid); 115 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh); 116 117 g_l2 += sizeof(ClpFhListEntry); 118 /* Add endian check for DPRINTF? */ 119 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n", 120 g_l2, 121 lduw_p(&rrb->response.fh_list[i].vendor_id), 122 lduw_p(&rrb->response.fh_list[i].device_id), 123 ldl_p(&rrb->response.fh_list[i].fid), 124 ldl_p(&rrb->response.fh_list[i].fh)); 125 pbdev = s390_pci_find_next_avail_dev(s, pbdev); 126 i++; 127 } 128 129 if (!pbdev) { 130 resume_token = 0; 131 } else { 132 resume_token = pbdev->fh & FH_MASK_INDEX; 133 } 134 stq_p(&rrb->response.resume_token, resume_token); 135 stw_p(&rrb->response.hdr.len, g_l2); 136 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK); 137 out: 138 if (rc) { 139 DPRINTF("list pci failed rc 0x%x\n", rc); 140 stw_p(&rrb->response.hdr.rsp, res_code); 141 } 142 return rc; 143 } 144 145 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) 146 { 147 ClpReqHdr *reqh; 148 ClpRspHdr *resh; 149 S390PCIBusDevice *pbdev; 150 uint32_t req_len; 151 uint32_t res_len; 152 uint8_t buffer[4096 * 2]; 153 uint8_t cc = 0; 154 CPUS390XState *env = &cpu->env; 155 S390pciState *s = s390_get_phb(); 156 int i; 157 158 cpu_synchronize_state(CPU(cpu)); 159 160 if (env->psw.mask & PSW_MASK_PSTATE) { 161 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 162 return 0; 163 } 164 165 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) { 166 s390_cpu_virt_mem_handle_exc(cpu, ra); 167 return 0; 168 } 169 reqh = (ClpReqHdr *)buffer; 170 req_len = lduw_p(&reqh->len); 171 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) { 172 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 173 return 0; 174 } 175 176 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 177 req_len + sizeof(*resh))) { 178 s390_cpu_virt_mem_handle_exc(cpu, ra); 179 return 0; 180 } 181 resh = (ClpRspHdr *)(buffer + req_len); 182 res_len = lduw_p(&resh->len); 183 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) { 184 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 185 return 0; 186 } 187 if ((req_len + res_len) > 8192) { 188 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 189 return 0; 190 } 191 192 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 193 req_len + res_len)) { 194 s390_cpu_virt_mem_handle_exc(cpu, ra); 195 return 0; 196 } 197 198 if (req_len != 32) { 199 stw_p(&resh->rsp, CLP_RC_LEN); 200 goto out; 201 } 202 203 switch (lduw_p(&reqh->cmd)) { 204 case CLP_LIST_PCI: { 205 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer; 206 list_pci(rrb, &cc); 207 break; 208 } 209 case CLP_SET_PCI_FN: { 210 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh; 211 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh; 212 213 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh)); 214 if (!pbdev) { 215 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); 216 goto out; 217 } 218 219 switch (reqsetpci->oc) { 220 case CLP_SET_ENABLE_PCI_FN: 221 switch (reqsetpci->ndas) { 222 case 0: 223 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); 224 goto out; 225 case 1: 226 break; 227 default: 228 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); 229 goto out; 230 } 231 232 if (pbdev->fh & FH_MASK_ENABLE) { 233 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 234 goto out; 235 } 236 237 pbdev->fh |= FH_MASK_ENABLE; 238 pbdev->state = ZPCI_FS_ENABLED; 239 stl_p(&ressetpci->fh, pbdev->fh); 240 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 241 break; 242 case CLP_SET_DISABLE_PCI_FN: 243 if (!(pbdev->fh & FH_MASK_ENABLE)) { 244 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 245 goto out; 246 } 247 device_reset(DEVICE(pbdev)); 248 pbdev->fh &= ~FH_MASK_ENABLE; 249 pbdev->state = ZPCI_FS_DISABLED; 250 stl_p(&ressetpci->fh, pbdev->fh); 251 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 252 break; 253 default: 254 DPRINTF("unknown set pci command\n"); 255 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 256 break; 257 } 258 break; 259 } 260 case CLP_QUERY_PCI_FN: { 261 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh; 262 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh; 263 264 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh)); 265 if (!pbdev) { 266 DPRINTF("query pci no pci dev\n"); 267 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); 268 goto out; 269 } 270 271 for (i = 0; i < PCI_BAR_COUNT; i++) { 272 uint32_t data = pci_get_long(pbdev->pdev->config + 273 PCI_BASE_ADDRESS_0 + (i * 4)); 274 275 stl_p(&resquery->bar[i], data); 276 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ? 277 ctz64(pbdev->pdev->io_regions[i].size) : 0; 278 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i, 279 ldl_p(&resquery->bar[i]), 280 pbdev->pdev->io_regions[i].size, 281 resquery->bar_size[i]); 282 } 283 284 stq_p(&resquery->sdma, ZPCI_SDMA_ADDR); 285 stq_p(&resquery->edma, ZPCI_EDMA_ADDR); 286 stl_p(&resquery->fid, pbdev->fid); 287 stw_p(&resquery->pchid, 0); 288 stw_p(&resquery->ug, 1); 289 stl_p(&resquery->uid, pbdev->uid); 290 stw_p(&resquery->hdr.rsp, CLP_RC_OK); 291 break; 292 } 293 case CLP_QUERY_PCI_FNGRP: { 294 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh; 295 resgrp->fr = 1; 296 stq_p(&resgrp->dasm, 0); 297 stq_p(&resgrp->msia, ZPCI_MSI_ADDR); 298 stw_p(&resgrp->mui, 0); 299 stw_p(&resgrp->i, 128); 300 resgrp->version = 0; 301 302 stw_p(&resgrp->hdr.rsp, CLP_RC_OK); 303 break; 304 } 305 default: 306 DPRINTF("unknown clp command\n"); 307 stw_p(&resh->rsp, CLP_RC_CMD); 308 break; 309 } 310 311 out: 312 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer, 313 req_len + res_len)) { 314 s390_cpu_virt_mem_handle_exc(cpu, ra); 315 return 0; 316 } 317 setcc(cpu, cc); 318 return 0; 319 } 320 321 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 322 { 323 CPUS390XState *env = &cpu->env; 324 S390PCIBusDevice *pbdev; 325 uint64_t offset; 326 uint64_t data; 327 MemoryRegion *mr; 328 MemTxResult result; 329 uint8_t len; 330 uint32_t fh; 331 uint8_t pcias; 332 333 cpu_synchronize_state(CPU(cpu)); 334 335 if (env->psw.mask & PSW_MASK_PSTATE) { 336 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 337 return 0; 338 } 339 340 if (r2 & 0x1) { 341 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 342 return 0; 343 } 344 345 fh = env->regs[r2] >> 32; 346 pcias = (env->regs[r2] >> 16) & 0xf; 347 len = env->regs[r2] & 0xf; 348 offset = env->regs[r2 + 1]; 349 350 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 351 if (!pbdev) { 352 DPRINTF("pcilg no pci dev\n"); 353 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 354 return 0; 355 } 356 357 switch (pbdev->state) { 358 case ZPCI_FS_RESERVED: 359 case ZPCI_FS_STANDBY: 360 case ZPCI_FS_DISABLED: 361 case ZPCI_FS_PERMANENT_ERROR: 362 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 363 return 0; 364 case ZPCI_FS_ERROR: 365 setcc(cpu, ZPCI_PCI_LS_ERR); 366 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 367 return 0; 368 default: 369 break; 370 } 371 372 if (pcias < 6) { 373 if ((8 - (offset & 0x7)) < len) { 374 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 375 return 0; 376 } 377 mr = pbdev->pdev->io_regions[pcias].memory; 378 result = memory_region_dispatch_read(mr, offset, &data, len, 379 MEMTXATTRS_UNSPECIFIED); 380 if (result != MEMTX_OK) { 381 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 382 return 0; 383 } 384 } else if (pcias == 15) { 385 if ((4 - (offset & 0x3)) < len) { 386 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 387 return 0; 388 } 389 data = pci_host_config_read_common( 390 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len); 391 392 switch (len) { 393 case 1: 394 break; 395 case 2: 396 data = bswap16(data); 397 break; 398 case 4: 399 data = bswap32(data); 400 break; 401 case 8: 402 data = bswap64(data); 403 break; 404 default: 405 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 406 return 0; 407 } 408 } else { 409 DPRINTF("invalid space\n"); 410 setcc(cpu, ZPCI_PCI_LS_ERR); 411 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 412 return 0; 413 } 414 415 env->regs[r1] = data; 416 setcc(cpu, ZPCI_PCI_LS_OK); 417 return 0; 418 } 419 420 static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias) 421 { 422 if (pbdev->msix.available && pbdev->msix.table_bar == pcias && 423 offset >= pbdev->msix.table_offset && 424 offset < (pbdev->msix.table_offset + 425 pbdev->msix.entries * PCI_MSIX_ENTRY_SIZE)) { 426 return 1; 427 } else { 428 return 0; 429 } 430 } 431 432 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 433 { 434 CPUS390XState *env = &cpu->env; 435 uint64_t offset, data; 436 S390PCIBusDevice *pbdev; 437 MemoryRegion *mr; 438 MemTxResult result; 439 uint8_t len; 440 uint32_t fh; 441 uint8_t pcias; 442 443 cpu_synchronize_state(CPU(cpu)); 444 445 if (env->psw.mask & PSW_MASK_PSTATE) { 446 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 447 return 0; 448 } 449 450 if (r2 & 0x1) { 451 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 452 return 0; 453 } 454 455 fh = env->regs[r2] >> 32; 456 pcias = (env->regs[r2] >> 16) & 0xf; 457 len = env->regs[r2] & 0xf; 458 offset = env->regs[r2 + 1]; 459 460 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 461 if (!pbdev) { 462 DPRINTF("pcistg no pci dev\n"); 463 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 464 return 0; 465 } 466 467 switch (pbdev->state) { 468 case ZPCI_FS_RESERVED: 469 case ZPCI_FS_STANDBY: 470 case ZPCI_FS_DISABLED: 471 case ZPCI_FS_PERMANENT_ERROR: 472 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 473 return 0; 474 case ZPCI_FS_ERROR: 475 setcc(cpu, ZPCI_PCI_LS_ERR); 476 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 477 return 0; 478 default: 479 break; 480 } 481 482 data = env->regs[r1]; 483 if (pcias < 6) { 484 if ((8 - (offset & 0x7)) < len) { 485 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 486 return 0; 487 } 488 489 if (trap_msix(pbdev, offset, pcias)) { 490 offset = offset - pbdev->msix.table_offset; 491 mr = &pbdev->pdev->msix_table_mmio; 492 } else { 493 mr = pbdev->pdev->io_regions[pcias].memory; 494 } 495 496 result = memory_region_dispatch_write(mr, offset, data, len, 497 MEMTXATTRS_UNSPECIFIED); 498 if (result != MEMTX_OK) { 499 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 500 return 0; 501 } 502 } else if (pcias == 15) { 503 if ((4 - (offset & 0x3)) < len) { 504 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 505 return 0; 506 } 507 switch (len) { 508 case 1: 509 break; 510 case 2: 511 data = bswap16(data); 512 break; 513 case 4: 514 data = bswap32(data); 515 break; 516 case 8: 517 data = bswap64(data); 518 break; 519 default: 520 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 521 return 0; 522 } 523 524 pci_host_config_write_common(pbdev->pdev, offset, 525 pci_config_size(pbdev->pdev), 526 data, len); 527 } else { 528 DPRINTF("pcistg invalid space\n"); 529 setcc(cpu, ZPCI_PCI_LS_ERR); 530 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 531 return 0; 532 } 533 534 setcc(cpu, ZPCI_PCI_LS_OK); 535 return 0; 536 } 537 538 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 539 { 540 CPUS390XState *env = &cpu->env; 541 uint32_t fh; 542 S390PCIBusDevice *pbdev; 543 S390PCIIOMMU *iommu; 544 hwaddr start, end; 545 IOMMUTLBEntry entry; 546 IOMMUMemoryRegion *iommu_mr; 547 IOMMUMemoryRegionClass *imrc; 548 549 cpu_synchronize_state(CPU(cpu)); 550 551 if (env->psw.mask & PSW_MASK_PSTATE) { 552 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 553 goto out; 554 } 555 556 if (r2 & 0x1) { 557 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 558 goto out; 559 } 560 561 fh = env->regs[r1] >> 32; 562 start = env->regs[r2]; 563 end = start + env->regs[r2 + 1]; 564 565 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 566 if (!pbdev) { 567 DPRINTF("rpcit no pci dev\n"); 568 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 569 goto out; 570 } 571 572 switch (pbdev->state) { 573 case ZPCI_FS_RESERVED: 574 case ZPCI_FS_STANDBY: 575 case ZPCI_FS_DISABLED: 576 case ZPCI_FS_PERMANENT_ERROR: 577 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 578 return 0; 579 case ZPCI_FS_ERROR: 580 setcc(cpu, ZPCI_PCI_LS_ERR); 581 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER); 582 return 0; 583 default: 584 break; 585 } 586 587 iommu = pbdev->iommu; 588 if (!iommu->g_iota) { 589 pbdev->state = ZPCI_FS_ERROR; 590 setcc(cpu, ZPCI_PCI_LS_ERR); 591 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 592 s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid, 593 start, 0); 594 goto out; 595 } 596 597 if (end < iommu->pba || start > iommu->pal) { 598 pbdev->state = ZPCI_FS_ERROR; 599 setcc(cpu, ZPCI_PCI_LS_ERR); 600 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 601 s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid, 602 start, 0); 603 goto out; 604 } 605 606 iommu_mr = &iommu->iommu_mr; 607 imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); 608 609 while (start < end) { 610 entry = imrc->translate(iommu_mr, start, IOMMU_NONE); 611 612 if (!entry.translated_addr) { 613 pbdev->state = ZPCI_FS_ERROR; 614 setcc(cpu, ZPCI_PCI_LS_ERR); 615 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 616 s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid, 617 start, ERR_EVENT_Q_BIT); 618 goto out; 619 } 620 621 memory_region_notify_iommu(iommu_mr, entry); 622 start += entry.addr_mask + 1; 623 } 624 625 setcc(cpu, ZPCI_PCI_LS_OK); 626 out: 627 return 0; 628 } 629 630 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, 631 uint8_t ar, uintptr_t ra) 632 { 633 CPUS390XState *env = &cpu->env; 634 S390PCIBusDevice *pbdev; 635 MemoryRegion *mr; 636 MemTxResult result; 637 int i; 638 uint32_t fh; 639 uint8_t pcias; 640 uint8_t len; 641 uint8_t buffer[128]; 642 643 if (env->psw.mask & PSW_MASK_PSTATE) { 644 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 645 return 0; 646 } 647 648 fh = env->regs[r1] >> 32; 649 pcias = (env->regs[r1] >> 16) & 0xf; 650 len = env->regs[r1] & 0xff; 651 652 if (pcias > 5) { 653 DPRINTF("pcistb invalid space\n"); 654 setcc(cpu, ZPCI_PCI_LS_ERR); 655 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS); 656 return 0; 657 } 658 659 switch (len) { 660 case 16: 661 case 32: 662 case 64: 663 case 128: 664 break; 665 default: 666 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 667 return 0; 668 } 669 670 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 671 if (!pbdev) { 672 DPRINTF("pcistb no pci dev fh 0x%x\n", fh); 673 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 674 return 0; 675 } 676 677 switch (pbdev->state) { 678 case ZPCI_FS_RESERVED: 679 case ZPCI_FS_STANDBY: 680 case ZPCI_FS_DISABLED: 681 case ZPCI_FS_PERMANENT_ERROR: 682 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 683 return 0; 684 case ZPCI_FS_ERROR: 685 setcc(cpu, ZPCI_PCI_LS_ERR); 686 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED); 687 return 0; 688 default: 689 break; 690 } 691 692 mr = pbdev->pdev->io_regions[pcias].memory; 693 if (!memory_region_access_valid(mr, env->regs[r3], len, true)) { 694 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 695 return 0; 696 } 697 698 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) { 699 s390_cpu_virt_mem_handle_exc(cpu, ra); 700 return 0; 701 } 702 703 for (i = 0; i < len / 8; i++) { 704 result = memory_region_dispatch_write(mr, env->regs[r3] + i * 8, 705 ldq_p(buffer + i * 8), 8, 706 MEMTXATTRS_UNSPECIFIED); 707 if (result != MEMTX_OK) { 708 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 709 return 0; 710 } 711 } 712 713 setcc(cpu, ZPCI_PCI_LS_OK); 714 return 0; 715 } 716 717 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) 718 { 719 int ret, len; 720 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data)); 721 722 pbdev->routes.adapter.adapter_id = css_get_adapter_id( 723 CSS_IO_ADAPTER_PCI, isc); 724 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t)); 725 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long); 726 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len); 727 728 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 729 if (ret) { 730 goto out; 731 } 732 733 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator); 734 if (ret) { 735 goto out; 736 } 737 738 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb); 739 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data)); 740 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv); 741 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data)); 742 pbdev->isc = isc; 743 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data)); 744 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data)); 745 746 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 747 return 0; 748 out: 749 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 750 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 751 pbdev->summary_ind = NULL; 752 pbdev->indicator = NULL; 753 return ret; 754 } 755 756 int pci_dereg_irqs(S390PCIBusDevice *pbdev) 757 { 758 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 759 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 760 761 pbdev->summary_ind = NULL; 762 pbdev->indicator = NULL; 763 pbdev->routes.adapter.summary_addr = 0; 764 pbdev->routes.adapter.summary_offset = 0; 765 pbdev->routes.adapter.ind_addr = 0; 766 pbdev->routes.adapter.ind_offset = 0; 767 pbdev->isc = 0; 768 pbdev->noi = 0; 769 pbdev->sum = 0; 770 771 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 772 return 0; 773 } 774 775 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, 776 uintptr_t ra) 777 { 778 uint64_t pba = ldq_p(&fib.pba); 779 uint64_t pal = ldq_p(&fib.pal); 780 uint64_t g_iota = ldq_p(&fib.iota); 781 uint8_t dt = (g_iota >> 2) & 0x7; 782 uint8_t t = (g_iota >> 11) & 0x1; 783 784 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) { 785 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 786 return -EINVAL; 787 } 788 789 /* currently we only support designation type 1 with translation */ 790 if (!(dt == ZPCI_IOTA_RTTO && t)) { 791 error_report("unsupported ioat dt %d t %d", dt, t); 792 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 793 return -EINVAL; 794 } 795 796 iommu->pba = pba; 797 iommu->pal = pal; 798 iommu->g_iota = g_iota; 799 800 s390_pci_iommu_enable(iommu); 801 802 return 0; 803 } 804 805 void pci_dereg_ioat(S390PCIIOMMU *iommu) 806 { 807 s390_pci_iommu_disable(iommu); 808 iommu->pba = 0; 809 iommu->pal = 0; 810 iommu->g_iota = 0; 811 } 812 813 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 814 uintptr_t ra) 815 { 816 CPUS390XState *env = &cpu->env; 817 uint8_t oc, dmaas; 818 uint32_t fh; 819 ZpciFib fib; 820 S390PCIBusDevice *pbdev; 821 uint64_t cc = ZPCI_PCI_LS_OK; 822 823 if (env->psw.mask & PSW_MASK_PSTATE) { 824 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 825 return 0; 826 } 827 828 oc = env->regs[r1] & 0xff; 829 dmaas = (env->regs[r1] >> 16) & 0xff; 830 fh = env->regs[r1] >> 32; 831 832 if (fiba & 0x7) { 833 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 834 return 0; 835 } 836 837 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 838 if (!pbdev) { 839 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh); 840 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 841 return 0; 842 } 843 844 switch (pbdev->state) { 845 case ZPCI_FS_RESERVED: 846 case ZPCI_FS_STANDBY: 847 case ZPCI_FS_DISABLED: 848 case ZPCI_FS_PERMANENT_ERROR: 849 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 850 return 0; 851 default: 852 break; 853 } 854 855 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 856 s390_cpu_virt_mem_handle_exc(cpu, ra); 857 return 0; 858 } 859 860 if (fib.fmt != 0) { 861 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 862 return 0; 863 } 864 865 switch (oc) { 866 case ZPCI_MOD_FC_REG_INT: 867 if (pbdev->summary_ind) { 868 cc = ZPCI_PCI_LS_ERR; 869 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 870 } else if (reg_irqs(env, pbdev, fib)) { 871 cc = ZPCI_PCI_LS_ERR; 872 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL); 873 } 874 break; 875 case ZPCI_MOD_FC_DEREG_INT: 876 if (!pbdev->summary_ind) { 877 cc = ZPCI_PCI_LS_ERR; 878 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 879 } else { 880 pci_dereg_irqs(pbdev); 881 } 882 break; 883 case ZPCI_MOD_FC_REG_IOAT: 884 if (dmaas != 0) { 885 cc = ZPCI_PCI_LS_ERR; 886 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 887 } else if (pbdev->iommu->enabled) { 888 cc = ZPCI_PCI_LS_ERR; 889 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 890 } else if (reg_ioat(env, pbdev->iommu, fib, ra)) { 891 cc = ZPCI_PCI_LS_ERR; 892 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 893 } 894 break; 895 case ZPCI_MOD_FC_DEREG_IOAT: 896 if (dmaas != 0) { 897 cc = ZPCI_PCI_LS_ERR; 898 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 899 } else if (!pbdev->iommu->enabled) { 900 cc = ZPCI_PCI_LS_ERR; 901 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 902 } else { 903 pci_dereg_ioat(pbdev->iommu); 904 } 905 break; 906 case ZPCI_MOD_FC_REREG_IOAT: 907 if (dmaas != 0) { 908 cc = ZPCI_PCI_LS_ERR; 909 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 910 } else if (!pbdev->iommu->enabled) { 911 cc = ZPCI_PCI_LS_ERR; 912 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 913 } else { 914 pci_dereg_ioat(pbdev->iommu); 915 if (reg_ioat(env, pbdev->iommu, fib, ra)) { 916 cc = ZPCI_PCI_LS_ERR; 917 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 918 } 919 } 920 break; 921 case ZPCI_MOD_FC_RESET_ERROR: 922 switch (pbdev->state) { 923 case ZPCI_FS_BLOCKED: 924 case ZPCI_FS_ERROR: 925 pbdev->state = ZPCI_FS_ENABLED; 926 break; 927 default: 928 cc = ZPCI_PCI_LS_ERR; 929 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 930 } 931 break; 932 case ZPCI_MOD_FC_RESET_BLOCK: 933 switch (pbdev->state) { 934 case ZPCI_FS_ERROR: 935 pbdev->state = ZPCI_FS_BLOCKED; 936 break; 937 default: 938 cc = ZPCI_PCI_LS_ERR; 939 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 940 } 941 break; 942 case ZPCI_MOD_FC_SET_MEASURE: 943 pbdev->fmb_addr = ldq_p(&fib.fmb_addr); 944 break; 945 default: 946 s390_program_interrupt(&cpu->env, PGM_OPERAND, 6, ra); 947 cc = ZPCI_PCI_LS_ERR; 948 } 949 950 setcc(cpu, cc); 951 return 0; 952 } 953 954 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 955 uintptr_t ra) 956 { 957 CPUS390XState *env = &cpu->env; 958 uint8_t dmaas; 959 uint32_t fh; 960 ZpciFib fib; 961 S390PCIBusDevice *pbdev; 962 uint32_t data; 963 uint64_t cc = ZPCI_PCI_LS_OK; 964 965 if (env->psw.mask & PSW_MASK_PSTATE) { 966 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 967 return 0; 968 } 969 970 fh = env->regs[r1] >> 32; 971 dmaas = (env->regs[r1] >> 16) & 0xff; 972 973 if (dmaas) { 974 setcc(cpu, ZPCI_PCI_LS_ERR); 975 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS); 976 return 0; 977 } 978 979 if (fiba & 0x7) { 980 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 981 return 0; 982 } 983 984 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX); 985 if (!pbdev) { 986 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 987 return 0; 988 } 989 990 memset(&fib, 0, sizeof(fib)); 991 992 switch (pbdev->state) { 993 case ZPCI_FS_RESERVED: 994 case ZPCI_FS_STANDBY: 995 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 996 return 0; 997 case ZPCI_FS_DISABLED: 998 if (fh & FH_MASK_ENABLE) { 999 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1000 return 0; 1001 } 1002 goto out; 1003 /* BLOCKED bit is set to one coincident with the setting of ERROR bit. 1004 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */ 1005 case ZPCI_FS_ERROR: 1006 fib.fc |= 0x20; 1007 case ZPCI_FS_BLOCKED: 1008 fib.fc |= 0x40; 1009 case ZPCI_FS_ENABLED: 1010 fib.fc |= 0x80; 1011 if (pbdev->iommu->enabled) { 1012 fib.fc |= 0x10; 1013 } 1014 if (!(fh & FH_MASK_ENABLE)) { 1015 env->regs[r1] |= 1ULL << 63; 1016 } 1017 break; 1018 case ZPCI_FS_PERMANENT_ERROR: 1019 setcc(cpu, ZPCI_PCI_LS_ERR); 1020 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR); 1021 return 0; 1022 } 1023 1024 stq_p(&fib.pba, pbdev->iommu->pba); 1025 stq_p(&fib.pal, pbdev->iommu->pal); 1026 stq_p(&fib.iota, pbdev->iommu->g_iota); 1027 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); 1028 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); 1029 stq_p(&fib.fmb_addr, pbdev->fmb_addr); 1030 1031 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | 1032 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | 1033 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; 1034 stl_p(&fib.data, data); 1035 1036 out: 1037 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1038 s390_cpu_virt_mem_handle_exc(cpu, ra); 1039 return 0; 1040 } 1041 1042 setcc(cpu, cc); 1043 return 0; 1044 } 1045