1 /* 2 * s390 PCI instructions 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu-common.h" 16 #include "cpu.h" 17 #include "s390-pci-inst.h" 18 #include "s390-pci-bus.h" 19 #include "exec/memory-internal.h" 20 #include "qemu/error-report.h" 21 #include "sysemu/hw_accel.h" 22 23 #ifndef DEBUG_S390PCI_INST 24 #define DEBUG_S390PCI_INST 0 25 #endif 26 27 #define DPRINTF(fmt, ...) \ 28 do { \ 29 if (DEBUG_S390PCI_INST) { \ 30 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \ 31 } \ 32 } while (0) 33 34 static void s390_set_status_code(CPUS390XState *env, 35 uint8_t r, uint64_t status_code) 36 { 37 env->regs[r] &= ~0xff000000ULL; 38 env->regs[r] |= (status_code & 0xff) << 24; 39 } 40 41 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) 42 { 43 S390PCIBusDevice *pbdev = NULL; 44 S390pciState *s = s390_get_phb(); 45 uint32_t res_code, initial_l2, g_l2; 46 int rc, i; 47 uint64_t resume_token; 48 49 rc = 0; 50 if (lduw_p(&rrb->request.hdr.len) != 32) { 51 res_code = CLP_RC_LEN; 52 rc = -EINVAL; 53 goto out; 54 } 55 56 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { 57 res_code = CLP_RC_FMT; 58 rc = -EINVAL; 59 goto out; 60 } 61 62 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || 63 ldq_p(&rrb->request.reserved1) != 0) { 64 res_code = CLP_RC_RESNOT0; 65 rc = -EINVAL; 66 goto out; 67 } 68 69 resume_token = ldq_p(&rrb->request.resume_token); 70 71 if (resume_token) { 72 pbdev = s390_pci_find_dev_by_idx(s, resume_token); 73 if (!pbdev) { 74 res_code = CLP_RC_LISTPCI_BADRT; 75 rc = -EINVAL; 76 goto out; 77 } 78 } else { 79 pbdev = s390_pci_find_next_avail_dev(s, NULL); 80 } 81 82 if (lduw_p(&rrb->response.hdr.len) < 48) { 83 res_code = CLP_RC_8K; 84 rc = -EINVAL; 85 goto out; 86 } 87 88 initial_l2 = lduw_p(&rrb->response.hdr.len); 89 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry) 90 != 0) { 91 res_code = CLP_RC_LEN; 92 rc = -EINVAL; 93 *cc = 3; 94 goto out; 95 } 96 97 stl_p(&rrb->response.fmt, 0); 98 stq_p(&rrb->response.reserved1, 0); 99 stl_p(&rrb->response.mdd, FH_MASK_SHM); 100 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); 101 rrb->response.flags = UID_CHECKING_ENABLED; 102 rrb->response.entry_size = sizeof(ClpFhListEntry); 103 104 i = 0; 105 g_l2 = LIST_PCI_HDR_LEN; 106 while (g_l2 < initial_l2 && pbdev) { 107 stw_p(&rrb->response.fh_list[i].device_id, 108 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID)); 109 stw_p(&rrb->response.fh_list[i].vendor_id, 110 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID)); 111 /* Ignore RESERVED devices. */ 112 stl_p(&rrb->response.fh_list[i].config, 113 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31); 114 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid); 115 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh); 116 117 g_l2 += sizeof(ClpFhListEntry); 118 /* Add endian check for DPRINTF? */ 119 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n", 120 g_l2, 121 lduw_p(&rrb->response.fh_list[i].vendor_id), 122 lduw_p(&rrb->response.fh_list[i].device_id), 123 ldl_p(&rrb->response.fh_list[i].fid), 124 ldl_p(&rrb->response.fh_list[i].fh)); 125 pbdev = s390_pci_find_next_avail_dev(s, pbdev); 126 i++; 127 } 128 129 if (!pbdev) { 130 resume_token = 0; 131 } else { 132 resume_token = pbdev->fh & FH_MASK_INDEX; 133 } 134 stq_p(&rrb->response.resume_token, resume_token); 135 stw_p(&rrb->response.hdr.len, g_l2); 136 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK); 137 out: 138 if (rc) { 139 DPRINTF("list pci failed rc 0x%x\n", rc); 140 stw_p(&rrb->response.hdr.rsp, res_code); 141 } 142 return rc; 143 } 144 145 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) 146 { 147 ClpReqHdr *reqh; 148 ClpRspHdr *resh; 149 S390PCIBusDevice *pbdev; 150 uint32_t req_len; 151 uint32_t res_len; 152 uint8_t buffer[4096 * 2]; 153 uint8_t cc = 0; 154 CPUS390XState *env = &cpu->env; 155 S390pciState *s = s390_get_phb(); 156 int i; 157 158 cpu_synchronize_state(CPU(cpu)); 159 160 if (env->psw.mask & PSW_MASK_PSTATE) { 161 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 162 return 0; 163 } 164 165 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) { 166 s390_cpu_virt_mem_handle_exc(cpu, ra); 167 return 0; 168 } 169 reqh = (ClpReqHdr *)buffer; 170 req_len = lduw_p(&reqh->len); 171 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) { 172 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 173 return 0; 174 } 175 176 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 177 req_len + sizeof(*resh))) { 178 s390_cpu_virt_mem_handle_exc(cpu, ra); 179 return 0; 180 } 181 resh = (ClpRspHdr *)(buffer + req_len); 182 res_len = lduw_p(&resh->len); 183 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) { 184 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 185 return 0; 186 } 187 if ((req_len + res_len) > 8192) { 188 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 189 return 0; 190 } 191 192 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 193 req_len + res_len)) { 194 s390_cpu_virt_mem_handle_exc(cpu, ra); 195 return 0; 196 } 197 198 if (req_len != 32) { 199 stw_p(&resh->rsp, CLP_RC_LEN); 200 goto out; 201 } 202 203 switch (lduw_p(&reqh->cmd)) { 204 case CLP_LIST_PCI: { 205 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer; 206 list_pci(rrb, &cc); 207 break; 208 } 209 case CLP_SET_PCI_FN: { 210 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh; 211 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh; 212 213 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh)); 214 if (!pbdev) { 215 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); 216 goto out; 217 } 218 219 switch (reqsetpci->oc) { 220 case CLP_SET_ENABLE_PCI_FN: 221 switch (reqsetpci->ndas) { 222 case 0: 223 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); 224 goto out; 225 case 1: 226 break; 227 default: 228 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); 229 goto out; 230 } 231 232 if (pbdev->fh & FH_MASK_ENABLE) { 233 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 234 goto out; 235 } 236 237 pbdev->fh |= FH_MASK_ENABLE; 238 pbdev->state = ZPCI_FS_ENABLED; 239 stl_p(&ressetpci->fh, pbdev->fh); 240 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 241 break; 242 case CLP_SET_DISABLE_PCI_FN: 243 if (!(pbdev->fh & FH_MASK_ENABLE)) { 244 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 245 goto out; 246 } 247 device_reset(DEVICE(pbdev)); 248 pbdev->fh &= ~FH_MASK_ENABLE; 249 pbdev->state = ZPCI_FS_DISABLED; 250 stl_p(&ressetpci->fh, pbdev->fh); 251 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 252 break; 253 default: 254 DPRINTF("unknown set pci command\n"); 255 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 256 break; 257 } 258 break; 259 } 260 case CLP_QUERY_PCI_FN: { 261 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh; 262 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh; 263 264 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh)); 265 if (!pbdev) { 266 DPRINTF("query pci no pci dev\n"); 267 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); 268 goto out; 269 } 270 271 for (i = 0; i < PCI_BAR_COUNT; i++) { 272 uint32_t data = pci_get_long(pbdev->pdev->config + 273 PCI_BASE_ADDRESS_0 + (i * 4)); 274 275 stl_p(&resquery->bar[i], data); 276 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ? 277 ctz64(pbdev->pdev->io_regions[i].size) : 0; 278 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i, 279 ldl_p(&resquery->bar[i]), 280 pbdev->pdev->io_regions[i].size, 281 resquery->bar_size[i]); 282 } 283 284 stq_p(&resquery->sdma, ZPCI_SDMA_ADDR); 285 stq_p(&resquery->edma, ZPCI_EDMA_ADDR); 286 stl_p(&resquery->fid, pbdev->fid); 287 stw_p(&resquery->pchid, 0); 288 stw_p(&resquery->ug, 1); 289 stl_p(&resquery->uid, pbdev->uid); 290 stw_p(&resquery->hdr.rsp, CLP_RC_OK); 291 break; 292 } 293 case CLP_QUERY_PCI_FNGRP: { 294 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh; 295 resgrp->fr = 1; 296 stq_p(&resgrp->dasm, 0); 297 stq_p(&resgrp->msia, ZPCI_MSI_ADDR); 298 stw_p(&resgrp->mui, 0); 299 stw_p(&resgrp->i, 128); 300 resgrp->version = 0; 301 302 stw_p(&resgrp->hdr.rsp, CLP_RC_OK); 303 break; 304 } 305 default: 306 DPRINTF("unknown clp command\n"); 307 stw_p(&resh->rsp, CLP_RC_CMD); 308 break; 309 } 310 311 out: 312 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer, 313 req_len + res_len)) { 314 s390_cpu_virt_mem_handle_exc(cpu, ra); 315 return 0; 316 } 317 setcc(cpu, cc); 318 return 0; 319 } 320 321 /** 322 * Swap data contained in s390x big endian registers to little endian 323 * PCI bars. 324 * 325 * @ptr: a pointer to a uint64_t data field 326 * @len: the length of the valid data, must be 1,2,4 or 8 327 */ 328 static int zpci_endian_swap(uint64_t *ptr, uint8_t len) 329 { 330 uint64_t data = *ptr; 331 332 switch (len) { 333 case 1: 334 break; 335 case 2: 336 data = bswap16(data); 337 break; 338 case 4: 339 data = bswap32(data); 340 break; 341 case 8: 342 data = bswap64(data); 343 break; 344 default: 345 return -EINVAL; 346 } 347 *ptr = data; 348 return 0; 349 } 350 351 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 352 { 353 CPUS390XState *env = &cpu->env; 354 S390PCIBusDevice *pbdev; 355 uint64_t offset; 356 uint64_t data; 357 MemoryRegion *mr; 358 MemTxResult result; 359 uint8_t len; 360 uint32_t fh; 361 uint8_t pcias; 362 363 cpu_synchronize_state(CPU(cpu)); 364 365 if (env->psw.mask & PSW_MASK_PSTATE) { 366 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 367 return 0; 368 } 369 370 if (r2 & 0x1) { 371 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 372 return 0; 373 } 374 375 fh = env->regs[r2] >> 32; 376 pcias = (env->regs[r2] >> 16) & 0xf; 377 len = env->regs[r2] & 0xf; 378 offset = env->regs[r2 + 1]; 379 380 if (!(fh & FH_MASK_ENABLE)) { 381 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 382 return 0; 383 } 384 385 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 386 if (!pbdev) { 387 DPRINTF("pcilg no pci dev\n"); 388 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 389 return 0; 390 } 391 392 switch (pbdev->state) { 393 case ZPCI_FS_PERMANENT_ERROR: 394 case ZPCI_FS_ERROR: 395 setcc(cpu, ZPCI_PCI_LS_ERR); 396 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 397 return 0; 398 default: 399 break; 400 } 401 402 switch (pcias) { 403 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 404 if (!len || (len > (8 - (offset & 0x7)))) { 405 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 406 return 0; 407 } 408 mr = pbdev->pdev->io_regions[pcias].memory; 409 result = memory_region_dispatch_read(mr, offset, &data, len, 410 MEMTXATTRS_UNSPECIFIED); 411 if (result != MEMTX_OK) { 412 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 413 return 0; 414 } 415 break; 416 case ZPCI_CONFIG_BAR: 417 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 418 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 419 return 0; 420 } 421 data = pci_host_config_read_common( 422 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len); 423 424 if (zpci_endian_swap(&data, len)) { 425 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 426 return 0; 427 } 428 break; 429 default: 430 DPRINTF("pcilg invalid space\n"); 431 setcc(cpu, ZPCI_PCI_LS_ERR); 432 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 433 return 0; 434 } 435 436 env->regs[r1] = data; 437 setcc(cpu, ZPCI_PCI_LS_OK); 438 return 0; 439 } 440 441 static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias) 442 { 443 if (pbdev->msix.available && pbdev->msix.table_bar == pcias && 444 offset >= pbdev->msix.table_offset && 445 offset < (pbdev->msix.table_offset + 446 pbdev->msix.entries * PCI_MSIX_ENTRY_SIZE)) { 447 return 1; 448 } else { 449 return 0; 450 } 451 } 452 453 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 454 { 455 CPUS390XState *env = &cpu->env; 456 uint64_t offset, data; 457 S390PCIBusDevice *pbdev; 458 MemoryRegion *mr; 459 MemTxResult result; 460 uint8_t len; 461 uint32_t fh; 462 uint8_t pcias; 463 464 cpu_synchronize_state(CPU(cpu)); 465 466 if (env->psw.mask & PSW_MASK_PSTATE) { 467 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 468 return 0; 469 } 470 471 if (r2 & 0x1) { 472 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 473 return 0; 474 } 475 476 fh = env->regs[r2] >> 32; 477 pcias = (env->regs[r2] >> 16) & 0xf; 478 len = env->regs[r2] & 0xf; 479 offset = env->regs[r2 + 1]; 480 data = env->regs[r1]; 481 482 if (!(fh & FH_MASK_ENABLE)) { 483 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 484 return 0; 485 } 486 487 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 488 if (!pbdev) { 489 DPRINTF("pcistg no pci dev\n"); 490 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 491 return 0; 492 } 493 494 switch (pbdev->state) { 495 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED 496 * are already covered by the FH_MASK_ENABLE check above 497 */ 498 case ZPCI_FS_PERMANENT_ERROR: 499 case ZPCI_FS_ERROR: 500 setcc(cpu, ZPCI_PCI_LS_ERR); 501 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 502 return 0; 503 default: 504 break; 505 } 506 507 switch (pcias) { 508 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */ 509 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 510 /* Check length: 511 * A length of 0 is invalid and length should not cross a double word 512 */ 513 if (!len || (len > (8 - (offset & 0x7)))) { 514 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 515 return 0; 516 } 517 518 if (trap_msix(pbdev, offset, pcias)) { 519 offset = offset - pbdev->msix.table_offset; 520 mr = &pbdev->pdev->msix_table_mmio; 521 } else { 522 mr = pbdev->pdev->io_regions[pcias].memory; 523 } 524 525 result = memory_region_dispatch_write(mr, offset, data, len, 526 MEMTXATTRS_UNSPECIFIED); 527 if (result != MEMTX_OK) { 528 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 529 return 0; 530 } 531 break; 532 case ZPCI_CONFIG_BAR: 533 /* ZPCI uses the pseudo BAR number 15 as configuration space */ 534 /* possible access lengths are 1,2,4 and must not cross a word */ 535 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 536 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 537 return 0; 538 } 539 /* len = 1,2,4 so we do not need to test */ 540 zpci_endian_swap(&data, len); 541 pci_host_config_write_common(pbdev->pdev, offset, 542 pci_config_size(pbdev->pdev), 543 data, len); 544 break; 545 default: 546 DPRINTF("pcistg invalid space\n"); 547 setcc(cpu, ZPCI_PCI_LS_ERR); 548 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 549 return 0; 550 } 551 552 setcc(cpu, ZPCI_PCI_LS_OK); 553 return 0; 554 } 555 556 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 557 { 558 CPUS390XState *env = &cpu->env; 559 uint32_t fh; 560 S390PCIBusDevice *pbdev; 561 S390PCIIOMMU *iommu; 562 hwaddr start, end; 563 IOMMUTLBEntry entry; 564 IOMMUMemoryRegion *iommu_mr; 565 IOMMUMemoryRegionClass *imrc; 566 567 cpu_synchronize_state(CPU(cpu)); 568 569 if (env->psw.mask & PSW_MASK_PSTATE) { 570 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 571 goto out; 572 } 573 574 if (r2 & 0x1) { 575 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 576 goto out; 577 } 578 579 fh = env->regs[r1] >> 32; 580 start = env->regs[r2]; 581 end = start + env->regs[r2 + 1]; 582 583 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 584 if (!pbdev) { 585 DPRINTF("rpcit no pci dev\n"); 586 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 587 goto out; 588 } 589 590 switch (pbdev->state) { 591 case ZPCI_FS_RESERVED: 592 case ZPCI_FS_STANDBY: 593 case ZPCI_FS_DISABLED: 594 case ZPCI_FS_PERMANENT_ERROR: 595 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 596 return 0; 597 case ZPCI_FS_ERROR: 598 setcc(cpu, ZPCI_PCI_LS_ERR); 599 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER); 600 return 0; 601 default: 602 break; 603 } 604 605 iommu = pbdev->iommu; 606 if (!iommu->g_iota) { 607 pbdev->state = ZPCI_FS_ERROR; 608 setcc(cpu, ZPCI_PCI_LS_ERR); 609 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 610 s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid, 611 start, 0); 612 goto out; 613 } 614 615 if (end < iommu->pba || start > iommu->pal) { 616 pbdev->state = ZPCI_FS_ERROR; 617 setcc(cpu, ZPCI_PCI_LS_ERR); 618 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 619 s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid, 620 start, 0); 621 goto out; 622 } 623 624 iommu_mr = &iommu->iommu_mr; 625 imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr); 626 627 while (start < end) { 628 entry = imrc->translate(iommu_mr, start, IOMMU_NONE); 629 630 if (!entry.translated_addr) { 631 pbdev->state = ZPCI_FS_ERROR; 632 setcc(cpu, ZPCI_PCI_LS_ERR); 633 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES); 634 s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid, 635 start, ERR_EVENT_Q_BIT); 636 goto out; 637 } 638 639 memory_region_notify_iommu(iommu_mr, entry); 640 start += entry.addr_mask + 1; 641 } 642 643 setcc(cpu, ZPCI_PCI_LS_OK); 644 out: 645 return 0; 646 } 647 648 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, 649 uint8_t ar, uintptr_t ra) 650 { 651 CPUS390XState *env = &cpu->env; 652 S390PCIBusDevice *pbdev; 653 MemoryRegion *mr; 654 MemTxResult result; 655 int i; 656 uint32_t fh; 657 uint8_t pcias; 658 uint8_t len; 659 uint8_t buffer[128]; 660 661 if (env->psw.mask & PSW_MASK_PSTATE) { 662 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 663 return 0; 664 } 665 666 fh = env->regs[r1] >> 32; 667 pcias = (env->regs[r1] >> 16) & 0xf; 668 len = env->regs[r1] & 0xff; 669 670 if (pcias > 5) { 671 DPRINTF("pcistb invalid space\n"); 672 setcc(cpu, ZPCI_PCI_LS_ERR); 673 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS); 674 return 0; 675 } 676 677 switch (len) { 678 case 16: 679 case 32: 680 case 64: 681 case 128: 682 break; 683 default: 684 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 685 return 0; 686 } 687 688 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 689 if (!pbdev) { 690 DPRINTF("pcistb no pci dev fh 0x%x\n", fh); 691 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 692 return 0; 693 } 694 695 switch (pbdev->state) { 696 case ZPCI_FS_RESERVED: 697 case ZPCI_FS_STANDBY: 698 case ZPCI_FS_DISABLED: 699 case ZPCI_FS_PERMANENT_ERROR: 700 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 701 return 0; 702 case ZPCI_FS_ERROR: 703 setcc(cpu, ZPCI_PCI_LS_ERR); 704 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED); 705 return 0; 706 default: 707 break; 708 } 709 710 mr = pbdev->pdev->io_regions[pcias].memory; 711 if (!memory_region_access_valid(mr, env->regs[r3], len, true)) { 712 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 713 return 0; 714 } 715 716 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) { 717 s390_cpu_virt_mem_handle_exc(cpu, ra); 718 return 0; 719 } 720 721 for (i = 0; i < len / 8; i++) { 722 result = memory_region_dispatch_write(mr, env->regs[r3] + i * 8, 723 ldq_p(buffer + i * 8), 8, 724 MEMTXATTRS_UNSPECIFIED); 725 if (result != MEMTX_OK) { 726 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 727 return 0; 728 } 729 } 730 731 setcc(cpu, ZPCI_PCI_LS_OK); 732 return 0; 733 } 734 735 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) 736 { 737 int ret, len; 738 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data)); 739 740 pbdev->routes.adapter.adapter_id = css_get_adapter_id( 741 CSS_IO_ADAPTER_PCI, isc); 742 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t)); 743 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long); 744 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len); 745 746 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 747 if (ret) { 748 goto out; 749 } 750 751 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator); 752 if (ret) { 753 goto out; 754 } 755 756 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb); 757 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data)); 758 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv); 759 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data)); 760 pbdev->isc = isc; 761 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data)); 762 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data)); 763 764 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 765 return 0; 766 out: 767 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 768 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 769 pbdev->summary_ind = NULL; 770 pbdev->indicator = NULL; 771 return ret; 772 } 773 774 int pci_dereg_irqs(S390PCIBusDevice *pbdev) 775 { 776 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 777 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 778 779 pbdev->summary_ind = NULL; 780 pbdev->indicator = NULL; 781 pbdev->routes.adapter.summary_addr = 0; 782 pbdev->routes.adapter.summary_offset = 0; 783 pbdev->routes.adapter.ind_addr = 0; 784 pbdev->routes.adapter.ind_offset = 0; 785 pbdev->isc = 0; 786 pbdev->noi = 0; 787 pbdev->sum = 0; 788 789 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 790 return 0; 791 } 792 793 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, 794 uintptr_t ra) 795 { 796 uint64_t pba = ldq_p(&fib.pba); 797 uint64_t pal = ldq_p(&fib.pal); 798 uint64_t g_iota = ldq_p(&fib.iota); 799 uint8_t dt = (g_iota >> 2) & 0x7; 800 uint8_t t = (g_iota >> 11) & 0x1; 801 802 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) { 803 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 804 return -EINVAL; 805 } 806 807 /* currently we only support designation type 1 with translation */ 808 if (!(dt == ZPCI_IOTA_RTTO && t)) { 809 error_report("unsupported ioat dt %d t %d", dt, t); 810 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 811 return -EINVAL; 812 } 813 814 iommu->pba = pba; 815 iommu->pal = pal; 816 iommu->g_iota = g_iota; 817 818 s390_pci_iommu_enable(iommu); 819 820 return 0; 821 } 822 823 void pci_dereg_ioat(S390PCIIOMMU *iommu) 824 { 825 s390_pci_iommu_disable(iommu); 826 iommu->pba = 0; 827 iommu->pal = 0; 828 iommu->g_iota = 0; 829 } 830 831 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 832 uintptr_t ra) 833 { 834 CPUS390XState *env = &cpu->env; 835 uint8_t oc, dmaas; 836 uint32_t fh; 837 ZpciFib fib; 838 S390PCIBusDevice *pbdev; 839 uint64_t cc = ZPCI_PCI_LS_OK; 840 841 if (env->psw.mask & PSW_MASK_PSTATE) { 842 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 843 return 0; 844 } 845 846 oc = env->regs[r1] & 0xff; 847 dmaas = (env->regs[r1] >> 16) & 0xff; 848 fh = env->regs[r1] >> 32; 849 850 if (fiba & 0x7) { 851 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 852 return 0; 853 } 854 855 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 856 if (!pbdev) { 857 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh); 858 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 859 return 0; 860 } 861 862 switch (pbdev->state) { 863 case ZPCI_FS_RESERVED: 864 case ZPCI_FS_STANDBY: 865 case ZPCI_FS_DISABLED: 866 case ZPCI_FS_PERMANENT_ERROR: 867 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 868 return 0; 869 default: 870 break; 871 } 872 873 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 874 s390_cpu_virt_mem_handle_exc(cpu, ra); 875 return 0; 876 } 877 878 if (fib.fmt != 0) { 879 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 880 return 0; 881 } 882 883 switch (oc) { 884 case ZPCI_MOD_FC_REG_INT: 885 if (pbdev->summary_ind) { 886 cc = ZPCI_PCI_LS_ERR; 887 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 888 } else if (reg_irqs(env, pbdev, fib)) { 889 cc = ZPCI_PCI_LS_ERR; 890 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL); 891 } 892 break; 893 case ZPCI_MOD_FC_DEREG_INT: 894 if (!pbdev->summary_ind) { 895 cc = ZPCI_PCI_LS_ERR; 896 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 897 } else { 898 pci_dereg_irqs(pbdev); 899 } 900 break; 901 case ZPCI_MOD_FC_REG_IOAT: 902 if (dmaas != 0) { 903 cc = ZPCI_PCI_LS_ERR; 904 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 905 } else if (pbdev->iommu->enabled) { 906 cc = ZPCI_PCI_LS_ERR; 907 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 908 } else if (reg_ioat(env, pbdev->iommu, fib, ra)) { 909 cc = ZPCI_PCI_LS_ERR; 910 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 911 } 912 break; 913 case ZPCI_MOD_FC_DEREG_IOAT: 914 if (dmaas != 0) { 915 cc = ZPCI_PCI_LS_ERR; 916 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 917 } else if (!pbdev->iommu->enabled) { 918 cc = ZPCI_PCI_LS_ERR; 919 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 920 } else { 921 pci_dereg_ioat(pbdev->iommu); 922 } 923 break; 924 case ZPCI_MOD_FC_REREG_IOAT: 925 if (dmaas != 0) { 926 cc = ZPCI_PCI_LS_ERR; 927 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 928 } else if (!pbdev->iommu->enabled) { 929 cc = ZPCI_PCI_LS_ERR; 930 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 931 } else { 932 pci_dereg_ioat(pbdev->iommu); 933 if (reg_ioat(env, pbdev->iommu, fib, ra)) { 934 cc = ZPCI_PCI_LS_ERR; 935 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 936 } 937 } 938 break; 939 case ZPCI_MOD_FC_RESET_ERROR: 940 switch (pbdev->state) { 941 case ZPCI_FS_BLOCKED: 942 case ZPCI_FS_ERROR: 943 pbdev->state = ZPCI_FS_ENABLED; 944 break; 945 default: 946 cc = ZPCI_PCI_LS_ERR; 947 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 948 } 949 break; 950 case ZPCI_MOD_FC_RESET_BLOCK: 951 switch (pbdev->state) { 952 case ZPCI_FS_ERROR: 953 pbdev->state = ZPCI_FS_BLOCKED; 954 break; 955 default: 956 cc = ZPCI_PCI_LS_ERR; 957 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 958 } 959 break; 960 case ZPCI_MOD_FC_SET_MEASURE: 961 pbdev->fmb_addr = ldq_p(&fib.fmb_addr); 962 break; 963 default: 964 s390_program_interrupt(&cpu->env, PGM_OPERAND, 6, ra); 965 cc = ZPCI_PCI_LS_ERR; 966 } 967 968 setcc(cpu, cc); 969 return 0; 970 } 971 972 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 973 uintptr_t ra) 974 { 975 CPUS390XState *env = &cpu->env; 976 uint8_t dmaas; 977 uint32_t fh; 978 ZpciFib fib; 979 S390PCIBusDevice *pbdev; 980 uint32_t data; 981 uint64_t cc = ZPCI_PCI_LS_OK; 982 983 if (env->psw.mask & PSW_MASK_PSTATE) { 984 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 985 return 0; 986 } 987 988 fh = env->regs[r1] >> 32; 989 dmaas = (env->regs[r1] >> 16) & 0xff; 990 991 if (dmaas) { 992 setcc(cpu, ZPCI_PCI_LS_ERR); 993 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS); 994 return 0; 995 } 996 997 if (fiba & 0x7) { 998 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 999 return 0; 1000 } 1001 1002 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX); 1003 if (!pbdev) { 1004 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1005 return 0; 1006 } 1007 1008 memset(&fib, 0, sizeof(fib)); 1009 1010 switch (pbdev->state) { 1011 case ZPCI_FS_RESERVED: 1012 case ZPCI_FS_STANDBY: 1013 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1014 return 0; 1015 case ZPCI_FS_DISABLED: 1016 if (fh & FH_MASK_ENABLE) { 1017 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1018 return 0; 1019 } 1020 goto out; 1021 /* BLOCKED bit is set to one coincident with the setting of ERROR bit. 1022 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */ 1023 case ZPCI_FS_ERROR: 1024 fib.fc |= 0x20; 1025 case ZPCI_FS_BLOCKED: 1026 fib.fc |= 0x40; 1027 case ZPCI_FS_ENABLED: 1028 fib.fc |= 0x80; 1029 if (pbdev->iommu->enabled) { 1030 fib.fc |= 0x10; 1031 } 1032 if (!(fh & FH_MASK_ENABLE)) { 1033 env->regs[r1] |= 1ULL << 63; 1034 } 1035 break; 1036 case ZPCI_FS_PERMANENT_ERROR: 1037 setcc(cpu, ZPCI_PCI_LS_ERR); 1038 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR); 1039 return 0; 1040 } 1041 1042 stq_p(&fib.pba, pbdev->iommu->pba); 1043 stq_p(&fib.pal, pbdev->iommu->pal); 1044 stq_p(&fib.iota, pbdev->iommu->g_iota); 1045 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); 1046 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); 1047 stq_p(&fib.fmb_addr, pbdev->fmb_addr); 1048 1049 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | 1050 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | 1051 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; 1052 stl_p(&fib.data, data); 1053 1054 out: 1055 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1056 s390_cpu_virt_mem_handle_exc(cpu, ra); 1057 return 0; 1058 } 1059 1060 setcc(cpu, cc); 1061 return 0; 1062 } 1063