1*819ce6b2SPhilippe Mathieu-Daudé /*
2*819ce6b2SPhilippe Mathieu-Daudé * QEMU M48T59 and M48T08 NVRAM emulation (common header)
3*819ce6b2SPhilippe Mathieu-Daudé *
4*819ce6b2SPhilippe Mathieu-Daudé * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5*819ce6b2SPhilippe Mathieu-Daudé * Copyright (c) 2013 Hervé Poussineau
6*819ce6b2SPhilippe Mathieu-Daudé *
7*819ce6b2SPhilippe Mathieu-Daudé * Permission is hereby granted, free of charge, to any person obtaining a copy
8*819ce6b2SPhilippe Mathieu-Daudé * of this software and associated documentation files (the "Software"), to deal
9*819ce6b2SPhilippe Mathieu-Daudé * in the Software without restriction, including without limitation the rights
10*819ce6b2SPhilippe Mathieu-Daudé * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11*819ce6b2SPhilippe Mathieu-Daudé * copies of the Software, and to permit persons to whom the Software is
12*819ce6b2SPhilippe Mathieu-Daudé * furnished to do so, subject to the following conditions:
13*819ce6b2SPhilippe Mathieu-Daudé *
14*819ce6b2SPhilippe Mathieu-Daudé * The above copyright notice and this permission notice shall be included in
15*819ce6b2SPhilippe Mathieu-Daudé * all copies or substantial portions of the Software.
16*819ce6b2SPhilippe Mathieu-Daudé *
17*819ce6b2SPhilippe Mathieu-Daudé * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18*819ce6b2SPhilippe Mathieu-Daudé * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19*819ce6b2SPhilippe Mathieu-Daudé * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20*819ce6b2SPhilippe Mathieu-Daudé * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21*819ce6b2SPhilippe Mathieu-Daudé * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22*819ce6b2SPhilippe Mathieu-Daudé * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23*819ce6b2SPhilippe Mathieu-Daudé * THE SOFTWARE.
24*819ce6b2SPhilippe Mathieu-Daudé */
25*819ce6b2SPhilippe Mathieu-Daudé
26*819ce6b2SPhilippe Mathieu-Daudé #ifndef HW_M48T59_INTERNAL_H
27*819ce6b2SPhilippe Mathieu-Daudé #define HW_M48T59_INTERNAL_H
28*819ce6b2SPhilippe Mathieu-Daudé
29*819ce6b2SPhilippe Mathieu-Daudé /*
30*819ce6b2SPhilippe Mathieu-Daudé * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
31*819ce6b2SPhilippe Mathieu-Daudé * alarm and a watchdog timer and related control registers. In the
32*819ce6b2SPhilippe Mathieu-Daudé * PPC platform there is also a nvram lock function.
33*819ce6b2SPhilippe Mathieu-Daudé */
34*819ce6b2SPhilippe Mathieu-Daudé
35*819ce6b2SPhilippe Mathieu-Daudé typedef struct M48txxInfo {
36*819ce6b2SPhilippe Mathieu-Daudé const char *bus_name;
37*819ce6b2SPhilippe Mathieu-Daudé uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
38*819ce6b2SPhilippe Mathieu-Daudé uint32_t size;
39*819ce6b2SPhilippe Mathieu-Daudé } M48txxInfo;
40*819ce6b2SPhilippe Mathieu-Daudé
41*819ce6b2SPhilippe Mathieu-Daudé typedef struct M48t59State {
42*819ce6b2SPhilippe Mathieu-Daudé /* Hardware parameters */
43*819ce6b2SPhilippe Mathieu-Daudé qemu_irq IRQ;
44*819ce6b2SPhilippe Mathieu-Daudé MemoryRegion iomem;
45*819ce6b2SPhilippe Mathieu-Daudé uint32_t size;
46*819ce6b2SPhilippe Mathieu-Daudé int32_t base_year;
47*819ce6b2SPhilippe Mathieu-Daudé /* RTC management */
48*819ce6b2SPhilippe Mathieu-Daudé time_t time_offset;
49*819ce6b2SPhilippe Mathieu-Daudé time_t stop_time;
50*819ce6b2SPhilippe Mathieu-Daudé /* Alarm & watchdog */
51*819ce6b2SPhilippe Mathieu-Daudé struct tm alarm;
52*819ce6b2SPhilippe Mathieu-Daudé QEMUTimer *alrm_timer;
53*819ce6b2SPhilippe Mathieu-Daudé QEMUTimer *wd_timer;
54*819ce6b2SPhilippe Mathieu-Daudé /* NVRAM storage */
55*819ce6b2SPhilippe Mathieu-Daudé uint8_t *buffer;
56*819ce6b2SPhilippe Mathieu-Daudé /* Model parameters */
57*819ce6b2SPhilippe Mathieu-Daudé uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
58*819ce6b2SPhilippe Mathieu-Daudé /* NVRAM storage */
59*819ce6b2SPhilippe Mathieu-Daudé uint16_t addr;
60*819ce6b2SPhilippe Mathieu-Daudé uint8_t lock;
61*819ce6b2SPhilippe Mathieu-Daudé } M48t59State;
62*819ce6b2SPhilippe Mathieu-Daudé
63*819ce6b2SPhilippe Mathieu-Daudé uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr);
64*819ce6b2SPhilippe Mathieu-Daudé void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val);
65*819ce6b2SPhilippe Mathieu-Daudé void m48t59_reset_common(M48t59State *NVRAM);
66*819ce6b2SPhilippe Mathieu-Daudé void m48t59_realize_common(M48t59State *s, Error **errp);
67*819ce6b2SPhilippe Mathieu-Daudé
m48t59_toggle_lock(M48t59State * NVRAM,int lock)68*819ce6b2SPhilippe Mathieu-Daudé static inline void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
69*819ce6b2SPhilippe Mathieu-Daudé {
70*819ce6b2SPhilippe Mathieu-Daudé NVRAM->lock ^= 1 << lock;
71*819ce6b2SPhilippe Mathieu-Daudé }
72*819ce6b2SPhilippe Mathieu-Daudé
73*819ce6b2SPhilippe Mathieu-Daudé extern const MemoryRegionOps m48t59_io_ops;
74*819ce6b2SPhilippe Mathieu-Daudé
75*819ce6b2SPhilippe Mathieu-Daudé #endif /* HW_M48T59_INTERNAL_H */
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