1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) GPIO (General Purpose Input/Output Controller) 15 * 5) OTP (One-Time Programmable) memory with stored serial number 16 * 6) GEM (Gigabit Ethernet Controller) and management block 17 * 7) DMA (Direct Memory Access Controller) 18 * 8) SPI0 connected to an SPI flash 19 * 9) SPI2 connected to an SD card 20 * 10) PWM0 and PWM1 21 * 22 * This board currently generates devicetree dynamically that indicates at least 23 * two harts and up to five harts. 24 * 25 * This program is free software; you can redistribute it and/or modify it 26 * under the terms and conditions of the GNU General Public License, 27 * version 2 or later, as published by the Free Software Foundation. 28 * 29 * This program is distributed in the hope it will be useful, but WITHOUT 30 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 31 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 32 * more details. 33 * 34 * You should have received a copy of the GNU General Public License along with 35 * this program. If not, see <http://www.gnu.org/licenses/>. 36 */ 37 38 #include "qemu/osdep.h" 39 #include "qemu/error-report.h" 40 #include "qapi/error.h" 41 #include "qapi/visitor.h" 42 #include "hw/boards.h" 43 #include "hw/irq.h" 44 #include "hw/loader.h" 45 #include "hw/sysbus.h" 46 #include "hw/char/serial.h" 47 #include "hw/cpu/cluster.h" 48 #include "hw/misc/unimp.h" 49 #include "hw/sd/sd.h" 50 #include "hw/ssi/ssi.h" 51 #include "target/riscv/cpu.h" 52 #include "hw/riscv/riscv_hart.h" 53 #include "hw/riscv/sifive_u.h" 54 #include "hw/riscv/boot.h" 55 #include "hw/char/sifive_uart.h" 56 #include "hw/intc/riscv_aclint.h" 57 #include "hw/intc/sifive_plic.h" 58 #include "chardev/char.h" 59 #include "net/eth.h" 60 #include "sysemu/device_tree.h" 61 #include "sysemu/runstate.h" 62 #include "sysemu/sysemu.h" 63 64 #include <libfdt.h> 65 66 /* CLINT timebase frequency */ 67 #define CLINT_TIMEBASE_FREQ 1000000 68 69 static const MemMapEntry sifive_u_memmap[] = { 70 [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, 71 [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, 72 [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 }, 73 [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 }, 74 [SIFIVE_U_DEV_PDMA] = { 0x3000000, 0x100000 }, 75 [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 }, 76 [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 }, 77 [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 }, 78 [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 }, 79 [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 }, 80 [SIFIVE_U_DEV_PWM0] = { 0x10020000, 0x1000 }, 81 [SIFIVE_U_DEV_PWM1] = { 0x10021000, 0x1000 }, 82 [SIFIVE_U_DEV_QSPI0] = { 0x10040000, 0x1000 }, 83 [SIFIVE_U_DEV_QSPI2] = { 0x10050000, 0x1000 }, 84 [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 }, 85 [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 }, 86 [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 }, 87 [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 }, 88 [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 }, 89 [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 }, 90 [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 }, 91 }; 92 93 #define OTP_SERIAL 1 94 #define GEM_REVISION 0x10070109 95 96 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, 97 bool is_32_bit) 98 { 99 MachineState *ms = MACHINE(s); 100 uint64_t mem_size = ms->ram_size; 101 void *fdt; 102 int cpu, fdt_size; 103 uint32_t *cells; 104 char *nodename; 105 uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; 106 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 107 static const char * const ethclk_names[2] = { "pclk", "hclk" }; 108 static const char * const clint_compat[2] = { 109 "sifive,clint0", "riscv,clint0" 110 }; 111 static const char * const plic_compat[2] = { 112 "sifive,plic-1.0.0", "riscv,plic0" 113 }; 114 115 if (ms->dtb) { 116 fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size); 117 if (!fdt) { 118 error_report("load_device_tree() failed"); 119 exit(1); 120 } 121 return; 122 } else { 123 fdt = ms->fdt = create_device_tree(&fdt_size); 124 if (!fdt) { 125 error_report("create_device_tree() failed"); 126 exit(1); 127 } 128 } 129 130 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 131 qemu_fdt_setprop_string(fdt, "/", "compatible", 132 "sifive,hifive-unleashed-a00"); 133 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 134 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 135 136 qemu_fdt_add_subnode(fdt, "/soc"); 137 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 138 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 139 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 140 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 141 142 hfclk_phandle = phandle++; 143 nodename = g_strdup_printf("/hfclk"); 144 qemu_fdt_add_subnode(fdt, nodename); 145 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 146 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 147 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 148 SIFIVE_U_HFCLK_FREQ); 149 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 150 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 151 g_free(nodename); 152 153 rtcclk_phandle = phandle++; 154 nodename = g_strdup_printf("/rtcclk"); 155 qemu_fdt_add_subnode(fdt, nodename); 156 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 157 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 158 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 159 SIFIVE_U_RTCCLK_FREQ); 160 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 161 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 162 g_free(nodename); 163 164 nodename = g_strdup_printf("/memory@%lx", 165 (long)memmap[SIFIVE_U_DEV_DRAM].base); 166 qemu_fdt_add_subnode(fdt, nodename); 167 qemu_fdt_setprop_cells(fdt, nodename, "reg", 168 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, 169 mem_size >> 32, mem_size); 170 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 171 g_free(nodename); 172 173 qemu_fdt_add_subnode(fdt, "/cpus"); 174 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 175 CLINT_TIMEBASE_FREQ); 176 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 177 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 178 179 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 180 int cpu_phandle = phandle++; 181 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 182 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 183 char *isa; 184 qemu_fdt_add_subnode(fdt, nodename); 185 /* cpu 0 is the management hart that does not have mmu */ 186 if (cpu != 0) { 187 if (is_32_bit) { 188 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32"); 189 } else { 190 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 191 } 192 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 193 } else { 194 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 195 } 196 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 197 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 198 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 199 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 200 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 201 qemu_fdt_add_subnode(fdt, intc); 202 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 203 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 204 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 205 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 206 g_free(isa); 207 g_free(intc); 208 g_free(nodename); 209 } 210 211 cells = g_new0(uint32_t, ms->smp.cpus * 4); 212 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 213 nodename = 214 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 215 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 216 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 217 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 218 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 219 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 220 g_free(nodename); 221 } 222 nodename = g_strdup_printf("/soc/clint@%lx", 223 (long)memmap[SIFIVE_U_DEV_CLINT].base); 224 qemu_fdt_add_subnode(fdt, nodename); 225 qemu_fdt_setprop_string_array(fdt, nodename, "compatible", 226 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 227 qemu_fdt_setprop_cells(fdt, nodename, "reg", 228 0x0, memmap[SIFIVE_U_DEV_CLINT].base, 229 0x0, memmap[SIFIVE_U_DEV_CLINT].size); 230 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 231 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 232 g_free(cells); 233 g_free(nodename); 234 235 nodename = g_strdup_printf("/soc/otp@%lx", 236 (long)memmap[SIFIVE_U_DEV_OTP].base); 237 qemu_fdt_add_subnode(fdt, nodename); 238 qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); 239 qemu_fdt_setprop_cells(fdt, nodename, "reg", 240 0x0, memmap[SIFIVE_U_DEV_OTP].base, 241 0x0, memmap[SIFIVE_U_DEV_OTP].size); 242 qemu_fdt_setprop_string(fdt, nodename, "compatible", 243 "sifive,fu540-c000-otp"); 244 g_free(nodename); 245 246 prci_phandle = phandle++; 247 nodename = g_strdup_printf("/soc/clock-controller@%lx", 248 (long)memmap[SIFIVE_U_DEV_PRCI].base); 249 qemu_fdt_add_subnode(fdt, nodename); 250 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 251 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 252 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 253 hfclk_phandle, rtcclk_phandle); 254 qemu_fdt_setprop_cells(fdt, nodename, "reg", 255 0x0, memmap[SIFIVE_U_DEV_PRCI].base, 256 0x0, memmap[SIFIVE_U_DEV_PRCI].size); 257 qemu_fdt_setprop_string(fdt, nodename, "compatible", 258 "sifive,fu540-c000-prci"); 259 g_free(nodename); 260 261 plic_phandle = phandle++; 262 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 263 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 264 nodename = 265 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 266 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 267 /* cpu 0 is the management hart that does not have S-mode */ 268 if (cpu == 0) { 269 cells[0] = cpu_to_be32(intc_phandle); 270 cells[1] = cpu_to_be32(IRQ_M_EXT); 271 } else { 272 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 273 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 274 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 275 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 276 } 277 g_free(nodename); 278 } 279 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 280 (long)memmap[SIFIVE_U_DEV_PLIC].base); 281 qemu_fdt_add_subnode(fdt, nodename); 282 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 283 qemu_fdt_setprop_string_array(fdt, nodename, "compatible", 284 (char **)&plic_compat, ARRAY_SIZE(plic_compat)); 285 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 286 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 287 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 288 qemu_fdt_setprop_cells(fdt, nodename, "reg", 289 0x0, memmap[SIFIVE_U_DEV_PLIC].base, 290 0x0, memmap[SIFIVE_U_DEV_PLIC].size); 291 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 292 SIFIVE_U_PLIC_NUM_SOURCES - 1); 293 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 294 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 295 g_free(cells); 296 g_free(nodename); 297 298 gpio_phandle = phandle++; 299 nodename = g_strdup_printf("/soc/gpio@%lx", 300 (long)memmap[SIFIVE_U_DEV_GPIO].base); 301 qemu_fdt_add_subnode(fdt, nodename); 302 qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); 303 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 304 prci_phandle, PRCI_CLK_TLCLK); 305 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2); 306 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 307 qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); 308 qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); 309 qemu_fdt_setprop_cells(fdt, nodename, "reg", 310 0x0, memmap[SIFIVE_U_DEV_GPIO].base, 311 0x0, memmap[SIFIVE_U_DEV_GPIO].size); 312 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, 313 SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, 314 SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, 315 SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9, 316 SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12, 317 SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15); 318 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 319 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0"); 320 g_free(nodename); 321 322 nodename = g_strdup_printf("/gpio-restart"); 323 qemu_fdt_add_subnode(fdt, nodename); 324 qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1); 325 qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); 326 g_free(nodename); 327 328 nodename = g_strdup_printf("/soc/dma@%lx", 329 (long)memmap[SIFIVE_U_DEV_PDMA].base); 330 qemu_fdt_add_subnode(fdt, nodename); 331 qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); 332 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 333 SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, 334 SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, 335 SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); 336 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 337 qemu_fdt_setprop_cells(fdt, nodename, "reg", 338 0x0, memmap[SIFIVE_U_DEV_PDMA].base, 339 0x0, memmap[SIFIVE_U_DEV_PDMA].size); 340 qemu_fdt_setprop_string(fdt, nodename, "compatible", 341 "sifive,fu540-c000-pdma"); 342 g_free(nodename); 343 344 nodename = g_strdup_printf("/soc/cache-controller@%lx", 345 (long)memmap[SIFIVE_U_DEV_L2CC].base); 346 qemu_fdt_add_subnode(fdt, nodename); 347 qemu_fdt_setprop_cells(fdt, nodename, "reg", 348 0x0, memmap[SIFIVE_U_DEV_L2CC].base, 349 0x0, memmap[SIFIVE_U_DEV_L2CC].size); 350 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 351 SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); 352 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 353 qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); 354 qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); 355 qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); 356 qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); 357 qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); 358 qemu_fdt_setprop_string(fdt, nodename, "compatible", 359 "sifive,fu540-c000-ccache"); 360 g_free(nodename); 361 362 nodename = g_strdup_printf("/soc/spi@%lx", 363 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 364 qemu_fdt_add_subnode(fdt, nodename); 365 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 366 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 367 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 368 prci_phandle, PRCI_CLK_TLCLK); 369 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); 370 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 371 qemu_fdt_setprop_cells(fdt, nodename, "reg", 372 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, 373 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); 374 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 375 g_free(nodename); 376 377 nodename = g_strdup_printf("/soc/spi@%lx/mmc@0", 378 (long)memmap[SIFIVE_U_DEV_QSPI2].base); 379 qemu_fdt_add_subnode(fdt, nodename); 380 qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0); 381 qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300); 382 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000); 383 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 384 qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot"); 385 g_free(nodename); 386 387 nodename = g_strdup_printf("/soc/spi@%lx", 388 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 389 qemu_fdt_add_subnode(fdt, nodename); 390 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 391 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 392 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 393 prci_phandle, PRCI_CLK_TLCLK); 394 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); 395 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 396 qemu_fdt_setprop_cells(fdt, nodename, "reg", 397 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, 398 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); 399 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); 400 g_free(nodename); 401 402 nodename = g_strdup_printf("/soc/spi@%lx/flash@0", 403 (long)memmap[SIFIVE_U_DEV_QSPI0].base); 404 qemu_fdt_add_subnode(fdt, nodename); 405 qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4); 406 qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4); 407 qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0); 408 qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000); 409 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0); 410 qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor"); 411 g_free(nodename); 412 413 phy_phandle = phandle++; 414 nodename = g_strdup_printf("/soc/ethernet@%lx", 415 (long)memmap[SIFIVE_U_DEV_GEM].base); 416 qemu_fdt_add_subnode(fdt, nodename); 417 qemu_fdt_setprop_string(fdt, nodename, "compatible", 418 "sifive,fu540-c000-gem"); 419 qemu_fdt_setprop_cells(fdt, nodename, "reg", 420 0x0, memmap[SIFIVE_U_DEV_GEM].base, 421 0x0, memmap[SIFIVE_U_DEV_GEM].size, 422 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, 423 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 424 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 425 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 426 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 427 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 428 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 429 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 430 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 431 qemu_fdt_setprop_string_array(fdt, nodename, "clock-names", 432 (char **)ðclk_names, ARRAY_SIZE(ethclk_names)); 433 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 434 s->soc.gem.conf.macaddr.a, ETH_ALEN); 435 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 436 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 437 438 qemu_fdt_add_subnode(fdt, "/aliases"); 439 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 440 441 g_free(nodename); 442 443 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 444 (long)memmap[SIFIVE_U_DEV_GEM].base); 445 qemu_fdt_add_subnode(fdt, nodename); 446 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 447 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 448 g_free(nodename); 449 450 nodename = g_strdup_printf("/soc/pwm@%lx", 451 (long)memmap[SIFIVE_U_DEV_PWM0].base); 452 qemu_fdt_add_subnode(fdt, nodename); 453 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); 454 qemu_fdt_setprop_cells(fdt, nodename, "reg", 455 0x0, memmap[SIFIVE_U_DEV_PWM0].base, 456 0x0, memmap[SIFIVE_U_DEV_PWM0].size); 457 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 458 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 459 SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1, 460 SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3); 461 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 462 prci_phandle, PRCI_CLK_TLCLK); 463 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); 464 g_free(nodename); 465 466 nodename = g_strdup_printf("/soc/pwm@%lx", 467 (long)memmap[SIFIVE_U_DEV_PWM1].base); 468 qemu_fdt_add_subnode(fdt, nodename); 469 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); 470 qemu_fdt_setprop_cells(fdt, nodename, "reg", 471 0x0, memmap[SIFIVE_U_DEV_PWM1].base, 472 0x0, memmap[SIFIVE_U_DEV_PWM1].size); 473 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 474 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 475 SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1, 476 SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3); 477 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 478 prci_phandle, PRCI_CLK_TLCLK); 479 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); 480 g_free(nodename); 481 482 nodename = g_strdup_printf("/soc/serial@%lx", 483 (long)memmap[SIFIVE_U_DEV_UART1].base); 484 qemu_fdt_add_subnode(fdt, nodename); 485 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 486 qemu_fdt_setprop_cells(fdt, nodename, "reg", 487 0x0, memmap[SIFIVE_U_DEV_UART1].base, 488 0x0, memmap[SIFIVE_U_DEV_UART1].size); 489 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 490 prci_phandle, PRCI_CLK_TLCLK); 491 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 492 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); 493 494 qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); 495 g_free(nodename); 496 497 nodename = g_strdup_printf("/soc/serial@%lx", 498 (long)memmap[SIFIVE_U_DEV_UART0].base); 499 qemu_fdt_add_subnode(fdt, nodename); 500 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 501 qemu_fdt_setprop_cells(fdt, nodename, "reg", 502 0x0, memmap[SIFIVE_U_DEV_UART0].base, 503 0x0, memmap[SIFIVE_U_DEV_UART0].size); 504 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 505 prci_phandle, PRCI_CLK_TLCLK); 506 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 507 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 508 509 qemu_fdt_add_subnode(fdt, "/chosen"); 510 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 511 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 512 513 g_free(nodename); 514 } 515 516 static void sifive_u_machine_reset(void *opaque, int n, int level) 517 { 518 /* gpio pin active low triggers reset */ 519 if (!level) { 520 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 521 } 522 } 523 524 static void sifive_u_machine_init(MachineState *machine) 525 { 526 const MemMapEntry *memmap = sifive_u_memmap; 527 SiFiveUState *s = RISCV_U_MACHINE(machine); 528 MemoryRegion *system_memory = get_system_memory(); 529 MemoryRegion *flash0 = g_new(MemoryRegion, 1); 530 target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 531 target_ulong firmware_end_addr, kernel_start_addr; 532 const char *firmware_name; 533 uint32_t start_addr_hi32 = 0x00000000; 534 int i; 535 uint32_t fdt_load_addr; 536 uint64_t kernel_entry; 537 DriveInfo *dinfo; 538 BlockBackend *blk; 539 DeviceState *flash_dev, *sd_dev, *card_dev; 540 qemu_irq flash_cs, sd_cs; 541 542 /* Initialize SoC */ 543 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); 544 object_property_set_uint(OBJECT(&s->soc), "serial", s->serial, 545 &error_abort); 546 object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, 547 &error_abort); 548 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 549 550 /* register RAM */ 551 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, 552 machine->ram); 553 554 /* register QSPI0 Flash */ 555 memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", 556 memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); 557 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base, 558 flash0); 559 560 /* register gpio-restart */ 561 qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10, 562 qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); 563 564 /* create device tree */ 565 create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); 566 567 if (s->start_in_flash) { 568 /* 569 * If start_in_flash property is given, assign s->msel to a value 570 * that representing booting from QSPI0 memory-mapped flash. 571 * 572 * This also means that when both start_in_flash and msel properties 573 * are given, start_in_flash takes the precedence over msel. 574 * 575 * Note this is to keep backward compatibility not to break existing 576 * users that use start_in_flash property. 577 */ 578 s->msel = MSEL_MEMMAP_QSPI0_FLASH; 579 } 580 581 switch (s->msel) { 582 case MSEL_MEMMAP_QSPI0_FLASH: 583 start_addr = memmap[SIFIVE_U_DEV_FLASH0].base; 584 break; 585 case MSEL_L2LIM_QSPI0_FLASH: 586 case MSEL_L2LIM_QSPI2_SD: 587 start_addr = memmap[SIFIVE_U_DEV_L2LIM].base; 588 break; 589 default: 590 start_addr = memmap[SIFIVE_U_DEV_DRAM].base; 591 break; 592 } 593 594 firmware_name = riscv_default_firmware_name(&s->soc.u_cpus); 595 firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 596 start_addr, NULL); 597 598 if (machine->kernel_filename) { 599 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, 600 firmware_end_addr); 601 602 kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, 603 kernel_start_addr, true, NULL); 604 } else { 605 /* 606 * If dynamic firmware is used, it doesn't know where is the next mode 607 * if kernel argument is not set. 608 */ 609 kernel_entry = 0; 610 } 611 612 fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, 613 memmap[SIFIVE_U_DEV_DRAM].size, 614 machine); 615 riscv_load_fdt(fdt_load_addr, machine->fdt); 616 617 if (!riscv_is_32bit(&s->soc.u_cpus)) { 618 start_addr_hi32 = (uint64_t)start_addr >> 32; 619 } 620 621 /* reset vector */ 622 uint32_t reset_vec[12] = { 623 s->msel, /* MSEL pin state */ 624 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 625 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */ 626 0xf1402573, /* csrr a0, mhartid */ 627 0, 628 0, 629 0x00028067, /* jr t0 */ 630 start_addr, /* start: .dword */ 631 start_addr_hi32, 632 fdt_load_addr, /* fdt_laddr: .dword */ 633 0x00000000, 634 0x00000000, 635 /* fw_dyn: */ 636 }; 637 if (riscv_is_32bit(&s->soc.u_cpus)) { 638 reset_vec[4] = 0x0202a583; /* lw a1, 32(t0) */ 639 reset_vec[5] = 0x0182a283; /* lw t0, 24(t0) */ 640 } else { 641 reset_vec[4] = 0x0202b583; /* ld a1, 32(t0) */ 642 reset_vec[5] = 0x0182b283; /* ld t0, 24(t0) */ 643 } 644 645 646 /* copy in the reset vector in little_endian byte order */ 647 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 648 reset_vec[i] = cpu_to_le32(reset_vec[i]); 649 } 650 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 651 memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); 652 653 riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base, 654 memmap[SIFIVE_U_DEV_MROM].size, 655 sizeof(reset_vec), kernel_entry); 656 657 /* Connect an SPI flash to SPI0 */ 658 flash_dev = qdev_new("is25wp256"); 659 dinfo = drive_get(IF_MTD, 0, 0); 660 if (dinfo) { 661 qdev_prop_set_drive_err(flash_dev, "drive", 662 blk_by_legacy_dinfo(dinfo), 663 &error_fatal); 664 } 665 qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal); 666 667 flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); 668 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs); 669 670 /* Connect an SD card to SPI2 */ 671 sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd"); 672 673 sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0); 674 sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs); 675 676 dinfo = drive_get(IF_SD, 0, 0); 677 blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; 678 card_dev = qdev_new(TYPE_SD_CARD); 679 qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal); 680 qdev_prop_set_bit(card_dev, "spi", true); 681 qdev_realize_and_unref(card_dev, 682 qdev_get_child_bus(sd_dev, "sd-bus"), 683 &error_fatal); 684 } 685 686 static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) 687 { 688 SiFiveUState *s = RISCV_U_MACHINE(obj); 689 690 return s->start_in_flash; 691 } 692 693 static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp) 694 { 695 SiFiveUState *s = RISCV_U_MACHINE(obj); 696 697 s->start_in_flash = value; 698 } 699 700 static void sifive_u_machine_instance_init(Object *obj) 701 { 702 SiFiveUState *s = RISCV_U_MACHINE(obj); 703 704 s->start_in_flash = false; 705 s->msel = 0; 706 object_property_add_uint32_ptr(obj, "msel", &s->msel, 707 OBJ_PROP_FLAG_READWRITE); 708 object_property_set_description(obj, "msel", 709 "Mode Select (MSEL[3:0]) pin state"); 710 711 s->serial = OTP_SERIAL; 712 object_property_add_uint32_ptr(obj, "serial", &s->serial, 713 OBJ_PROP_FLAG_READWRITE); 714 object_property_set_description(obj, "serial", "Board serial number"); 715 } 716 717 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) 718 { 719 MachineClass *mc = MACHINE_CLASS(oc); 720 721 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 722 mc->init = sifive_u_machine_init; 723 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 724 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 725 mc->default_cpu_type = SIFIVE_U_CPU; 726 mc->default_cpus = mc->min_cpus; 727 mc->default_ram_id = "riscv.sifive.u.ram"; 728 729 object_class_property_add_bool(oc, "start-in-flash", 730 sifive_u_machine_get_start_in_flash, 731 sifive_u_machine_set_start_in_flash); 732 object_class_property_set_description(oc, "start-in-flash", 733 "Set on to tell QEMU's ROM to jump to " 734 "flash. Otherwise QEMU will jump to DRAM " 735 "or L2LIM depending on the msel value"); 736 } 737 738 static const TypeInfo sifive_u_machine_typeinfo = { 739 .name = MACHINE_TYPE_NAME("sifive_u"), 740 .parent = TYPE_MACHINE, 741 .class_init = sifive_u_machine_class_init, 742 .instance_init = sifive_u_machine_instance_init, 743 .instance_size = sizeof(SiFiveUState), 744 }; 745 746 static void sifive_u_machine_init_register_types(void) 747 { 748 type_register_static(&sifive_u_machine_typeinfo); 749 } 750 751 type_init(sifive_u_machine_init_register_types) 752 753 static void sifive_u_soc_instance_init(Object *obj) 754 { 755 SiFiveUSoCState *s = RISCV_U_SOC(obj); 756 757 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 758 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 759 760 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 761 TYPE_RISCV_HART_ARRAY); 762 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 763 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 764 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 765 qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); 766 767 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 768 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 769 770 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 771 TYPE_RISCV_HART_ARRAY); 772 773 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); 774 object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); 775 object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); 776 object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); 777 object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); 778 object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI); 779 object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI); 780 object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM); 781 object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM); 782 } 783 784 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) 785 { 786 MachineState *ms = MACHINE(qdev_get_machine()); 787 SiFiveUSoCState *s = RISCV_U_SOC(dev); 788 const MemMapEntry *memmap = sifive_u_memmap; 789 MemoryRegion *system_memory = get_system_memory(); 790 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 791 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 792 char *plic_hart_config; 793 int i, j; 794 NICInfo *nd = &nd_table[0]; 795 796 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 797 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 798 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); 799 qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); 800 801 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal); 802 sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal); 803 /* 804 * The cluster must be realized after the RISC-V hart array container, 805 * as the container's CPU object is only created on realize, and the 806 * CPU must exist and have been parented into the cluster before the 807 * cluster is realized. 808 */ 809 qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 810 qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 811 812 /* boot rom */ 813 memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", 814 memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); 815 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base, 816 mask_rom); 817 818 /* 819 * Add L2-LIM at reset size. 820 * This should be reduced in size as the L2 Cache Controller WayEnable 821 * register is incremented. Unfortunately I don't see a nice (or any) way 822 * to handle reducing or blocking out the L2 LIM while still allowing it 823 * be re returned to all enabled after a reset. For the time being, just 824 * leave it enabled all the time. This won't break anything, but will be 825 * too generous to misbehaving guests. 826 */ 827 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 828 memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); 829 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base, 830 l2lim_mem); 831 832 /* create PLIC hart topology configuration string */ 833 plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); 834 835 /* MMIO */ 836 s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, 837 plic_hart_config, ms->smp.cpus, 0, 838 SIFIVE_U_PLIC_NUM_SOURCES, 839 SIFIVE_U_PLIC_NUM_PRIORITIES, 840 SIFIVE_U_PLIC_PRIORITY_BASE, 841 SIFIVE_U_PLIC_PENDING_BASE, 842 SIFIVE_U_PLIC_ENABLE_BASE, 843 SIFIVE_U_PLIC_ENABLE_STRIDE, 844 SIFIVE_U_PLIC_CONTEXT_BASE, 845 SIFIVE_U_PLIC_CONTEXT_STRIDE, 846 memmap[SIFIVE_U_DEV_PLIC].size); 847 g_free(plic_hart_config); 848 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, 849 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 850 sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, 851 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 852 riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0, 853 ms->smp.cpus, false); 854 riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base + 855 RISCV_ACLINT_SWI_SIZE, 856 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, 857 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 858 CLINT_TIMEBASE_FREQ, false); 859 860 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { 861 return; 862 } 863 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base); 864 865 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); 866 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 867 return; 868 } 869 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base); 870 871 /* Pass all GPIOs to the SOC layer so they are available to the board */ 872 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 873 874 /* Connect GPIO interrupts to the PLIC */ 875 for (i = 0; i < 16; i++) { 876 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 877 qdev_get_gpio_in(DEVICE(s->plic), 878 SIFIVE_U_GPIO_IRQ0 + i)); 879 } 880 881 /* PDMA */ 882 sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 883 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base); 884 885 /* Connect PDMA interrupts to the PLIC */ 886 for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 887 sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 888 qdev_get_gpio_in(DEVICE(s->plic), 889 SIFIVE_U_PDMA_IRQ0 + i)); 890 } 891 892 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); 893 if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { 894 return; 895 } 896 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base); 897 898 /* FIXME use qdev NIC properties instead of nd_table[] */ 899 if (nd->used) { 900 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 901 qdev_set_nic_properties(DEVICE(&s->gem), nd); 902 } 903 object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION, 904 &error_abort); 905 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { 906 return; 907 } 908 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base); 909 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 910 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)); 911 912 /* PWM */ 913 for (i = 0; i < 2; i++) { 914 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) { 915 return; 916 } 917 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0, 918 memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i)); 919 920 /* Connect PWM interrupts to the PLIC */ 921 for (j = 0; j < SIFIVE_PWM_IRQS; j++) { 922 sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j, 923 qdev_get_gpio_in(DEVICE(s->plic), 924 SIFIVE_U_PWM0_IRQ0 + (i * 4) + j)); 925 } 926 } 927 928 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 929 memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size); 930 931 create_unimplemented_device("riscv.sifive.u.dmc", 932 memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); 933 934 create_unimplemented_device("riscv.sifive.u.l2cc", 935 memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); 936 937 sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp); 938 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0, 939 memmap[SIFIVE_U_DEV_QSPI0].base); 940 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0, 941 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ)); 942 sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp); 943 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0, 944 memmap[SIFIVE_U_DEV_QSPI2].base); 945 sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0, 946 qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); 947 } 948 949 static Property sifive_u_soc_props[] = { 950 DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), 951 DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), 952 DEFINE_PROP_END_OF_LIST() 953 }; 954 955 static void sifive_u_soc_class_init(ObjectClass *oc, void *data) 956 { 957 DeviceClass *dc = DEVICE_CLASS(oc); 958 959 device_class_set_props(dc, sifive_u_soc_props); 960 dc->realize = sifive_u_soc_realize; 961 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 962 dc->user_creatable = false; 963 } 964 965 static const TypeInfo sifive_u_soc_type_info = { 966 .name = TYPE_RISCV_U_SOC, 967 .parent = TYPE_DEVICE, 968 .instance_size = sizeof(SiFiveUSoCState), 969 .instance_init = sifive_u_soc_instance_init, 970 .class_init = sifive_u_soc_class_init, 971 }; 972 973 static void sifive_u_soc_register_types(void) 974 { 975 type_register_static(&sifive_u_soc_type_info); 976 } 977 978 type_init(sifive_u_soc_register_types) 979