1 /* 2 * QEMU RISC-V Boot Helper 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "exec/cpu-defs.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/riscv/boot.h" 28 #include "hw/riscv/boot_opensbi.h" 29 #include "elf.h" 30 #include "sysemu/device_tree.h" 31 #include "sysemu/qtest.h" 32 #include "sysemu/kvm.h" 33 #include "sysemu/reset.h" 34 35 #include <libfdt.h> 36 37 bool riscv_is_32bit(RISCVHartArrayState *harts) 38 { 39 return harts->harts[0].env.misa_mxl_max == MXL_RV32; 40 } 41 42 /* 43 * Return the per-socket PLIC hart topology configuration string 44 * (caller must free with g_free()) 45 */ 46 char *riscv_plic_hart_config_string(int hart_count) 47 { 48 g_autofree const char **vals = g_new(const char *, hart_count + 1); 49 int i; 50 51 for (i = 0; i < hart_count; i++) { 52 CPUState *cs = qemu_get_cpu(i); 53 CPURISCVState *env = &RISCV_CPU(cs)->env; 54 55 if (kvm_enabled()) { 56 vals[i] = "S"; 57 } else if (riscv_has_ext(env, RVS)) { 58 vals[i] = "MS"; 59 } else { 60 vals[i] = "M"; 61 } 62 } 63 vals[i] = NULL; 64 65 /* g_strjoinv() obliges us to cast away const here */ 66 return g_strjoinv(",", (char **)vals); 67 } 68 69 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, 70 target_ulong firmware_end_addr) { 71 if (riscv_is_32bit(harts)) { 72 return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); 73 } else { 74 return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); 75 } 76 } 77 78 const char *riscv_default_firmware_name(RISCVHartArrayState *harts) 79 { 80 if (riscv_is_32bit(harts)) { 81 return RISCV32_BIOS_BIN; 82 } 83 84 return RISCV64_BIOS_BIN; 85 } 86 87 static char *riscv_find_firmware(const char *firmware_filename) 88 { 89 char *filename; 90 91 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); 92 if (filename == NULL) { 93 if (!qtest_enabled()) { 94 /* 95 * We only ship OpenSBI binary bios images in the QEMU source. 96 * For machines that use images other than the default bios, 97 * running QEMU test will complain hence let's suppress the error 98 * report for QEMU testing. 99 */ 100 error_report("Unable to load the RISC-V firmware \"%s\"", 101 firmware_filename); 102 exit(1); 103 } 104 } 105 106 return filename; 107 } 108 109 target_ulong riscv_find_and_load_firmware(MachineState *machine, 110 const char *default_machine_firmware, 111 hwaddr firmware_load_addr, 112 symbol_fn_t sym_cb) 113 { 114 char *firmware_filename = NULL; 115 target_ulong firmware_end_addr = firmware_load_addr; 116 117 if ((!machine->firmware) || (!strcmp(machine->firmware, "default"))) { 118 /* 119 * The user didn't specify -bios, or has specified "-bios default". 120 * That means we are going to load the OpenSBI binary included in 121 * the QEMU source. 122 */ 123 firmware_filename = riscv_find_firmware(default_machine_firmware); 124 } else if (strcmp(machine->firmware, "none")) { 125 firmware_filename = riscv_find_firmware(machine->firmware); 126 } 127 128 if (firmware_filename) { 129 /* If not "none" load the firmware */ 130 firmware_end_addr = riscv_load_firmware(firmware_filename, 131 firmware_load_addr, sym_cb); 132 g_free(firmware_filename); 133 } 134 135 return firmware_end_addr; 136 } 137 138 target_ulong riscv_load_firmware(const char *firmware_filename, 139 hwaddr firmware_load_addr, 140 symbol_fn_t sym_cb) 141 { 142 uint64_t firmware_entry, firmware_end; 143 ssize_t firmware_size; 144 145 if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, 146 &firmware_entry, NULL, &firmware_end, NULL, 147 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 148 return firmware_end; 149 } 150 151 firmware_size = load_image_targphys_as(firmware_filename, 152 firmware_load_addr, 153 current_machine->ram_size, NULL); 154 155 if (firmware_size > 0) { 156 return firmware_load_addr + firmware_size; 157 } 158 159 error_report("could not load firmware '%s'", firmware_filename); 160 exit(1); 161 } 162 163 target_ulong riscv_load_kernel(const char *kernel_filename, 164 target_ulong kernel_start_addr, 165 symbol_fn_t sym_cb) 166 { 167 uint64_t kernel_load_base, kernel_entry; 168 169 /* 170 * NB: Use low address not ELF entry point to ensure that the fw_dynamic 171 * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL 172 * behaviour, as well as fw_dynamic with a raw binary, all of which jump to 173 * the (expected) load address load address. This allows kernels to have 174 * separate SBI and ELF entry points (used by FreeBSD, for example). 175 */ 176 if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, 177 NULL, &kernel_load_base, NULL, NULL, 0, 178 EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { 179 return kernel_load_base; 180 } 181 182 if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, 183 NULL, NULL, NULL) > 0) { 184 return kernel_entry; 185 } 186 187 if (load_image_targphys_as(kernel_filename, kernel_start_addr, 188 current_machine->ram_size, NULL) > 0) { 189 return kernel_start_addr; 190 } 191 192 error_report("could not load kernel '%s'", kernel_filename); 193 exit(1); 194 } 195 196 hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, 197 uint64_t kernel_entry, hwaddr *start) 198 { 199 ssize_t size; 200 201 /* 202 * We want to put the initrd far enough into RAM that when the 203 * kernel is uncompressed it will not clobber the initrd. However 204 * on boards without much RAM we must ensure that we still leave 205 * enough room for a decent sized initrd, and on boards with large 206 * amounts of RAM we must avoid the initrd being so far up in RAM 207 * that it is outside lowmem and inaccessible to the kernel. 208 * So for boards with less than 256MB of RAM we put the initrd 209 * halfway into RAM, and for boards with 256MB of RAM or more we put 210 * the initrd at 128MB. 211 */ 212 *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); 213 214 size = load_ramdisk(filename, *start, mem_size - *start); 215 if (size == -1) { 216 size = load_image_targphys(filename, *start, mem_size - *start); 217 if (size == -1) { 218 error_report("could not load ramdisk '%s'", filename); 219 exit(1); 220 } 221 } 222 223 return *start + size; 224 } 225 226 uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) 227 { 228 uint64_t temp, fdt_addr; 229 hwaddr dram_end = dram_base + mem_size; 230 int ret, fdtsize = fdt_totalsize(fdt); 231 232 if (fdtsize <= 0) { 233 error_report("invalid device-tree"); 234 exit(1); 235 } 236 237 /* 238 * We should put fdt as far as possible to avoid kernel/initrd overwriting 239 * its content. But it should be addressable by 32 bit system as well. 240 * Thus, put it at an 2MB aligned address that less than fdt size from the 241 * end of dram or 3GB whichever is lesser. 242 */ 243 temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; 244 fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); 245 246 ret = fdt_pack(fdt); 247 /* Should only fail if we've built a corrupted tree */ 248 g_assert(ret == 0); 249 /* copy in the device tree */ 250 qemu_fdt_dumpdtb(fdt, fdtsize); 251 252 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 253 &address_space_memory); 254 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 255 rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); 256 257 return fdt_addr; 258 } 259 260 void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, 261 hwaddr rom_size, uint32_t reset_vec_size, 262 uint64_t kernel_entry) 263 { 264 struct fw_dynamic_info dinfo; 265 size_t dinfo_len; 266 267 if (sizeof(dinfo.magic) == 4) { 268 dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE); 269 dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION); 270 dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S); 271 dinfo.next_addr = cpu_to_le32(kernel_entry); 272 } else { 273 dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE); 274 dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION); 275 dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S); 276 dinfo.next_addr = cpu_to_le64(kernel_entry); 277 } 278 dinfo.options = 0; 279 dinfo.boot_hart = 0; 280 dinfo_len = sizeof(dinfo); 281 282 /** 283 * copy the dynamic firmware info. This information is specific to 284 * OpenSBI but doesn't break any other firmware as long as they don't 285 * expect any certain value in "a2" register. 286 */ 287 if (dinfo_len > (rom_size - reset_vec_size)) { 288 error_report("not enough space to store dynamic firmware info"); 289 exit(1); 290 } 291 292 rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len, 293 rom_base + reset_vec_size, 294 &address_space_memory); 295 } 296 297 void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, 298 hwaddr start_addr, 299 hwaddr rom_base, hwaddr rom_size, 300 uint64_t kernel_entry, 301 uint64_t fdt_load_addr) 302 { 303 int i; 304 uint32_t start_addr_hi32 = 0x00000000; 305 uint32_t fdt_load_addr_hi32 = 0x00000000; 306 307 if (!riscv_is_32bit(harts)) { 308 start_addr_hi32 = start_addr >> 32; 309 fdt_load_addr_hi32 = fdt_load_addr >> 32; 310 } 311 /* reset vector */ 312 uint32_t reset_vec[10] = { 313 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 314 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 315 0xf1402573, /* csrr a0, mhartid */ 316 0, 317 0, 318 0x00028067, /* jr t0 */ 319 start_addr, /* start: .dword */ 320 start_addr_hi32, 321 fdt_load_addr, /* fdt_laddr: .dword */ 322 fdt_load_addr_hi32, 323 /* fw_dyn: */ 324 }; 325 if (riscv_is_32bit(harts)) { 326 reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */ 327 reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */ 328 } else { 329 reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */ 330 reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ 331 } 332 333 /* copy in the reset vector in little_endian byte order */ 334 for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { 335 reset_vec[i] = cpu_to_le32(reset_vec[i]); 336 } 337 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 338 rom_base, &address_space_memory); 339 riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec), 340 kernel_entry); 341 } 342 343 void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) 344 { 345 CPUState *cs; 346 347 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { 348 RISCVCPU *riscv_cpu = RISCV_CPU(cs); 349 riscv_cpu->env.kernel_addr = kernel_addr; 350 riscv_cpu->env.fdt_addr = fdt_addr; 351 } 352 } 353 354 void riscv_setup_firmware_boot(MachineState *machine) 355 { 356 if (machine->kernel_filename) { 357 FWCfgState *fw_cfg; 358 fw_cfg = fw_cfg_find(); 359 360 assert(fw_cfg); 361 /* 362 * Expose the kernel, the command line, and the initrd in fw_cfg. 363 * We don't process them here at all, it's all left to the 364 * firmware. 365 */ 366 load_image_to_fw_cfg(fw_cfg, 367 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 368 machine->kernel_filename, 369 true); 370 load_image_to_fw_cfg(fw_cfg, 371 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 372 machine->initrd_filename, false); 373 374 if (machine->kernel_cmdline) { 375 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 376 strlen(machine->kernel_cmdline) + 1); 377 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 378 machine->kernel_cmdline); 379 } 380 } 381 } 382