1 /* 2 * Copyright © 2018, 2021 Oracle and/or its affiliates. 3 * 4 * This work is licensed under the terms of the GNU GPL, version 2 or later. 5 * See the COPYING file in the top-level directory. 6 * 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu-common.h" 11 12 #include "hw/remote/proxy.h" 13 #include "hw/pci/pci.h" 14 #include "qapi/error.h" 15 #include "io/channel-util.h" 16 #include "hw/qdev-properties.h" 17 #include "monitor/monitor.h" 18 #include "migration/blocker.h" 19 #include "qemu/sockets.h" 20 #include "hw/remote/mpqemu-link.h" 21 #include "qemu/error-report.h" 22 #include "hw/remote/proxy-memory-listener.h" 23 #include "qom/object.h" 24 #include "qemu/event_notifier.h" 25 #include "sysemu/kvm.h" 26 #include "util/event_notifier-posix.c" 27 28 static void probe_pci_info(PCIDevice *dev, Error **errp); 29 30 static void proxy_intx_update(PCIDevice *pci_dev) 31 { 32 PCIProxyDev *dev = PCI_PROXY_DEV(pci_dev); 33 PCIINTxRoute route; 34 int pin = pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; 35 36 if (dev->virq != -1) { 37 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &dev->intr, dev->virq); 38 dev->virq = -1; 39 } 40 41 route = pci_device_route_intx_to_irq(pci_dev, pin); 42 43 dev->virq = route.irq; 44 45 if (dev->virq != -1) { 46 kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &dev->intr, 47 &dev->resample, dev->virq); 48 } 49 } 50 51 static void setup_irqfd(PCIProxyDev *dev) 52 { 53 PCIDevice *pci_dev = PCI_DEVICE(dev); 54 MPQemuMsg msg; 55 Error *local_err = NULL; 56 57 event_notifier_init(&dev->intr, 0); 58 event_notifier_init(&dev->resample, 0); 59 60 memset(&msg, 0, sizeof(MPQemuMsg)); 61 msg.cmd = MPQEMU_CMD_SET_IRQFD; 62 msg.num_fds = 2; 63 msg.fds[0] = event_notifier_get_fd(&dev->intr); 64 msg.fds[1] = event_notifier_get_fd(&dev->resample); 65 msg.size = 0; 66 67 if (!mpqemu_msg_send(&msg, dev->ioc, &local_err)) { 68 error_report_err(local_err); 69 } 70 71 dev->virq = -1; 72 73 proxy_intx_update(pci_dev); 74 75 pci_device_set_intx_routing_notifier(pci_dev, proxy_intx_update); 76 } 77 78 static void pci_proxy_dev_realize(PCIDevice *device, Error **errp) 79 { 80 ERRP_GUARD(); 81 PCIProxyDev *dev = PCI_PROXY_DEV(device); 82 uint8_t *pci_conf = device->config; 83 int fd; 84 85 if (!dev->fd) { 86 error_setg(errp, "fd parameter not specified for %s", 87 DEVICE(device)->id); 88 return; 89 } 90 91 fd = monitor_fd_param(monitor_cur(), dev->fd, errp); 92 if (fd == -1) { 93 error_prepend(errp, "proxy: unable to parse fd %s: ", dev->fd); 94 return; 95 } 96 97 if (!fd_is_socket(fd)) { 98 error_setg(errp, "proxy: fd %d is not a socket", fd); 99 close(fd); 100 return; 101 } 102 103 dev->ioc = qio_channel_new_fd(fd, errp); 104 105 error_setg(&dev->migration_blocker, "%s does not support migration", 106 TYPE_PCI_PROXY_DEV); 107 migrate_add_blocker(dev->migration_blocker, errp); 108 109 qemu_mutex_init(&dev->io_mutex); 110 qio_channel_set_blocking(dev->ioc, true, NULL); 111 112 pci_conf[PCI_LATENCY_TIMER] = 0xff; 113 pci_conf[PCI_INTERRUPT_PIN] = 0x01; 114 115 proxy_memory_listener_configure(&dev->proxy_listener, dev->ioc); 116 117 setup_irqfd(dev); 118 119 probe_pci_info(PCI_DEVICE(dev), errp); 120 } 121 122 static void pci_proxy_dev_exit(PCIDevice *pdev) 123 { 124 PCIProxyDev *dev = PCI_PROXY_DEV(pdev); 125 126 if (dev->ioc) { 127 qio_channel_close(dev->ioc, NULL); 128 } 129 130 migrate_del_blocker(dev->migration_blocker); 131 132 error_free(dev->migration_blocker); 133 134 proxy_memory_listener_deconfigure(&dev->proxy_listener); 135 136 event_notifier_cleanup(&dev->intr); 137 event_notifier_cleanup(&dev->resample); 138 } 139 140 static void config_op_send(PCIProxyDev *pdev, uint32_t addr, uint32_t *val, 141 int len, unsigned int op) 142 { 143 MPQemuMsg msg = { 0 }; 144 uint64_t ret = -EINVAL; 145 Error *local_err = NULL; 146 147 msg.cmd = op; 148 msg.data.pci_conf_data.addr = addr; 149 msg.data.pci_conf_data.val = (op == MPQEMU_CMD_PCI_CFGWRITE) ? *val : 0; 150 msg.data.pci_conf_data.len = len; 151 msg.size = sizeof(PciConfDataMsg); 152 153 ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); 154 if (local_err) { 155 error_report_err(local_err); 156 } 157 158 if (ret == UINT64_MAX) { 159 error_report("Failed to perform PCI config %s operation", 160 (op == MPQEMU_CMD_PCI_CFGREAD) ? "READ" : "WRITE"); 161 } 162 163 if (op == MPQEMU_CMD_PCI_CFGREAD) { 164 *val = (uint32_t)ret; 165 } 166 } 167 168 static uint32_t pci_proxy_read_config(PCIDevice *d, uint32_t addr, int len) 169 { 170 uint32_t val; 171 172 config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGREAD); 173 174 return val; 175 } 176 177 static void pci_proxy_write_config(PCIDevice *d, uint32_t addr, uint32_t val, 178 int len) 179 { 180 /* 181 * Some of the functions access the copy of remote device's PCI config 182 * space which is cached in the proxy device. Therefore, maintain 183 * it updated. 184 */ 185 pci_default_write_config(d, addr, val, len); 186 187 config_op_send(PCI_PROXY_DEV(d), addr, &val, len, MPQEMU_CMD_PCI_CFGWRITE); 188 } 189 190 static Property proxy_properties[] = { 191 DEFINE_PROP_STRING("fd", PCIProxyDev, fd), 192 DEFINE_PROP_END_OF_LIST(), 193 }; 194 195 static void pci_proxy_dev_class_init(ObjectClass *klass, void *data) 196 { 197 DeviceClass *dc = DEVICE_CLASS(klass); 198 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 199 200 k->realize = pci_proxy_dev_realize; 201 k->exit = pci_proxy_dev_exit; 202 k->config_read = pci_proxy_read_config; 203 k->config_write = pci_proxy_write_config; 204 205 device_class_set_props(dc, proxy_properties); 206 } 207 208 static const TypeInfo pci_proxy_dev_type_info = { 209 .name = TYPE_PCI_PROXY_DEV, 210 .parent = TYPE_PCI_DEVICE, 211 .instance_size = sizeof(PCIProxyDev), 212 .class_init = pci_proxy_dev_class_init, 213 .interfaces = (InterfaceInfo[]) { 214 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 215 { }, 216 }, 217 }; 218 219 static void pci_proxy_dev_register_types(void) 220 { 221 type_register_static(&pci_proxy_dev_type_info); 222 } 223 224 type_init(pci_proxy_dev_register_types) 225 226 static void send_bar_access_msg(PCIProxyDev *pdev, MemoryRegion *mr, 227 bool write, hwaddr addr, uint64_t *val, 228 unsigned size, bool memory) 229 { 230 MPQemuMsg msg = { 0 }; 231 long ret = -EINVAL; 232 Error *local_err = NULL; 233 234 msg.size = sizeof(BarAccessMsg); 235 msg.data.bar_access.addr = mr->addr + addr; 236 msg.data.bar_access.size = size; 237 msg.data.bar_access.memory = memory; 238 239 if (write) { 240 msg.cmd = MPQEMU_CMD_BAR_WRITE; 241 msg.data.bar_access.val = *val; 242 } else { 243 msg.cmd = MPQEMU_CMD_BAR_READ; 244 } 245 246 ret = mpqemu_msg_send_and_await_reply(&msg, pdev, &local_err); 247 if (local_err) { 248 error_report_err(local_err); 249 } 250 251 if (!write) { 252 *val = ret; 253 } 254 } 255 256 static void proxy_bar_write(void *opaque, hwaddr addr, uint64_t val, 257 unsigned size) 258 { 259 ProxyMemoryRegion *pmr = opaque; 260 261 send_bar_access_msg(pmr->dev, &pmr->mr, true, addr, &val, size, 262 pmr->memory); 263 } 264 265 static uint64_t proxy_bar_read(void *opaque, hwaddr addr, unsigned size) 266 { 267 ProxyMemoryRegion *pmr = opaque; 268 uint64_t val; 269 270 send_bar_access_msg(pmr->dev, &pmr->mr, false, addr, &val, size, 271 pmr->memory); 272 273 return val; 274 } 275 276 const MemoryRegionOps proxy_mr_ops = { 277 .read = proxy_bar_read, 278 .write = proxy_bar_write, 279 .endianness = DEVICE_NATIVE_ENDIAN, 280 .impl = { 281 .min_access_size = 1, 282 .max_access_size = 8, 283 }, 284 }; 285 286 static void probe_pci_info(PCIDevice *dev, Error **errp) 287 { 288 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 289 uint32_t orig_val, new_val, base_class, val; 290 PCIProxyDev *pdev = PCI_PROXY_DEV(dev); 291 DeviceClass *dc = DEVICE_CLASS(pc); 292 uint8_t type; 293 int i, size; 294 295 config_op_send(pdev, PCI_VENDOR_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 296 pc->vendor_id = (uint16_t)val; 297 298 config_op_send(pdev, PCI_DEVICE_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 299 pc->device_id = (uint16_t)val; 300 301 config_op_send(pdev, PCI_CLASS_DEVICE, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 302 pc->class_id = (uint16_t)val; 303 304 config_op_send(pdev, PCI_SUBSYSTEM_ID, &val, 2, MPQEMU_CMD_PCI_CFGREAD); 305 pc->subsystem_id = (uint16_t)val; 306 307 base_class = pc->class_id >> 4; 308 switch (base_class) { 309 case PCI_BASE_CLASS_BRIDGE: 310 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 311 break; 312 case PCI_BASE_CLASS_STORAGE: 313 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 314 break; 315 case PCI_BASE_CLASS_NETWORK: 316 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 317 break; 318 case PCI_BASE_CLASS_INPUT: 319 set_bit(DEVICE_CATEGORY_INPUT, dc->categories); 320 break; 321 case PCI_BASE_CLASS_DISPLAY: 322 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); 323 break; 324 case PCI_BASE_CLASS_PROCESSOR: 325 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 326 break; 327 default: 328 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 329 break; 330 } 331 332 for (i = 0; i < PCI_NUM_REGIONS; i++) { 333 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4, 334 MPQEMU_CMD_PCI_CFGREAD); 335 new_val = 0xffffffff; 336 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, 337 MPQEMU_CMD_PCI_CFGWRITE); 338 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &new_val, 4, 339 MPQEMU_CMD_PCI_CFGREAD); 340 size = (~(new_val & 0xFFFFFFF0)) + 1; 341 config_op_send(pdev, PCI_BASE_ADDRESS_0 + (4 * i), &orig_val, 4, 342 MPQEMU_CMD_PCI_CFGWRITE); 343 type = (new_val & 0x1) ? 344 PCI_BASE_ADDRESS_SPACE_IO : PCI_BASE_ADDRESS_SPACE_MEMORY; 345 346 if (size) { 347 g_autofree char *name; 348 pdev->region[i].dev = pdev; 349 pdev->region[i].present = true; 350 if (type == PCI_BASE_ADDRESS_SPACE_MEMORY) { 351 pdev->region[i].memory = true; 352 } 353 name = g_strdup_printf("bar-region-%d", i); 354 memory_region_init_io(&pdev->region[i].mr, OBJECT(pdev), 355 &proxy_mr_ops, &pdev->region[i], 356 name, size); 357 pci_register_bar(dev, i, type, &pdev->region[i].mr); 358 } 359 } 360 } 361