1 /* 2 * sPAPR CPU core device, acts as container of CPU thread devices. 3 * 4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com> 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2 or later. 7 * See the COPYING file in the top-level directory. 8 */ 9 #include "hw/cpu/core.h" 10 #include "hw/ppc/spapr_cpu_core.h" 11 #include "target/ppc/cpu.h" 12 #include "hw/ppc/spapr.h" 13 #include "hw/boards.h" 14 #include "qapi/error.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/kvm.h" 17 #include "target/ppc/kvm_ppc.h" 18 #include "hw/ppc/ppc.h" 19 #include "target/ppc/mmu-hash64.h" 20 #include "sysemu/numa.h" 21 #include "qemu/error-report.h" 22 23 static void spapr_cpu_reset(void *opaque) 24 { 25 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 26 PowerPCCPU *cpu = opaque; 27 CPUState *cs = CPU(cpu); 28 CPUPPCState *env = &cpu->env; 29 30 cpu_reset(cs); 31 32 /* All CPUs start halted. CPU0 is unhalted from the machine level 33 * reset code and the rest are explicitly started up by the guest 34 * using an RTAS call */ 35 cs->halted = 1; 36 37 env->spr[SPR_HIOR] = 0; 38 39 /* 40 * This is a hack for the benefit of KVM PR - it abuses the SDR1 41 * slot in kvm_sregs to communicate the userspace address of the 42 * HPT 43 */ 44 if (kvm_enabled()) { 45 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab 46 | (spapr->htab_shift - 18); 47 if (kvmppc_put_books_sregs(cpu) < 0) { 48 error_report("Unable to update SDR1 in KVM"); 49 exit(1); 50 } 51 } 52 } 53 54 static void spapr_cpu_destroy(PowerPCCPU *cpu) 55 { 56 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 57 58 xics_cpu_destroy(XICS_FABRIC(spapr), cpu); 59 qemu_unregister_reset(spapr_cpu_reset, cpu); 60 } 61 62 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, 63 Error **errp) 64 { 65 CPUPPCState *env = &cpu->env; 66 67 /* Set time-base frequency to 512 MHz */ 68 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ); 69 70 /* Enable PAPR mode in TCG or KVM */ 71 cpu_ppc_set_papr(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); 72 73 if (cpu->max_compat) { 74 Error *local_err = NULL; 75 76 ppc_set_compat(cpu, cpu->max_compat, &local_err); 77 if (local_err) { 78 error_propagate(errp, local_err); 79 return; 80 } 81 } 82 83 qemu_register_reset(spapr_cpu_reset, cpu); 84 spapr_cpu_reset(cpu); 85 } 86 87 /* 88 * Return the sPAPR CPU core type for @model which essentially is the CPU 89 * model specified with -cpu cmdline option. 90 */ 91 char *spapr_get_cpu_core_type(const char *model) 92 { 93 char *core_type; 94 gchar **model_pieces = g_strsplit(model, ",", 2); 95 96 core_type = g_strdup_printf("%s-%s", model_pieces[0], TYPE_SPAPR_CPU_CORE); 97 98 /* Check whether it exists or whether we have to look up an alias name */ 99 if (!object_class_by_name(core_type)) { 100 const char *realmodel; 101 102 g_free(core_type); 103 core_type = NULL; 104 realmodel = ppc_cpu_lookup_alias(model_pieces[0]); 105 if (realmodel) { 106 core_type = spapr_get_cpu_core_type(realmodel); 107 } 108 } 109 110 g_strfreev(model_pieces); 111 return core_type; 112 } 113 114 static void spapr_cpu_core_unrealizefn(DeviceState *dev, Error **errp) 115 { 116 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 117 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 118 const char *typename = object_class_get_name(scc->cpu_class); 119 size_t size = object_type_get_instance_size(typename); 120 CPUCore *cc = CPU_CORE(dev); 121 int i; 122 123 for (i = 0; i < cc->nr_threads; i++) { 124 void *obj = sc->threads + i * size; 125 DeviceState *dev = DEVICE(obj); 126 CPUState *cs = CPU(dev); 127 PowerPCCPU *cpu = POWERPC_CPU(cs); 128 129 spapr_cpu_destroy(cpu); 130 object_unparent(cpu->intc); 131 cpu_remove_sync(cs); 132 object_unparent(obj); 133 } 134 g_free(sc->threads); 135 } 136 137 static void spapr_cpu_core_realize_child(Object *child, Error **errp) 138 { 139 Error *local_err = NULL; 140 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 141 CPUState *cs = CPU(child); 142 PowerPCCPU *cpu = POWERPC_CPU(cs); 143 Object *obj; 144 145 obj = object_new(spapr->icp_type); 146 object_property_add_child(OBJECT(cpu), "icp", obj, &error_abort); 147 object_unref(obj); 148 object_property_add_const_link(obj, "xics", OBJECT(spapr), &error_abort); 149 object_property_set_bool(obj, true, "realized", &local_err); 150 if (local_err) { 151 goto error; 152 } 153 154 object_property_set_bool(child, true, "realized", &local_err); 155 if (local_err) { 156 goto error; 157 } 158 159 spapr_cpu_init(spapr, cpu, &local_err); 160 if (local_err) { 161 goto error; 162 } 163 164 xics_cpu_setup(XICS_FABRIC(spapr), cpu, ICP(obj)); 165 return; 166 167 error: 168 object_unparent(obj); 169 error_propagate(errp, local_err); 170 } 171 172 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) 173 { 174 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 175 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(dev)); 176 CPUCore *cc = CPU_CORE(OBJECT(dev)); 177 const char *typename = object_class_get_name(scc->cpu_class); 178 size_t size = object_type_get_instance_size(typename); 179 Error *local_err = NULL; 180 void *obj; 181 int i, j; 182 183 sc->threads = g_malloc0(size * cc->nr_threads); 184 for (i = 0; i < cc->nr_threads; i++) { 185 char id[32]; 186 CPUState *cs; 187 PowerPCCPU *cpu; 188 189 obj = sc->threads + i * size; 190 191 object_initialize(obj, size, typename); 192 cs = CPU(obj); 193 cpu = POWERPC_CPU(cs); 194 cs->cpu_index = cc->core_id + i; 195 196 /* Set NUMA node for the threads belonged to core */ 197 cpu->node_id = sc->node_id; 198 199 snprintf(id, sizeof(id), "thread[%d]", i); 200 object_property_add_child(OBJECT(sc), id, obj, &local_err); 201 if (local_err) { 202 goto err; 203 } 204 object_unref(obj); 205 } 206 207 for (j = 0; j < cc->nr_threads; j++) { 208 obj = sc->threads + j * size; 209 210 spapr_cpu_core_realize_child(obj, &local_err); 211 if (local_err) { 212 goto err; 213 } 214 } 215 return; 216 217 err: 218 while (--i >= 0) { 219 obj = sc->threads + i * size; 220 object_unparent(obj); 221 } 222 g_free(sc->threads); 223 error_propagate(errp, local_err); 224 } 225 226 static const char *spapr_core_models[] = { 227 /* 970 */ 228 "970_v2.2", 229 230 /* 970MP variants */ 231 "970MP_v1.0", 232 "970mp_v1.0", 233 "970MP_v1.1", 234 "970mp_v1.1", 235 236 /* POWER5+ */ 237 "POWER5+_v2.1", 238 239 /* POWER7 */ 240 "POWER7_v2.3", 241 242 /* POWER7+ */ 243 "POWER7+_v2.1", 244 245 /* POWER8 */ 246 "POWER8_v2.0", 247 248 /* POWER8E */ 249 "POWER8E_v2.1", 250 251 /* POWER8NVL */ 252 "POWER8NVL_v1.0", 253 254 /* POWER9 */ 255 "POWER9_v1.0", 256 }; 257 258 static Property spapr_cpu_core_properties[] = { 259 DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID), 260 DEFINE_PROP_END_OF_LIST() 261 }; 262 263 void spapr_cpu_core_class_init(ObjectClass *oc, void *data) 264 { 265 DeviceClass *dc = DEVICE_CLASS(oc); 266 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc); 267 268 dc->realize = spapr_cpu_core_realize; 269 dc->unrealize = spapr_cpu_core_unrealizefn; 270 dc->props = spapr_cpu_core_properties; 271 scc->cpu_class = cpu_class_by_name(TYPE_POWERPC_CPU, data); 272 g_assert(scc->cpu_class); 273 } 274 275 static const TypeInfo spapr_cpu_core_type_info = { 276 .name = TYPE_SPAPR_CPU_CORE, 277 .parent = TYPE_CPU_CORE, 278 .abstract = true, 279 .instance_size = sizeof(sPAPRCPUCore), 280 .class_size = sizeof(sPAPRCPUCoreClass), 281 }; 282 283 static void spapr_cpu_core_register_types(void) 284 { 285 int i; 286 287 type_register_static(&spapr_cpu_core_type_info); 288 289 for (i = 0; i < ARRAY_SIZE(spapr_core_models); i++) { 290 TypeInfo type_info = { 291 .parent = TYPE_SPAPR_CPU_CORE, 292 .instance_size = sizeof(sPAPRCPUCore), 293 .class_init = spapr_cpu_core_class_init, 294 .class_data = (void *) spapr_core_models[i], 295 }; 296 297 type_info.name = g_strdup_printf("%s-" TYPE_SPAPR_CPU_CORE, 298 spapr_core_models[i]); 299 type_register(&type_info); 300 g_free((void *)type_info.name); 301 } 302 } 303 304 type_init(spapr_cpu_core_register_types) 305