1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "hw/hw.h" 30 #include "hw/fw-path-provider.h" 31 #include "elf.h" 32 #include "net/net.h" 33 #include "sysemu/block-backend.h" 34 #include "sysemu/cpus.h" 35 #include "sysemu/kvm.h" 36 #include "kvm_ppc.h" 37 #include "mmu-hash64.h" 38 #include "qom/cpu.h" 39 40 #include "hw/boards.h" 41 #include "hw/ppc/ppc.h" 42 #include "hw/loader.h" 43 44 #include "hw/ppc/spapr.h" 45 #include "hw/ppc/spapr_vio.h" 46 #include "hw/pci-host/spapr.h" 47 #include "hw/ppc/xics.h" 48 #include "hw/pci/msi.h" 49 50 #include "hw/pci/pci.h" 51 #include "hw/scsi/scsi.h" 52 #include "hw/virtio/virtio-scsi.h" 53 54 #include "exec/address-spaces.h" 55 #include "hw/usb.h" 56 #include "qemu/config-file.h" 57 #include "qemu/error-report.h" 58 #include "trace.h" 59 #include "hw/nmi.h" 60 61 #include "hw/compat.h" 62 63 #include <libfdt.h> 64 65 /* SLOF memory layout: 66 * 67 * SLOF raw image loaded at 0, copies its romfs right below the flat 68 * device-tree, then position SLOF itself 31M below that 69 * 70 * So we set FW_OVERHEAD to 40MB which should account for all of that 71 * and more 72 * 73 * We load our kernel at 4M, leaving space for SLOF initial image 74 */ 75 #define FDT_MAX_SIZE 0x40000 76 #define RTAS_MAX_SIZE 0x10000 77 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 78 #define FW_MAX_SIZE 0x400000 79 #define FW_FILE_NAME "slof.bin" 80 #define FW_OVERHEAD 0x2800000 81 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 82 83 #define MIN_RMA_SLOF 128UL 84 85 #define TIMEBASE_FREQ 512000000ULL 86 87 #define MAX_CPUS 255 88 89 #define PHANDLE_XICP 0x00001111 90 91 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 92 93 typedef struct sPAPRMachineState sPAPRMachineState; 94 95 #define TYPE_SPAPR_MACHINE "spapr-machine" 96 #define SPAPR_MACHINE(obj) \ 97 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 98 99 /** 100 * sPAPRMachineState: 101 */ 102 struct sPAPRMachineState { 103 /*< private >*/ 104 MachineState parent_obj; 105 106 /*< public >*/ 107 char *kvm_type; 108 }; 109 110 sPAPREnvironment *spapr; 111 112 static XICSState *try_create_xics(const char *type, int nr_servers, 113 int nr_irqs) 114 { 115 DeviceState *dev; 116 117 dev = qdev_create(NULL, type); 118 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 119 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 120 if (qdev_init(dev) < 0) { 121 return NULL; 122 } 123 124 return XICS_COMMON(dev); 125 } 126 127 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 128 { 129 XICSState *icp = NULL; 130 131 if (kvm_enabled()) { 132 QemuOpts *machine_opts = qemu_get_machine_opts(); 133 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 134 "kernel_irqchip", true); 135 bool irqchip_required = qemu_opt_get_bool(machine_opts, 136 "kernel_irqchip", false); 137 if (irqchip_allowed) { 138 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 139 } 140 141 if (irqchip_required && !icp) { 142 perror("Failed to create in-kernel XICS\n"); 143 abort(); 144 } 145 } 146 147 if (!icp) { 148 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 149 } 150 151 if (!icp) { 152 perror("Failed to create XICS\n"); 153 abort(); 154 } 155 156 return icp; 157 } 158 159 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 160 int smt_threads) 161 { 162 int i, ret = 0; 163 uint32_t servers_prop[smt_threads]; 164 uint32_t gservers_prop[smt_threads * 2]; 165 int index = ppc_get_vcpu_dt_id(cpu); 166 167 if (cpu->cpu_version) { 168 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 169 if (ret < 0) { 170 return ret; 171 } 172 } 173 174 /* Build interrupt servers and gservers properties */ 175 for (i = 0; i < smt_threads; i++) { 176 servers_prop[i] = cpu_to_be32(index + i); 177 /* Hack, direct the group queues back to cpu 0 */ 178 gservers_prop[i*2] = cpu_to_be32(index + i); 179 gservers_prop[i*2 + 1] = 0; 180 } 181 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 182 servers_prop, sizeof(servers_prop)); 183 if (ret < 0) { 184 return ret; 185 } 186 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 187 gservers_prop, sizeof(gservers_prop)); 188 189 return ret; 190 } 191 192 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 193 { 194 int ret = 0, offset, cpus_offset; 195 CPUState *cs; 196 char cpu_model[32]; 197 int smt = kvmppc_smt_threads(); 198 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 199 200 CPU_FOREACH(cs) { 201 PowerPCCPU *cpu = POWERPC_CPU(cs); 202 DeviceClass *dc = DEVICE_GET_CLASS(cs); 203 int index = ppc_get_vcpu_dt_id(cpu); 204 uint32_t associativity[] = {cpu_to_be32(0x5), 205 cpu_to_be32(0x0), 206 cpu_to_be32(0x0), 207 cpu_to_be32(0x0), 208 cpu_to_be32(cs->numa_node), 209 cpu_to_be32(index)}; 210 211 if ((index % smt) != 0) { 212 continue; 213 } 214 215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 216 217 cpus_offset = fdt_path_offset(fdt, "/cpus"); 218 if (cpus_offset < 0) { 219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 220 "cpus"); 221 if (cpus_offset < 0) { 222 return cpus_offset; 223 } 224 } 225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 226 if (offset < 0) { 227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 228 if (offset < 0) { 229 return offset; 230 } 231 } 232 233 if (nb_numa_nodes > 1) { 234 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 235 sizeof(associativity)); 236 if (ret < 0) { 237 return ret; 238 } 239 } 240 241 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 242 pft_size_prop, sizeof(pft_size_prop)); 243 if (ret < 0) { 244 return ret; 245 } 246 247 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 248 ppc_get_compat_smt_threads(cpu)); 249 if (ret < 0) { 250 return ret; 251 } 252 } 253 return ret; 254 } 255 256 257 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 258 size_t maxsize) 259 { 260 size_t maxcells = maxsize / sizeof(uint32_t); 261 int i, j, count; 262 uint32_t *p = prop; 263 264 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 265 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 266 267 if (!sps->page_shift) { 268 break; 269 } 270 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 271 if (sps->enc[count].page_shift == 0) { 272 break; 273 } 274 } 275 if ((p - prop) >= (maxcells - 3 - count * 2)) { 276 break; 277 } 278 *(p++) = cpu_to_be32(sps->page_shift); 279 *(p++) = cpu_to_be32(sps->slb_enc); 280 *(p++) = cpu_to_be32(count); 281 for (j = 0; j < count; j++) { 282 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 283 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 284 } 285 } 286 287 return (p - prop) * sizeof(uint32_t); 288 } 289 290 static hwaddr spapr_node0_size(void) 291 { 292 if (nb_numa_nodes) { 293 int i; 294 for (i = 0; i < nb_numa_nodes; ++i) { 295 if (numa_info[i].node_mem) { 296 return MIN(pow2floor(numa_info[i].node_mem), ram_size); 297 } 298 } 299 } 300 return ram_size; 301 } 302 303 #define _FDT(exp) \ 304 do { \ 305 int ret = (exp); \ 306 if (ret < 0) { \ 307 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 308 #exp, fdt_strerror(ret)); \ 309 exit(1); \ 310 } \ 311 } while (0) 312 313 static void add_str(GString *s, const gchar *s1) 314 { 315 g_string_append_len(s, s1, strlen(s1) + 1); 316 } 317 318 static void *spapr_create_fdt_skel(hwaddr initrd_base, 319 hwaddr initrd_size, 320 hwaddr kernel_size, 321 bool little_endian, 322 const char *boot_device, 323 const char *kernel_cmdline, 324 uint32_t epow_irq) 325 { 326 void *fdt; 327 CPUState *cs; 328 uint32_t start_prop = cpu_to_be32(initrd_base); 329 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 330 GString *hypertas = g_string_sized_new(256); 331 GString *qemu_hypertas = g_string_sized_new(256); 332 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 333 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 334 int smt = kvmppc_smt_threads(); 335 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 336 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 337 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 338 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 339 char *buf; 340 341 add_str(hypertas, "hcall-pft"); 342 add_str(hypertas, "hcall-term"); 343 add_str(hypertas, "hcall-dabr"); 344 add_str(hypertas, "hcall-interrupt"); 345 add_str(hypertas, "hcall-tce"); 346 add_str(hypertas, "hcall-vio"); 347 add_str(hypertas, "hcall-splpar"); 348 add_str(hypertas, "hcall-bulk"); 349 add_str(hypertas, "hcall-set-mode"); 350 add_str(qemu_hypertas, "hcall-memop1"); 351 352 fdt = g_malloc0(FDT_MAX_SIZE); 353 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 354 355 if (kernel_size) { 356 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 357 } 358 if (initrd_size) { 359 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 360 } 361 _FDT((fdt_finish_reservemap(fdt))); 362 363 /* Root node */ 364 _FDT((fdt_begin_node(fdt, ""))); 365 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 366 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 367 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 368 369 /* 370 * Add info to guest to indentify which host is it being run on 371 * and what is the uuid of the guest 372 */ 373 if (kvmppc_get_host_model(&buf)) { 374 _FDT((fdt_property_string(fdt, "host-model", buf))); 375 g_free(buf); 376 } 377 if (kvmppc_get_host_serial(&buf)) { 378 _FDT((fdt_property_string(fdt, "host-serial", buf))); 379 g_free(buf); 380 } 381 382 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 383 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 384 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 385 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 386 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 387 qemu_uuid[14], qemu_uuid[15]); 388 389 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 390 g_free(buf); 391 392 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 393 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 394 395 /* /chosen */ 396 _FDT((fdt_begin_node(fdt, "chosen"))); 397 398 /* Set Form1_affinity */ 399 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 400 401 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 402 _FDT((fdt_property(fdt, "linux,initrd-start", 403 &start_prop, sizeof(start_prop)))); 404 _FDT((fdt_property(fdt, "linux,initrd-end", 405 &end_prop, sizeof(end_prop)))); 406 if (kernel_size) { 407 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 408 cpu_to_be64(kernel_size) }; 409 410 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 411 if (little_endian) { 412 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 413 } 414 } 415 if (boot_device) { 416 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 417 } 418 if (boot_menu) { 419 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 420 } 421 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 422 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 423 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 424 425 _FDT((fdt_end_node(fdt))); 426 427 /* cpus */ 428 _FDT((fdt_begin_node(fdt, "cpus"))); 429 430 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 431 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 432 433 CPU_FOREACH(cs) { 434 PowerPCCPU *cpu = POWERPC_CPU(cs); 435 CPUPPCState *env = &cpu->env; 436 DeviceClass *dc = DEVICE_GET_CLASS(cs); 437 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 438 int index = ppc_get_vcpu_dt_id(cpu); 439 char *nodename; 440 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 441 0xffffffff, 0xffffffff}; 442 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 443 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 444 uint32_t page_sizes_prop[64]; 445 size_t page_sizes_prop_size; 446 447 if ((index % smt) != 0) { 448 continue; 449 } 450 451 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 452 453 _FDT((fdt_begin_node(fdt, nodename))); 454 455 g_free(nodename); 456 457 _FDT((fdt_property_cell(fdt, "reg", index))); 458 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 459 460 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 461 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 462 env->dcache_line_size))); 463 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 464 env->dcache_line_size))); 465 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 466 env->icache_line_size))); 467 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 468 env->icache_line_size))); 469 470 if (pcc->l1_dcache_size) { 471 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 472 } else { 473 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 474 } 475 if (pcc->l1_icache_size) { 476 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 477 } else { 478 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 479 } 480 481 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 482 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 483 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 484 _FDT((fdt_property_string(fdt, "status", "okay"))); 485 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 486 487 if (env->spr_cb[SPR_PURR].oea_read) { 488 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 489 } 490 491 if (env->mmu_model & POWERPC_MMU_1TSEG) { 492 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 493 segs, sizeof(segs)))); 494 } 495 496 /* Advertise VMX/VSX (vector extensions) if available 497 * 0 / no property == no vector extensions 498 * 1 == VMX / Altivec available 499 * 2 == VSX available */ 500 if (env->insns_flags & PPC_ALTIVEC) { 501 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 502 503 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 504 } 505 506 /* Advertise DFP (Decimal Floating Point) if available 507 * 0 / no property == no DFP 508 * 1 == DFP available */ 509 if (env->insns_flags2 & PPC2_DFP) { 510 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 511 } 512 513 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 514 sizeof(page_sizes_prop)); 515 if (page_sizes_prop_size) { 516 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 517 page_sizes_prop, page_sizes_prop_size))); 518 } 519 520 _FDT((fdt_property_cell(fdt, "ibm,chip-id", 521 cs->cpu_index / cpus_per_socket))); 522 523 _FDT((fdt_end_node(fdt))); 524 } 525 526 _FDT((fdt_end_node(fdt))); 527 528 /* RTAS */ 529 _FDT((fdt_begin_node(fdt, "rtas"))); 530 531 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 532 add_str(hypertas, "hcall-multi-tce"); 533 } 534 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 535 hypertas->len))); 536 g_string_free(hypertas, TRUE); 537 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 538 qemu_hypertas->len))); 539 g_string_free(qemu_hypertas, TRUE); 540 541 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 542 refpoints, sizeof(refpoints)))); 543 544 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 545 546 /* 547 * According to PAPR, rtas ibm,os-term does not guarantee a return 548 * back to the guest cpu. 549 * 550 * While an additional ibm,extended-os-term property indicates that 551 * rtas call return will always occur. Set this property. 552 */ 553 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 554 555 _FDT((fdt_end_node(fdt))); 556 557 /* interrupt controller */ 558 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 559 560 _FDT((fdt_property_string(fdt, "device_type", 561 "PowerPC-External-Interrupt-Presentation"))); 562 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 563 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 564 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 565 interrupt_server_ranges_prop, 566 sizeof(interrupt_server_ranges_prop)))); 567 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 568 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 569 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 570 571 _FDT((fdt_end_node(fdt))); 572 573 /* vdevice */ 574 _FDT((fdt_begin_node(fdt, "vdevice"))); 575 576 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 577 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 578 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 579 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 580 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 581 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 582 583 _FDT((fdt_end_node(fdt))); 584 585 /* event-sources */ 586 spapr_events_fdt_skel(fdt, epow_irq); 587 588 /* /hypervisor node */ 589 if (kvm_enabled()) { 590 uint8_t hypercall[16]; 591 592 /* indicate KVM hypercall interface */ 593 _FDT((fdt_begin_node(fdt, "hypervisor"))); 594 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 595 if (kvmppc_has_cap_fixup_hcalls()) { 596 /* 597 * Older KVM versions with older guest kernels were broken with the 598 * magic page, don't allow the guest to map it. 599 */ 600 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 601 sizeof(hypercall)); 602 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 603 sizeof(hypercall)))); 604 } 605 _FDT((fdt_end_node(fdt))); 606 } 607 608 _FDT((fdt_end_node(fdt))); /* close root node */ 609 _FDT((fdt_finish(fdt))); 610 611 return fdt; 612 } 613 614 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size) 615 { 616 void *fdt, *fdt_skel; 617 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 618 619 size -= sizeof(hdr); 620 621 /* Create sceleton */ 622 fdt_skel = g_malloc0(size); 623 _FDT((fdt_create(fdt_skel, size))); 624 _FDT((fdt_begin_node(fdt_skel, ""))); 625 _FDT((fdt_end_node(fdt_skel))); 626 _FDT((fdt_finish(fdt_skel))); 627 fdt = g_malloc0(size); 628 _FDT((fdt_open_into(fdt_skel, fdt, size))); 629 g_free(fdt_skel); 630 631 /* Fix skeleton up */ 632 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 633 634 /* Pack resulting tree */ 635 _FDT((fdt_pack(fdt))); 636 637 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 638 trace_spapr_cas_failed(size); 639 return -1; 640 } 641 642 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 643 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 644 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 645 g_free(fdt); 646 647 return 0; 648 } 649 650 static void spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 651 hwaddr size) 652 { 653 uint32_t associativity[] = { 654 cpu_to_be32(0x4), /* length */ 655 cpu_to_be32(0x0), cpu_to_be32(0x0), 656 cpu_to_be32(0x0), cpu_to_be32(nodeid) 657 }; 658 char mem_name[32]; 659 uint64_t mem_reg_property[2]; 660 int off; 661 662 mem_reg_property[0] = cpu_to_be64(start); 663 mem_reg_property[1] = cpu_to_be64(size); 664 665 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 666 off = fdt_add_subnode(fdt, 0, mem_name); 667 _FDT(off); 668 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 669 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 670 sizeof(mem_reg_property)))); 671 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 672 sizeof(associativity)))); 673 } 674 675 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 676 { 677 hwaddr mem_start, node_size; 678 int i, nb_nodes = nb_numa_nodes; 679 NodeInfo *nodes = numa_info; 680 NodeInfo ramnode; 681 682 /* No NUMA nodes, assume there is just one node with whole RAM */ 683 if (!nb_numa_nodes) { 684 nb_nodes = 1; 685 ramnode.node_mem = ram_size; 686 nodes = &ramnode; 687 } 688 689 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 690 if (!nodes[i].node_mem) { 691 continue; 692 } 693 if (mem_start >= ram_size) { 694 node_size = 0; 695 } else { 696 node_size = nodes[i].node_mem; 697 if (node_size > ram_size - mem_start) { 698 node_size = ram_size - mem_start; 699 } 700 } 701 if (!mem_start) { 702 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 703 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 704 mem_start += spapr->rma_size; 705 node_size -= spapr->rma_size; 706 } 707 for ( ; node_size; ) { 708 hwaddr sizetmp = pow2floor(node_size); 709 710 /* mem_start != 0 here */ 711 if (ctzl(mem_start) < ctzl(sizetmp)) { 712 sizetmp = 1ULL << ctzl(mem_start); 713 } 714 715 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 716 node_size -= sizetmp; 717 mem_start += sizetmp; 718 } 719 } 720 721 return 0; 722 } 723 724 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 725 hwaddr fdt_addr, 726 hwaddr rtas_addr, 727 hwaddr rtas_size) 728 { 729 int ret, i; 730 size_t cb = 0; 731 char *bootlist; 732 void *fdt; 733 sPAPRPHBState *phb; 734 735 fdt = g_malloc(FDT_MAX_SIZE); 736 737 /* open out the base tree into a temp buffer for the final tweaks */ 738 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 739 740 ret = spapr_populate_memory(spapr, fdt); 741 if (ret < 0) { 742 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 743 exit(1); 744 } 745 746 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 747 if (ret < 0) { 748 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 749 exit(1); 750 } 751 752 QLIST_FOREACH(phb, &spapr->phbs, list) { 753 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 754 } 755 756 if (ret < 0) { 757 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 758 exit(1); 759 } 760 761 /* RTAS */ 762 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 763 if (ret < 0) { 764 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 765 } 766 767 /* Advertise NUMA via ibm,associativity */ 768 ret = spapr_fixup_cpu_dt(fdt, spapr); 769 if (ret < 0) { 770 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 771 } 772 773 bootlist = get_boot_devices_list(&cb, true); 774 if (cb && bootlist) { 775 int offset = fdt_path_offset(fdt, "/chosen"); 776 if (offset < 0) { 777 exit(1); 778 } 779 for (i = 0; i < cb; i++) { 780 if (bootlist[i] == '\n') { 781 bootlist[i] = ' '; 782 } 783 784 } 785 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 786 } 787 788 if (!spapr->has_graphics) { 789 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 790 } 791 792 _FDT((fdt_pack(fdt))); 793 794 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 795 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 796 fdt_totalsize(fdt), FDT_MAX_SIZE); 797 exit(1); 798 } 799 800 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 801 802 g_free(bootlist); 803 g_free(fdt); 804 } 805 806 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 807 { 808 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 809 } 810 811 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 812 { 813 CPUPPCState *env = &cpu->env; 814 815 if (msr_pr) { 816 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 817 env->gpr[3] = H_PRIVILEGE; 818 } else { 819 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 820 } 821 } 822 823 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 824 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 825 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 826 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 827 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 828 829 static void spapr_reset_htab(sPAPREnvironment *spapr) 830 { 831 long shift; 832 int index; 833 834 /* allocate hash page table. For now we always make this 16mb, 835 * later we should probably make it scale to the size of guest 836 * RAM */ 837 838 shift = kvmppc_reset_htab(spapr->htab_shift); 839 840 if (shift > 0) { 841 /* Kernel handles htab, we don't need to allocate one */ 842 spapr->htab_shift = shift; 843 kvmppc_kern_htab = true; 844 845 /* Tell readers to update their file descriptor */ 846 if (spapr->htab_fd >= 0) { 847 spapr->htab_fd_stale = true; 848 } 849 } else { 850 if (!spapr->htab) { 851 /* Allocate an htab if we don't yet have one */ 852 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 853 } 854 855 /* And clear it */ 856 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 857 858 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 859 DIRTY_HPTE(HPTE(spapr->htab, index)); 860 } 861 } 862 863 /* Update the RMA size if necessary */ 864 if (spapr->vrma_adjust) { 865 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 866 spapr->htab_shift); 867 } 868 } 869 870 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 871 { 872 bool matched = false; 873 874 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 875 matched = true; 876 } 877 878 if (!matched) { 879 error_report("Device %s is not supported by this machine yet.", 880 qdev_fw_name(DEVICE(sbdev))); 881 exit(1); 882 } 883 884 return 0; 885 } 886 887 /* 888 * A guest reset will cause spapr->htab_fd to become stale if being used. 889 * Reopen the file descriptor to make sure the whole HTAB is properly read. 890 */ 891 static int spapr_check_htab_fd(sPAPREnvironment *spapr) 892 { 893 int rc = 0; 894 895 if (spapr->htab_fd_stale) { 896 close(spapr->htab_fd); 897 spapr->htab_fd = kvmppc_get_htab_fd(false); 898 if (spapr->htab_fd < 0) { 899 error_report("Unable to open fd for reading hash table from KVM: " 900 "%s", strerror(errno)); 901 rc = -1; 902 } 903 spapr->htab_fd_stale = false; 904 } 905 906 return rc; 907 } 908 909 static void ppc_spapr_reset(void) 910 { 911 PowerPCCPU *first_ppc_cpu; 912 uint32_t rtas_limit; 913 914 /* Check for unknown sysbus devices */ 915 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 916 917 /* Reset the hash table & recalc the RMA */ 918 spapr_reset_htab(spapr); 919 920 qemu_devices_reset(); 921 922 /* 923 * We place the device tree and RTAS just below either the top of the RMA, 924 * or just below 2GB, whichever is lowere, so that it can be 925 * processed with 32-bit real mode code if necessary 926 */ 927 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 928 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 929 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 930 931 /* Load the fdt */ 932 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 933 spapr->rtas_size); 934 935 /* Copy RTAS over */ 936 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 937 spapr->rtas_size); 938 939 /* Set up the entry state */ 940 first_ppc_cpu = POWERPC_CPU(first_cpu); 941 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 942 first_ppc_cpu->env.gpr[5] = 0; 943 first_cpu->halted = 0; 944 first_ppc_cpu->env.nip = spapr->entry_point; 945 946 } 947 948 static void spapr_cpu_reset(void *opaque) 949 { 950 PowerPCCPU *cpu = opaque; 951 CPUState *cs = CPU(cpu); 952 CPUPPCState *env = &cpu->env; 953 954 cpu_reset(cs); 955 956 /* All CPUs start halted. CPU0 is unhalted from the machine level 957 * reset code and the rest are explicitly started up by the guest 958 * using an RTAS call */ 959 cs->halted = 1; 960 961 env->spr[SPR_HIOR] = 0; 962 963 env->external_htab = (uint8_t *)spapr->htab; 964 if (kvm_enabled() && !env->external_htab) { 965 /* 966 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 967 * functions do the right thing. 968 */ 969 env->external_htab = (void *)1; 970 } 971 env->htab_base = -1; 972 /* 973 * htab_mask is the mask used to normalize hash value to PTEG index. 974 * htab_shift is log2 of hash table size. 975 * We have 8 hpte per group, and each hpte is 16 bytes. 976 * ie have 128 bytes per hpte entry. 977 */ 978 env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1; 979 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 980 (spapr->htab_shift - 18); 981 } 982 983 static void spapr_create_nvram(sPAPREnvironment *spapr) 984 { 985 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 986 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 987 988 if (dinfo) { 989 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo)); 990 } 991 992 qdev_init_nofail(dev); 993 994 spapr->nvram = (struct sPAPRNVRAM *)dev; 995 } 996 997 /* Returns whether we want to use VGA or not */ 998 static int spapr_vga_init(PCIBus *pci_bus) 999 { 1000 switch (vga_interface_type) { 1001 case VGA_NONE: 1002 return false; 1003 case VGA_DEVICE: 1004 return true; 1005 case VGA_STD: 1006 return pci_vga_init(pci_bus) != NULL; 1007 default: 1008 fprintf(stderr, "This vga model is not supported," 1009 "currently it only supports -vga std\n"); 1010 exit(0); 1011 } 1012 } 1013 1014 static const VMStateDescription vmstate_spapr = { 1015 .name = "spapr", 1016 .version_id = 2, 1017 .minimum_version_id = 1, 1018 .fields = (VMStateField[]) { 1019 VMSTATE_UNUSED(4), /* used to be @next_irq */ 1020 1021 /* RTC offset */ 1022 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 1023 VMSTATE_PPC_TIMEBASE_V(tb, sPAPREnvironment, 2), 1024 VMSTATE_END_OF_LIST() 1025 }, 1026 }; 1027 1028 static int htab_save_setup(QEMUFile *f, void *opaque) 1029 { 1030 sPAPREnvironment *spapr = opaque; 1031 1032 /* "Iteration" header */ 1033 qemu_put_be32(f, spapr->htab_shift); 1034 1035 if (spapr->htab) { 1036 spapr->htab_save_index = 0; 1037 spapr->htab_first_pass = true; 1038 } else { 1039 assert(kvm_enabled()); 1040 1041 spapr->htab_fd = kvmppc_get_htab_fd(false); 1042 spapr->htab_fd_stale = false; 1043 if (spapr->htab_fd < 0) { 1044 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 1045 strerror(errno)); 1046 return -1; 1047 } 1048 } 1049 1050 1051 return 0; 1052 } 1053 1054 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 1055 int64_t max_ns) 1056 { 1057 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1058 int index = spapr->htab_save_index; 1059 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1060 1061 assert(spapr->htab_first_pass); 1062 1063 do { 1064 int chunkstart; 1065 1066 /* Consume invalid HPTEs */ 1067 while ((index < htabslots) 1068 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1069 index++; 1070 CLEAN_HPTE(HPTE(spapr->htab, index)); 1071 } 1072 1073 /* Consume valid HPTEs */ 1074 chunkstart = index; 1075 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1076 && HPTE_VALID(HPTE(spapr->htab, index))) { 1077 index++; 1078 CLEAN_HPTE(HPTE(spapr->htab, index)); 1079 } 1080 1081 if (index > chunkstart) { 1082 int n_valid = index - chunkstart; 1083 1084 qemu_put_be32(f, chunkstart); 1085 qemu_put_be16(f, n_valid); 1086 qemu_put_be16(f, 0); 1087 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1088 HASH_PTE_SIZE_64 * n_valid); 1089 1090 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1091 break; 1092 } 1093 } 1094 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1095 1096 if (index >= htabslots) { 1097 assert(index == htabslots); 1098 index = 0; 1099 spapr->htab_first_pass = false; 1100 } 1101 spapr->htab_save_index = index; 1102 } 1103 1104 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 1105 int64_t max_ns) 1106 { 1107 bool final = max_ns < 0; 1108 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1109 int examined = 0, sent = 0; 1110 int index = spapr->htab_save_index; 1111 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1112 1113 assert(!spapr->htab_first_pass); 1114 1115 do { 1116 int chunkstart, invalidstart; 1117 1118 /* Consume non-dirty HPTEs */ 1119 while ((index < htabslots) 1120 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1121 index++; 1122 examined++; 1123 } 1124 1125 chunkstart = index; 1126 /* Consume valid dirty HPTEs */ 1127 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1128 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1129 && HPTE_VALID(HPTE(spapr->htab, index))) { 1130 CLEAN_HPTE(HPTE(spapr->htab, index)); 1131 index++; 1132 examined++; 1133 } 1134 1135 invalidstart = index; 1136 /* Consume invalid dirty HPTEs */ 1137 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1138 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1139 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1140 CLEAN_HPTE(HPTE(spapr->htab, index)); 1141 index++; 1142 examined++; 1143 } 1144 1145 if (index > chunkstart) { 1146 int n_valid = invalidstart - chunkstart; 1147 int n_invalid = index - invalidstart; 1148 1149 qemu_put_be32(f, chunkstart); 1150 qemu_put_be16(f, n_valid); 1151 qemu_put_be16(f, n_invalid); 1152 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1153 HASH_PTE_SIZE_64 * n_valid); 1154 sent += index - chunkstart; 1155 1156 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1157 break; 1158 } 1159 } 1160 1161 if (examined >= htabslots) { 1162 break; 1163 } 1164 1165 if (index >= htabslots) { 1166 assert(index == htabslots); 1167 index = 0; 1168 } 1169 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1170 1171 if (index >= htabslots) { 1172 assert(index == htabslots); 1173 index = 0; 1174 } 1175 1176 spapr->htab_save_index = index; 1177 1178 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1179 } 1180 1181 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1182 #define MAX_KVM_BUF_SIZE 2048 1183 1184 static int htab_save_iterate(QEMUFile *f, void *opaque) 1185 { 1186 sPAPREnvironment *spapr = opaque; 1187 int rc = 0; 1188 1189 /* Iteration header */ 1190 qemu_put_be32(f, 0); 1191 1192 if (!spapr->htab) { 1193 assert(kvm_enabled()); 1194 1195 rc = spapr_check_htab_fd(spapr); 1196 if (rc < 0) { 1197 return rc; 1198 } 1199 1200 rc = kvmppc_save_htab(f, spapr->htab_fd, 1201 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1202 if (rc < 0) { 1203 return rc; 1204 } 1205 } else if (spapr->htab_first_pass) { 1206 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1207 } else { 1208 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1209 } 1210 1211 /* End marker */ 1212 qemu_put_be32(f, 0); 1213 qemu_put_be16(f, 0); 1214 qemu_put_be16(f, 0); 1215 1216 return rc; 1217 } 1218 1219 static int htab_save_complete(QEMUFile *f, void *opaque) 1220 { 1221 sPAPREnvironment *spapr = opaque; 1222 1223 /* Iteration header */ 1224 qemu_put_be32(f, 0); 1225 1226 if (!spapr->htab) { 1227 int rc; 1228 1229 assert(kvm_enabled()); 1230 1231 rc = spapr_check_htab_fd(spapr); 1232 if (rc < 0) { 1233 return rc; 1234 } 1235 1236 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1237 if (rc < 0) { 1238 return rc; 1239 } 1240 close(spapr->htab_fd); 1241 spapr->htab_fd = -1; 1242 } else { 1243 htab_save_later_pass(f, spapr, -1); 1244 } 1245 1246 /* End marker */ 1247 qemu_put_be32(f, 0); 1248 qemu_put_be16(f, 0); 1249 qemu_put_be16(f, 0); 1250 1251 return 0; 1252 } 1253 1254 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1255 { 1256 sPAPREnvironment *spapr = opaque; 1257 uint32_t section_hdr; 1258 int fd = -1; 1259 1260 if (version_id < 1 || version_id > 1) { 1261 fprintf(stderr, "htab_load() bad version\n"); 1262 return -EINVAL; 1263 } 1264 1265 section_hdr = qemu_get_be32(f); 1266 1267 if (section_hdr) { 1268 /* First section, just the hash shift */ 1269 if (spapr->htab_shift != section_hdr) { 1270 return -EINVAL; 1271 } 1272 return 0; 1273 } 1274 1275 if (!spapr->htab) { 1276 assert(kvm_enabled()); 1277 1278 fd = kvmppc_get_htab_fd(true); 1279 if (fd < 0) { 1280 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1281 strerror(errno)); 1282 } 1283 } 1284 1285 while (true) { 1286 uint32_t index; 1287 uint16_t n_valid, n_invalid; 1288 1289 index = qemu_get_be32(f); 1290 n_valid = qemu_get_be16(f); 1291 n_invalid = qemu_get_be16(f); 1292 1293 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1294 /* End of Stream */ 1295 break; 1296 } 1297 1298 if ((index + n_valid + n_invalid) > 1299 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1300 /* Bad index in stream */ 1301 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1302 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1303 spapr->htab_shift); 1304 return -EINVAL; 1305 } 1306 1307 if (spapr->htab) { 1308 if (n_valid) { 1309 qemu_get_buffer(f, HPTE(spapr->htab, index), 1310 HASH_PTE_SIZE_64 * n_valid); 1311 } 1312 if (n_invalid) { 1313 memset(HPTE(spapr->htab, index + n_valid), 0, 1314 HASH_PTE_SIZE_64 * n_invalid); 1315 } 1316 } else { 1317 int rc; 1318 1319 assert(fd >= 0); 1320 1321 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1322 if (rc < 0) { 1323 return rc; 1324 } 1325 } 1326 } 1327 1328 if (!spapr->htab) { 1329 assert(fd >= 0); 1330 close(fd); 1331 } 1332 1333 return 0; 1334 } 1335 1336 static SaveVMHandlers savevm_htab_handlers = { 1337 .save_live_setup = htab_save_setup, 1338 .save_live_iterate = htab_save_iterate, 1339 .save_live_complete = htab_save_complete, 1340 .load_state = htab_load, 1341 }; 1342 1343 /* pSeries LPAR / sPAPR hardware init */ 1344 static void ppc_spapr_init(MachineState *machine) 1345 { 1346 ram_addr_t ram_size = machine->ram_size; 1347 const char *cpu_model = machine->cpu_model; 1348 const char *kernel_filename = machine->kernel_filename; 1349 const char *kernel_cmdline = machine->kernel_cmdline; 1350 const char *initrd_filename = machine->initrd_filename; 1351 const char *boot_device = machine->boot_order; 1352 PowerPCCPU *cpu; 1353 CPUPPCState *env; 1354 PCIHostState *phb; 1355 int i; 1356 MemoryRegion *sysmem = get_system_memory(); 1357 MemoryRegion *ram = g_new(MemoryRegion, 1); 1358 MemoryRegion *rma_region; 1359 void *rma = NULL; 1360 hwaddr rma_alloc_size; 1361 hwaddr node0_size = spapr_node0_size(); 1362 uint32_t initrd_base = 0; 1363 long kernel_size = 0, initrd_size = 0; 1364 long load_limit, fw_size; 1365 bool kernel_le = false; 1366 char *filename; 1367 1368 msi_supported = true; 1369 1370 spapr = g_malloc0(sizeof(*spapr)); 1371 QLIST_INIT(&spapr->phbs); 1372 1373 cpu_ppc_hypercall = emulate_spapr_hypercall; 1374 1375 /* Allocate RMA if necessary */ 1376 rma_alloc_size = kvmppc_alloc_rma(&rma); 1377 1378 if (rma_alloc_size == -1) { 1379 hw_error("qemu: Unable to create RMA\n"); 1380 exit(1); 1381 } 1382 1383 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1384 spapr->rma_size = rma_alloc_size; 1385 } else { 1386 spapr->rma_size = node0_size; 1387 1388 /* With KVM, we don't actually know whether KVM supports an 1389 * unbounded RMA (PR KVM) or is limited by the hash table size 1390 * (HV KVM using VRMA), so we always assume the latter 1391 * 1392 * In that case, we also limit the initial allocations for RTAS 1393 * etc... to 256M since we have no way to know what the VRMA size 1394 * is going to be as it depends on the size of the hash table 1395 * isn't determined yet. 1396 */ 1397 if (kvm_enabled()) { 1398 spapr->vrma_adjust = 1; 1399 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1400 } 1401 } 1402 1403 if (spapr->rma_size > node0_size) { 1404 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1405 spapr->rma_size); 1406 exit(1); 1407 } 1408 1409 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1410 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1411 1412 /* We aim for a hash table of size 1/128 the size of RAM. The 1413 * normal rule of thumb is 1/64 the size of RAM, but that's much 1414 * more than needed for the Linux guests we support. */ 1415 spapr->htab_shift = 18; /* Minimum architected size */ 1416 while (spapr->htab_shift <= 46) { 1417 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1418 break; 1419 } 1420 spapr->htab_shift++; 1421 } 1422 1423 /* Set up Interrupt Controller before we create the VCPUs */ 1424 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1425 XICS_IRQS); 1426 1427 /* init CPUs */ 1428 if (cpu_model == NULL) { 1429 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1430 } 1431 for (i = 0; i < smp_cpus; i++) { 1432 cpu = cpu_ppc_init(cpu_model); 1433 if (cpu == NULL) { 1434 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1435 exit(1); 1436 } 1437 env = &cpu->env; 1438 1439 /* Set time-base frequency to 512 MHz */ 1440 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1441 1442 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1443 * MSR[IP] should never be set. 1444 */ 1445 env->msr_mask &= ~(1 << 6); 1446 1447 /* Tell KVM that we're in PAPR mode */ 1448 if (kvm_enabled()) { 1449 kvmppc_set_papr(cpu); 1450 } 1451 1452 if (cpu->max_compat) { 1453 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1454 exit(1); 1455 } 1456 } 1457 1458 xics_cpu_setup(spapr->icp, cpu); 1459 1460 qemu_register_reset(spapr_cpu_reset, cpu); 1461 } 1462 1463 /* allocate RAM */ 1464 spapr->ram_limit = ram_size; 1465 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1466 spapr->ram_limit); 1467 memory_region_add_subregion(sysmem, 0, ram); 1468 1469 if (rma_alloc_size && rma) { 1470 rma_region = g_new(MemoryRegion, 1); 1471 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1472 rma_alloc_size, rma); 1473 vmstate_register_ram_global(rma_region); 1474 memory_region_add_subregion(sysmem, 0, rma_region); 1475 } 1476 1477 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1478 spapr->rtas_size = get_image_size(filename); 1479 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1480 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1481 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1482 exit(1); 1483 } 1484 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1485 hw_error("RTAS too big ! 0x%zx bytes (max is 0x%x)\n", 1486 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1487 exit(1); 1488 } 1489 g_free(filename); 1490 1491 /* Set up EPOW events infrastructure */ 1492 spapr_events_init(spapr); 1493 1494 /* Set up VIO bus */ 1495 spapr->vio_bus = spapr_vio_bus_init(); 1496 1497 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1498 if (serial_hds[i]) { 1499 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1500 } 1501 } 1502 1503 /* We always have at least the nvram device on VIO */ 1504 spapr_create_nvram(spapr); 1505 1506 /* Set up PCI */ 1507 spapr_pci_rtas_init(); 1508 1509 phb = spapr_create_phb(spapr, 0); 1510 1511 for (i = 0; i < nb_nics; i++) { 1512 NICInfo *nd = &nd_table[i]; 1513 1514 if (!nd->model) { 1515 nd->model = g_strdup("ibmveth"); 1516 } 1517 1518 if (strcmp(nd->model, "ibmveth") == 0) { 1519 spapr_vlan_create(spapr->vio_bus, nd); 1520 } else { 1521 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1522 } 1523 } 1524 1525 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1526 spapr_vscsi_create(spapr->vio_bus); 1527 } 1528 1529 /* Graphics */ 1530 if (spapr_vga_init(phb->bus)) { 1531 spapr->has_graphics = true; 1532 machine->usb |= defaults_enabled(); 1533 } 1534 1535 if (machine->usb) { 1536 pci_create_simple(phb->bus, -1, "pci-ohci"); 1537 if (spapr->has_graphics) { 1538 usbdevice_create("keyboard"); 1539 usbdevice_create("mouse"); 1540 } 1541 } 1542 1543 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1544 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1545 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1546 exit(1); 1547 } 1548 1549 if (kernel_filename) { 1550 uint64_t lowaddr = 0; 1551 1552 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1553 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1554 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1555 kernel_size = load_elf(kernel_filename, 1556 translate_kernel_address, NULL, 1557 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1558 kernel_le = kernel_size > 0; 1559 } 1560 if (kernel_size < 0) { 1561 fprintf(stderr, "qemu: error loading %s: %s\n", 1562 kernel_filename, load_elf_strerror(kernel_size)); 1563 exit(1); 1564 } 1565 1566 /* load initrd */ 1567 if (initrd_filename) { 1568 /* Try to locate the initrd in the gap between the kernel 1569 * and the firmware. Add a bit of space just in case 1570 */ 1571 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1572 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1573 load_limit - initrd_base); 1574 if (initrd_size < 0) { 1575 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1576 initrd_filename); 1577 exit(1); 1578 } 1579 } else { 1580 initrd_base = 0; 1581 initrd_size = 0; 1582 } 1583 } 1584 1585 if (bios_name == NULL) { 1586 bios_name = FW_FILE_NAME; 1587 } 1588 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1589 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1590 if (fw_size < 0) { 1591 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1592 exit(1); 1593 } 1594 g_free(filename); 1595 1596 spapr->entry_point = 0x100; 1597 1598 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1599 register_savevm_live(NULL, "spapr/htab", -1, 1, 1600 &savevm_htab_handlers, spapr); 1601 1602 /* Prepare the device tree */ 1603 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1604 kernel_size, kernel_le, 1605 boot_device, kernel_cmdline, 1606 spapr->epow_irq); 1607 assert(spapr->fdt_skel != NULL); 1608 } 1609 1610 static int spapr_kvm_type(const char *vm_type) 1611 { 1612 if (!vm_type) { 1613 return 0; 1614 } 1615 1616 if (!strcmp(vm_type, "HV")) { 1617 return 1; 1618 } 1619 1620 if (!strcmp(vm_type, "PR")) { 1621 return 2; 1622 } 1623 1624 error_report("Unknown kvm-type specified '%s'", vm_type); 1625 exit(1); 1626 } 1627 1628 /* 1629 * Implementation of an interface to adjust firmware path 1630 * for the bootindex property handling. 1631 */ 1632 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1633 DeviceState *dev) 1634 { 1635 #define CAST(type, obj, name) \ 1636 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1637 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1638 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1639 1640 if (d) { 1641 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1642 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1643 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1644 1645 if (spapr) { 1646 /* 1647 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1648 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1649 * in the top 16 bits of the 64-bit LUN 1650 */ 1651 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1652 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1653 (uint64_t)id << 48); 1654 } else if (virtio) { 1655 /* 1656 * We use SRP luns of the form 01000000 | (target << 8) | lun 1657 * in the top 32 bits of the 64-bit LUN 1658 * Note: the quote above is from SLOF and it is wrong, 1659 * the actual binding is: 1660 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1661 */ 1662 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1663 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1664 (uint64_t)id << 32); 1665 } else if (usb) { 1666 /* 1667 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1668 * in the top 32 bits of the 64-bit LUN 1669 */ 1670 unsigned usb_port = atoi(usb->port->path); 1671 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1672 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1673 (uint64_t)id << 32); 1674 } 1675 } 1676 1677 if (phb) { 1678 /* Replace "pci" with "pci@800000020000000" */ 1679 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1680 } 1681 1682 return NULL; 1683 } 1684 1685 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1686 { 1687 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1688 1689 return g_strdup(sm->kvm_type); 1690 } 1691 1692 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1693 { 1694 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1695 1696 g_free(sm->kvm_type); 1697 sm->kvm_type = g_strdup(value); 1698 } 1699 1700 static void spapr_machine_initfn(Object *obj) 1701 { 1702 object_property_add_str(obj, "kvm-type", 1703 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1704 object_property_set_description(obj, "kvm-type", 1705 "Specifies the KVM virtualization mode (HV, PR)", 1706 NULL); 1707 } 1708 1709 static void ppc_cpu_do_nmi_on_cpu(void *arg) 1710 { 1711 CPUState *cs = arg; 1712 1713 cpu_synchronize_state(cs); 1714 ppc_cpu_do_system_reset(cs); 1715 } 1716 1717 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 1718 { 1719 CPUState *cs; 1720 1721 CPU_FOREACH(cs) { 1722 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 1723 } 1724 } 1725 1726 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1727 { 1728 MachineClass *mc = MACHINE_CLASS(oc); 1729 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1730 NMIClass *nc = NMI_CLASS(oc); 1731 1732 mc->init = ppc_spapr_init; 1733 mc->reset = ppc_spapr_reset; 1734 mc->block_default_type = IF_SCSI; 1735 mc->max_cpus = MAX_CPUS; 1736 mc->no_parallel = 1; 1737 mc->default_boot_order = NULL; 1738 mc->kvm_type = spapr_kvm_type; 1739 mc->has_dynamic_sysbus = true; 1740 1741 fwc->get_dev_path = spapr_get_fw_dev_path; 1742 nc->nmi_monitor_handler = spapr_nmi; 1743 } 1744 1745 static const TypeInfo spapr_machine_info = { 1746 .name = TYPE_SPAPR_MACHINE, 1747 .parent = TYPE_MACHINE, 1748 .abstract = true, 1749 .instance_size = sizeof(sPAPRMachineState), 1750 .instance_init = spapr_machine_initfn, 1751 .class_init = spapr_machine_class_init, 1752 .interfaces = (InterfaceInfo[]) { 1753 { TYPE_FW_PATH_PROVIDER }, 1754 { TYPE_NMI }, 1755 { } 1756 }, 1757 }; 1758 1759 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 1760 { 1761 MachineClass *mc = MACHINE_CLASS(oc); 1762 static GlobalProperty compat_props[] = { 1763 HW_COMPAT_2_1, 1764 { /* end of list */ } 1765 }; 1766 1767 mc->name = "pseries-2.1"; 1768 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 1769 mc->compat_props = compat_props; 1770 } 1771 1772 static const TypeInfo spapr_machine_2_1_info = { 1773 .name = TYPE_SPAPR_MACHINE "2.1", 1774 .parent = TYPE_SPAPR_MACHINE, 1775 .class_init = spapr_machine_2_1_class_init, 1776 }; 1777 1778 static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) 1779 { 1780 MachineClass *mc = MACHINE_CLASS(oc); 1781 1782 mc->name = "pseries-2.2"; 1783 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; 1784 mc->alias = "pseries"; 1785 mc->is_default = 1; 1786 } 1787 1788 static const TypeInfo spapr_machine_2_2_info = { 1789 .name = TYPE_SPAPR_MACHINE "2.2", 1790 .parent = TYPE_SPAPR_MACHINE, 1791 .class_init = spapr_machine_2_2_class_init, 1792 }; 1793 1794 static void spapr_machine_register_types(void) 1795 { 1796 type_register_static(&spapr_machine_info); 1797 type_register_static(&spapr_machine_2_1_info); 1798 type_register_static(&spapr_machine_2_2_info); 1799 } 1800 1801 type_init(spapr_machine_register_types) 1802