1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "sysemu/sysemu.h" 28 #include "hw/hw.h" 29 #include "hw/fw-path-provider.h" 30 #include "elf.h" 31 #include "net/net.h" 32 #include "sysemu/block-backend.h" 33 #include "sysemu/cpus.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_ppc.h" 36 #include "mmu-hash64.h" 37 #include "qom/cpu.h" 38 39 #include "hw/boards.h" 40 #include "hw/ppc/ppc.h" 41 #include "hw/loader.h" 42 43 #include "hw/ppc/spapr.h" 44 #include "hw/ppc/spapr_vio.h" 45 #include "hw/pci-host/spapr.h" 46 #include "hw/ppc/xics.h" 47 #include "hw/pci/msi.h" 48 49 #include "hw/pci/pci.h" 50 #include "hw/scsi/scsi.h" 51 #include "hw/virtio/virtio-scsi.h" 52 53 #include "exec/address-spaces.h" 54 #include "hw/usb.h" 55 #include "qemu/config-file.h" 56 #include "qemu/error-report.h" 57 #include "trace.h" 58 #include "hw/nmi.h" 59 60 #include "hw/compat.h" 61 62 #include <libfdt.h> 63 64 /* SLOF memory layout: 65 * 66 * SLOF raw image loaded at 0, copies its romfs right below the flat 67 * device-tree, then position SLOF itself 31M below that 68 * 69 * So we set FW_OVERHEAD to 40MB which should account for all of that 70 * and more 71 * 72 * We load our kernel at 4M, leaving space for SLOF initial image 73 */ 74 #define FDT_MAX_SIZE 0x40000 75 #define RTAS_MAX_SIZE 0x10000 76 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 77 #define FW_MAX_SIZE 0x400000 78 #define FW_FILE_NAME "slof.bin" 79 #define FW_OVERHEAD 0x2800000 80 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 81 82 #define MIN_RMA_SLOF 128UL 83 84 #define TIMEBASE_FREQ 512000000ULL 85 86 #define MAX_CPUS 255 87 88 #define PHANDLE_XICP 0x00001111 89 90 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 91 92 typedef struct sPAPRMachineState sPAPRMachineState; 93 94 #define TYPE_SPAPR_MACHINE "spapr-machine" 95 #define SPAPR_MACHINE(obj) \ 96 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE) 97 98 /** 99 * sPAPRMachineState: 100 */ 101 struct sPAPRMachineState { 102 /*< private >*/ 103 MachineState parent_obj; 104 105 /*< public >*/ 106 char *kvm_type; 107 }; 108 109 sPAPREnvironment *spapr; 110 111 static XICSState *try_create_xics(const char *type, int nr_servers, 112 int nr_irqs) 113 { 114 DeviceState *dev; 115 116 dev = qdev_create(NULL, type); 117 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 118 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 119 if (qdev_init(dev) < 0) { 120 return NULL; 121 } 122 123 return XICS_COMMON(dev); 124 } 125 126 static XICSState *xics_system_init(int nr_servers, int nr_irqs) 127 { 128 XICSState *icp = NULL; 129 130 if (kvm_enabled()) { 131 QemuOpts *machine_opts = qemu_get_machine_opts(); 132 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 133 "kernel_irqchip", true); 134 bool irqchip_required = qemu_opt_get_bool(machine_opts, 135 "kernel_irqchip", false); 136 if (irqchip_allowed) { 137 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs); 138 } 139 140 if (irqchip_required && !icp) { 141 perror("Failed to create in-kernel XICS\n"); 142 abort(); 143 } 144 } 145 146 if (!icp) { 147 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs); 148 } 149 150 if (!icp) { 151 perror("Failed to create XICS\n"); 152 abort(); 153 } 154 155 return icp; 156 } 157 158 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 159 int smt_threads) 160 { 161 int i, ret = 0; 162 uint32_t servers_prop[smt_threads]; 163 uint32_t gservers_prop[smt_threads * 2]; 164 int index = ppc_get_vcpu_dt_id(cpu); 165 166 if (cpu->cpu_version) { 167 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 168 if (ret < 0) { 169 return ret; 170 } 171 } 172 173 /* Build interrupt servers and gservers properties */ 174 for (i = 0; i < smt_threads; i++) { 175 servers_prop[i] = cpu_to_be32(index + i); 176 /* Hack, direct the group queues back to cpu 0 */ 177 gservers_prop[i*2] = cpu_to_be32(index + i); 178 gservers_prop[i*2 + 1] = 0; 179 } 180 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 181 servers_prop, sizeof(servers_prop)); 182 if (ret < 0) { 183 return ret; 184 } 185 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 186 gservers_prop, sizeof(gservers_prop)); 187 188 return ret; 189 } 190 191 static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr) 192 { 193 int ret = 0, offset, cpus_offset; 194 CPUState *cs; 195 char cpu_model[32]; 196 int smt = kvmppc_smt_threads(); 197 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 198 199 CPU_FOREACH(cs) { 200 PowerPCCPU *cpu = POWERPC_CPU(cs); 201 DeviceClass *dc = DEVICE_GET_CLASS(cs); 202 int index = ppc_get_vcpu_dt_id(cpu); 203 uint32_t associativity[] = {cpu_to_be32(0x5), 204 cpu_to_be32(0x0), 205 cpu_to_be32(0x0), 206 cpu_to_be32(0x0), 207 cpu_to_be32(cs->numa_node), 208 cpu_to_be32(index)}; 209 210 if ((index % smt) != 0) { 211 continue; 212 } 213 214 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 215 216 cpus_offset = fdt_path_offset(fdt, "/cpus"); 217 if (cpus_offset < 0) { 218 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 219 "cpus"); 220 if (cpus_offset < 0) { 221 return cpus_offset; 222 } 223 } 224 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 225 if (offset < 0) { 226 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 227 if (offset < 0) { 228 return offset; 229 } 230 } 231 232 if (nb_numa_nodes > 1) { 233 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 234 sizeof(associativity)); 235 if (ret < 0) { 236 return ret; 237 } 238 } 239 240 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 241 pft_size_prop, sizeof(pft_size_prop)); 242 if (ret < 0) { 243 return ret; 244 } 245 246 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 247 ppc_get_compat_smt_threads(cpu)); 248 if (ret < 0) { 249 return ret; 250 } 251 } 252 return ret; 253 } 254 255 256 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 257 size_t maxsize) 258 { 259 size_t maxcells = maxsize / sizeof(uint32_t); 260 int i, j, count; 261 uint32_t *p = prop; 262 263 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 264 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 265 266 if (!sps->page_shift) { 267 break; 268 } 269 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 270 if (sps->enc[count].page_shift == 0) { 271 break; 272 } 273 } 274 if ((p - prop) >= (maxcells - 3 - count * 2)) { 275 break; 276 } 277 *(p++) = cpu_to_be32(sps->page_shift); 278 *(p++) = cpu_to_be32(sps->slb_enc); 279 *(p++) = cpu_to_be32(count); 280 for (j = 0; j < count; j++) { 281 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 282 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 283 } 284 } 285 286 return (p - prop) * sizeof(uint32_t); 287 } 288 289 static hwaddr spapr_node0_size(void) 290 { 291 if (nb_numa_nodes) { 292 int i; 293 for (i = 0; i < nb_numa_nodes; ++i) { 294 if (numa_info[i].node_mem) { 295 return MIN(pow2floor(numa_info[i].node_mem), ram_size); 296 } 297 } 298 } 299 return ram_size; 300 } 301 302 #define _FDT(exp) \ 303 do { \ 304 int ret = (exp); \ 305 if (ret < 0) { \ 306 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 307 #exp, fdt_strerror(ret)); \ 308 exit(1); \ 309 } \ 310 } while (0) 311 312 static void add_str(GString *s, const gchar *s1) 313 { 314 g_string_append_len(s, s1, strlen(s1) + 1); 315 } 316 317 static void *spapr_create_fdt_skel(hwaddr initrd_base, 318 hwaddr initrd_size, 319 hwaddr kernel_size, 320 bool little_endian, 321 const char *boot_device, 322 const char *kernel_cmdline, 323 uint32_t epow_irq) 324 { 325 void *fdt; 326 CPUState *cs; 327 uint32_t start_prop = cpu_to_be32(initrd_base); 328 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 329 GString *hypertas = g_string_sized_new(256); 330 GString *qemu_hypertas = g_string_sized_new(256); 331 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 332 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; 333 int smt = kvmppc_smt_threads(); 334 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 335 QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL); 336 unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0; 337 uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1; 338 char *buf; 339 340 add_str(hypertas, "hcall-pft"); 341 add_str(hypertas, "hcall-term"); 342 add_str(hypertas, "hcall-dabr"); 343 add_str(hypertas, "hcall-interrupt"); 344 add_str(hypertas, "hcall-tce"); 345 add_str(hypertas, "hcall-vio"); 346 add_str(hypertas, "hcall-splpar"); 347 add_str(hypertas, "hcall-bulk"); 348 add_str(hypertas, "hcall-set-mode"); 349 add_str(qemu_hypertas, "hcall-memop1"); 350 351 fdt = g_malloc0(FDT_MAX_SIZE); 352 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 353 354 if (kernel_size) { 355 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 356 } 357 if (initrd_size) { 358 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 359 } 360 _FDT((fdt_finish_reservemap(fdt))); 361 362 /* Root node */ 363 _FDT((fdt_begin_node(fdt, ""))); 364 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 365 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 366 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 367 368 /* 369 * Add info to guest to indentify which host is it being run on 370 * and what is the uuid of the guest 371 */ 372 if (kvmppc_get_host_model(&buf)) { 373 _FDT((fdt_property_string(fdt, "host-model", buf))); 374 g_free(buf); 375 } 376 if (kvmppc_get_host_serial(&buf)) { 377 _FDT((fdt_property_string(fdt, "host-serial", buf))); 378 g_free(buf); 379 } 380 381 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 382 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 383 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 384 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 385 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 386 qemu_uuid[14], qemu_uuid[15]); 387 388 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 389 g_free(buf); 390 391 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 392 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 393 394 /* /chosen */ 395 _FDT((fdt_begin_node(fdt, "chosen"))); 396 397 /* Set Form1_affinity */ 398 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 399 400 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 401 _FDT((fdt_property(fdt, "linux,initrd-start", 402 &start_prop, sizeof(start_prop)))); 403 _FDT((fdt_property(fdt, "linux,initrd-end", 404 &end_prop, sizeof(end_prop)))); 405 if (kernel_size) { 406 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 407 cpu_to_be64(kernel_size) }; 408 409 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 410 if (little_endian) { 411 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 412 } 413 } 414 if (boot_device) { 415 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); 416 } 417 if (boot_menu) { 418 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 419 } 420 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 421 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 422 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 423 424 _FDT((fdt_end_node(fdt))); 425 426 /* cpus */ 427 _FDT((fdt_begin_node(fdt, "cpus"))); 428 429 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 430 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 431 432 CPU_FOREACH(cs) { 433 PowerPCCPU *cpu = POWERPC_CPU(cs); 434 CPUPPCState *env = &cpu->env; 435 DeviceClass *dc = DEVICE_GET_CLASS(cs); 436 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 437 int index = ppc_get_vcpu_dt_id(cpu); 438 char *nodename; 439 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 440 0xffffffff, 0xffffffff}; 441 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 442 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 443 uint32_t page_sizes_prop[64]; 444 size_t page_sizes_prop_size; 445 446 if ((index % smt) != 0) { 447 continue; 448 } 449 450 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 451 452 _FDT((fdt_begin_node(fdt, nodename))); 453 454 g_free(nodename); 455 456 _FDT((fdt_property_cell(fdt, "reg", index))); 457 _FDT((fdt_property_string(fdt, "device_type", "cpu"))); 458 459 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); 460 _FDT((fdt_property_cell(fdt, "d-cache-block-size", 461 env->dcache_line_size))); 462 _FDT((fdt_property_cell(fdt, "d-cache-line-size", 463 env->dcache_line_size))); 464 _FDT((fdt_property_cell(fdt, "i-cache-block-size", 465 env->icache_line_size))); 466 _FDT((fdt_property_cell(fdt, "i-cache-line-size", 467 env->icache_line_size))); 468 469 if (pcc->l1_dcache_size) { 470 _FDT((fdt_property_cell(fdt, "d-cache-size", pcc->l1_dcache_size))); 471 } else { 472 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 473 } 474 if (pcc->l1_icache_size) { 475 _FDT((fdt_property_cell(fdt, "i-cache-size", pcc->l1_icache_size))); 476 } else { 477 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 478 } 479 480 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq))); 481 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq))); 482 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); 483 _FDT((fdt_property_string(fdt, "status", "okay"))); 484 _FDT((fdt_property(fdt, "64-bit", NULL, 0))); 485 486 if (env->spr_cb[SPR_PURR].oea_read) { 487 _FDT((fdt_property(fdt, "ibm,purr", NULL, 0))); 488 } 489 490 if (env->mmu_model & POWERPC_MMU_1TSEG) { 491 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", 492 segs, sizeof(segs)))); 493 } 494 495 /* Advertise VMX/VSX (vector extensions) if available 496 * 0 / no property == no vector extensions 497 * 1 == VMX / Altivec available 498 * 2 == VSX available */ 499 if (env->insns_flags & PPC_ALTIVEC) { 500 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 501 502 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx))); 503 } 504 505 /* Advertise DFP (Decimal Floating Point) if available 506 * 0 / no property == no DFP 507 * 1 == DFP available */ 508 if (env->insns_flags2 & PPC2_DFP) { 509 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1))); 510 } 511 512 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 513 sizeof(page_sizes_prop)); 514 if (page_sizes_prop_size) { 515 _FDT((fdt_property(fdt, "ibm,segment-page-sizes", 516 page_sizes_prop, page_sizes_prop_size))); 517 } 518 519 _FDT((fdt_property_cell(fdt, "ibm,chip-id", 520 cs->cpu_index / cpus_per_socket))); 521 522 _FDT((fdt_end_node(fdt))); 523 } 524 525 _FDT((fdt_end_node(fdt))); 526 527 /* RTAS */ 528 _FDT((fdt_begin_node(fdt, "rtas"))); 529 530 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 531 add_str(hypertas, "hcall-multi-tce"); 532 } 533 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 534 hypertas->len))); 535 g_string_free(hypertas, TRUE); 536 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 537 qemu_hypertas->len))); 538 g_string_free(qemu_hypertas, TRUE); 539 540 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 541 refpoints, sizeof(refpoints)))); 542 543 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 544 545 /* 546 * According to PAPR, rtas ibm,os-term does not guarantee a return 547 * back to the guest cpu. 548 * 549 * While an additional ibm,extended-os-term property indicates that 550 * rtas call return will always occur. Set this property. 551 */ 552 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 553 554 _FDT((fdt_end_node(fdt))); 555 556 /* interrupt controller */ 557 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 558 559 _FDT((fdt_property_string(fdt, "device_type", 560 "PowerPC-External-Interrupt-Presentation"))); 561 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 562 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 563 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 564 interrupt_server_ranges_prop, 565 sizeof(interrupt_server_ranges_prop)))); 566 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 567 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 568 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 569 570 _FDT((fdt_end_node(fdt))); 571 572 /* vdevice */ 573 _FDT((fdt_begin_node(fdt, "vdevice"))); 574 575 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 576 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 577 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 578 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 579 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 580 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 581 582 _FDT((fdt_end_node(fdt))); 583 584 /* event-sources */ 585 spapr_events_fdt_skel(fdt, epow_irq); 586 587 /* /hypervisor node */ 588 if (kvm_enabled()) { 589 uint8_t hypercall[16]; 590 591 /* indicate KVM hypercall interface */ 592 _FDT((fdt_begin_node(fdt, "hypervisor"))); 593 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 594 if (kvmppc_has_cap_fixup_hcalls()) { 595 /* 596 * Older KVM versions with older guest kernels were broken with the 597 * magic page, don't allow the guest to map it. 598 */ 599 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 600 sizeof(hypercall)); 601 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 602 sizeof(hypercall)))); 603 } 604 _FDT((fdt_end_node(fdt))); 605 } 606 607 _FDT((fdt_end_node(fdt))); /* close root node */ 608 _FDT((fdt_finish(fdt))); 609 610 return fdt; 611 } 612 613 int spapr_h_cas_compose_response(target_ulong addr, target_ulong size) 614 { 615 void *fdt, *fdt_skel; 616 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 617 618 size -= sizeof(hdr); 619 620 /* Create sceleton */ 621 fdt_skel = g_malloc0(size); 622 _FDT((fdt_create(fdt_skel, size))); 623 _FDT((fdt_begin_node(fdt_skel, ""))); 624 _FDT((fdt_end_node(fdt_skel))); 625 _FDT((fdt_finish(fdt_skel))); 626 fdt = g_malloc0(size); 627 _FDT((fdt_open_into(fdt_skel, fdt, size))); 628 g_free(fdt_skel); 629 630 /* Fix skeleton up */ 631 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 632 633 /* Pack resulting tree */ 634 _FDT((fdt_pack(fdt))); 635 636 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 637 trace_spapr_cas_failed(size); 638 return -1; 639 } 640 641 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 642 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 643 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 644 g_free(fdt); 645 646 return 0; 647 } 648 649 static void spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 650 hwaddr size) 651 { 652 uint32_t associativity[] = { 653 cpu_to_be32(0x4), /* length */ 654 cpu_to_be32(0x0), cpu_to_be32(0x0), 655 cpu_to_be32(0x0), cpu_to_be32(nodeid) 656 }; 657 char mem_name[32]; 658 uint64_t mem_reg_property[2]; 659 int off; 660 661 mem_reg_property[0] = cpu_to_be64(start); 662 mem_reg_property[1] = cpu_to_be64(size); 663 664 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 665 off = fdt_add_subnode(fdt, 0, mem_name); 666 _FDT(off); 667 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 668 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 669 sizeof(mem_reg_property)))); 670 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 671 sizeof(associativity)))); 672 } 673 674 static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt) 675 { 676 hwaddr mem_start, node_size; 677 int i, nb_nodes = nb_numa_nodes; 678 NodeInfo *nodes = numa_info; 679 NodeInfo ramnode; 680 681 /* No NUMA nodes, assume there is just one node with whole RAM */ 682 if (!nb_numa_nodes) { 683 nb_nodes = 1; 684 ramnode.node_mem = ram_size; 685 nodes = &ramnode; 686 } 687 688 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 689 if (!nodes[i].node_mem) { 690 continue; 691 } 692 if (mem_start >= ram_size) { 693 node_size = 0; 694 } else { 695 node_size = nodes[i].node_mem; 696 if (node_size > ram_size - mem_start) { 697 node_size = ram_size - mem_start; 698 } 699 } 700 if (!mem_start) { 701 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 702 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 703 mem_start += spapr->rma_size; 704 node_size -= spapr->rma_size; 705 } 706 for ( ; node_size; ) { 707 hwaddr sizetmp = pow2floor(node_size); 708 709 /* mem_start != 0 here */ 710 if (ctzl(mem_start) < ctzl(sizetmp)) { 711 sizetmp = 1ULL << ctzl(mem_start); 712 } 713 714 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 715 node_size -= sizetmp; 716 mem_start += sizetmp; 717 } 718 } 719 720 return 0; 721 } 722 723 static void spapr_finalize_fdt(sPAPREnvironment *spapr, 724 hwaddr fdt_addr, 725 hwaddr rtas_addr, 726 hwaddr rtas_size) 727 { 728 int ret, i; 729 size_t cb = 0; 730 char *bootlist; 731 void *fdt; 732 sPAPRPHBState *phb; 733 734 fdt = g_malloc(FDT_MAX_SIZE); 735 736 /* open out the base tree into a temp buffer for the final tweaks */ 737 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 738 739 ret = spapr_populate_memory(spapr, fdt); 740 if (ret < 0) { 741 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 742 exit(1); 743 } 744 745 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 746 if (ret < 0) { 747 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 748 exit(1); 749 } 750 751 QLIST_FOREACH(phb, &spapr->phbs, list) { 752 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 753 } 754 755 if (ret < 0) { 756 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 757 exit(1); 758 } 759 760 /* RTAS */ 761 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 762 if (ret < 0) { 763 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 764 } 765 766 /* Advertise NUMA via ibm,associativity */ 767 ret = spapr_fixup_cpu_dt(fdt, spapr); 768 if (ret < 0) { 769 fprintf(stderr, "Couldn't finalize CPU device tree properties\n"); 770 } 771 772 bootlist = get_boot_devices_list(&cb, true); 773 if (cb && bootlist) { 774 int offset = fdt_path_offset(fdt, "/chosen"); 775 if (offset < 0) { 776 exit(1); 777 } 778 for (i = 0; i < cb; i++) { 779 if (bootlist[i] == '\n') { 780 bootlist[i] = ' '; 781 } 782 783 } 784 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 785 } 786 787 if (!spapr->has_graphics) { 788 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 789 } 790 791 _FDT((fdt_pack(fdt))); 792 793 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 794 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n", 795 fdt_totalsize(fdt), FDT_MAX_SIZE); 796 exit(1); 797 } 798 799 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 800 801 g_free(bootlist); 802 g_free(fdt); 803 } 804 805 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 806 { 807 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 808 } 809 810 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 811 { 812 CPUPPCState *env = &cpu->env; 813 814 if (msr_pr) { 815 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 816 env->gpr[3] = H_PRIVILEGE; 817 } else { 818 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 819 } 820 } 821 822 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 823 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 824 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 825 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 826 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 827 828 static void spapr_reset_htab(sPAPREnvironment *spapr) 829 { 830 long shift; 831 int index; 832 833 /* allocate hash page table. For now we always make this 16mb, 834 * later we should probably make it scale to the size of guest 835 * RAM */ 836 837 shift = kvmppc_reset_htab(spapr->htab_shift); 838 839 if (shift > 0) { 840 /* Kernel handles htab, we don't need to allocate one */ 841 spapr->htab_shift = shift; 842 kvmppc_kern_htab = true; 843 844 /* Tell readers to update their file descriptor */ 845 if (spapr->htab_fd >= 0) { 846 spapr->htab_fd_stale = true; 847 } 848 } else { 849 if (!spapr->htab) { 850 /* Allocate an htab if we don't yet have one */ 851 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr)); 852 } 853 854 /* And clear it */ 855 memset(spapr->htab, 0, HTAB_SIZE(spapr)); 856 857 for (index = 0; index < HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; index++) { 858 DIRTY_HPTE(HPTE(spapr->htab, index)); 859 } 860 } 861 862 /* Update the RMA size if necessary */ 863 if (spapr->vrma_adjust) { 864 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 865 spapr->htab_shift); 866 } 867 } 868 869 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 870 { 871 bool matched = false; 872 873 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 874 matched = true; 875 } 876 877 if (!matched) { 878 error_report("Device %s is not supported by this machine yet.", 879 qdev_fw_name(DEVICE(sbdev))); 880 exit(1); 881 } 882 883 return 0; 884 } 885 886 /* 887 * A guest reset will cause spapr->htab_fd to become stale if being used. 888 * Reopen the file descriptor to make sure the whole HTAB is properly read. 889 */ 890 static int spapr_check_htab_fd(sPAPREnvironment *spapr) 891 { 892 int rc = 0; 893 894 if (spapr->htab_fd_stale) { 895 close(spapr->htab_fd); 896 spapr->htab_fd = kvmppc_get_htab_fd(false); 897 if (spapr->htab_fd < 0) { 898 error_report("Unable to open fd for reading hash table from KVM: " 899 "%s", strerror(errno)); 900 rc = -1; 901 } 902 spapr->htab_fd_stale = false; 903 } 904 905 return rc; 906 } 907 908 static void ppc_spapr_reset(void) 909 { 910 PowerPCCPU *first_ppc_cpu; 911 uint32_t rtas_limit; 912 913 /* Check for unknown sysbus devices */ 914 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 915 916 /* Reset the hash table & recalc the RMA */ 917 spapr_reset_htab(spapr); 918 919 qemu_devices_reset(); 920 921 /* 922 * We place the device tree and RTAS just below either the top of the RMA, 923 * or just below 2GB, whichever is lowere, so that it can be 924 * processed with 32-bit real mode code if necessary 925 */ 926 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 927 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 928 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 929 930 /* Load the fdt */ 931 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 932 spapr->rtas_size); 933 934 /* Copy RTAS over */ 935 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 936 spapr->rtas_size); 937 938 /* Set up the entry state */ 939 first_ppc_cpu = POWERPC_CPU(first_cpu); 940 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 941 first_ppc_cpu->env.gpr[5] = 0; 942 first_cpu->halted = 0; 943 first_ppc_cpu->env.nip = spapr->entry_point; 944 945 } 946 947 static void spapr_cpu_reset(void *opaque) 948 { 949 PowerPCCPU *cpu = opaque; 950 CPUState *cs = CPU(cpu); 951 CPUPPCState *env = &cpu->env; 952 953 cpu_reset(cs); 954 955 /* All CPUs start halted. CPU0 is unhalted from the machine level 956 * reset code and the rest are explicitly started up by the guest 957 * using an RTAS call */ 958 cs->halted = 1; 959 960 env->spr[SPR_HIOR] = 0; 961 962 env->external_htab = (uint8_t *)spapr->htab; 963 if (kvm_enabled() && !env->external_htab) { 964 /* 965 * HV KVM, set external_htab to 1 so our ppc_hash64_load_hpte* 966 * functions do the right thing. 967 */ 968 env->external_htab = (void *)1; 969 } 970 env->htab_base = -1; 971 /* 972 * htab_mask is the mask used to normalize hash value to PTEG index. 973 * htab_shift is log2 of hash table size. 974 * We have 8 hpte per group, and each hpte is 16 bytes. 975 * ie have 128 bytes per hpte entry. 976 */ 977 env->htab_mask = (1ULL << ((spapr)->htab_shift - 7)) - 1; 978 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 979 (spapr->htab_shift - 18); 980 } 981 982 static void spapr_create_nvram(sPAPREnvironment *spapr) 983 { 984 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 985 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 986 987 if (dinfo) { 988 qdev_prop_set_drive_nofail(dev, "drive", blk_by_legacy_dinfo(dinfo)); 989 } 990 991 qdev_init_nofail(dev); 992 993 spapr->nvram = (struct sPAPRNVRAM *)dev; 994 } 995 996 /* Returns whether we want to use VGA or not */ 997 static int spapr_vga_init(PCIBus *pci_bus) 998 { 999 switch (vga_interface_type) { 1000 case VGA_NONE: 1001 return false; 1002 case VGA_DEVICE: 1003 return true; 1004 case VGA_STD: 1005 return pci_vga_init(pci_bus) != NULL; 1006 default: 1007 fprintf(stderr, "This vga model is not supported," 1008 "currently it only supports -vga std\n"); 1009 exit(0); 1010 } 1011 } 1012 1013 static const VMStateDescription vmstate_spapr = { 1014 .name = "spapr", 1015 .version_id = 2, 1016 .minimum_version_id = 1, 1017 .fields = (VMStateField[]) { 1018 VMSTATE_UNUSED(4), /* used to be @next_irq */ 1019 1020 /* RTC offset */ 1021 VMSTATE_UINT64(rtc_offset, sPAPREnvironment), 1022 VMSTATE_PPC_TIMEBASE_V(tb, sPAPREnvironment, 2), 1023 VMSTATE_END_OF_LIST() 1024 }, 1025 }; 1026 1027 static int htab_save_setup(QEMUFile *f, void *opaque) 1028 { 1029 sPAPREnvironment *spapr = opaque; 1030 1031 /* "Iteration" header */ 1032 qemu_put_be32(f, spapr->htab_shift); 1033 1034 if (spapr->htab) { 1035 spapr->htab_save_index = 0; 1036 spapr->htab_first_pass = true; 1037 } else { 1038 assert(kvm_enabled()); 1039 1040 spapr->htab_fd = kvmppc_get_htab_fd(false); 1041 spapr->htab_fd_stale = false; 1042 if (spapr->htab_fd < 0) { 1043 fprintf(stderr, "Unable to open fd for reading hash table from KVM: %s\n", 1044 strerror(errno)); 1045 return -1; 1046 } 1047 } 1048 1049 1050 return 0; 1051 } 1052 1053 static void htab_save_first_pass(QEMUFile *f, sPAPREnvironment *spapr, 1054 int64_t max_ns) 1055 { 1056 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1057 int index = spapr->htab_save_index; 1058 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1059 1060 assert(spapr->htab_first_pass); 1061 1062 do { 1063 int chunkstart; 1064 1065 /* Consume invalid HPTEs */ 1066 while ((index < htabslots) 1067 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1068 index++; 1069 CLEAN_HPTE(HPTE(spapr->htab, index)); 1070 } 1071 1072 /* Consume valid HPTEs */ 1073 chunkstart = index; 1074 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1075 && HPTE_VALID(HPTE(spapr->htab, index))) { 1076 index++; 1077 CLEAN_HPTE(HPTE(spapr->htab, index)); 1078 } 1079 1080 if (index > chunkstart) { 1081 int n_valid = index - chunkstart; 1082 1083 qemu_put_be32(f, chunkstart); 1084 qemu_put_be16(f, n_valid); 1085 qemu_put_be16(f, 0); 1086 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1087 HASH_PTE_SIZE_64 * n_valid); 1088 1089 if ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1090 break; 1091 } 1092 } 1093 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1094 1095 if (index >= htabslots) { 1096 assert(index == htabslots); 1097 index = 0; 1098 spapr->htab_first_pass = false; 1099 } 1100 spapr->htab_save_index = index; 1101 } 1102 1103 static int htab_save_later_pass(QEMUFile *f, sPAPREnvironment *spapr, 1104 int64_t max_ns) 1105 { 1106 bool final = max_ns < 0; 1107 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1108 int examined = 0, sent = 0; 1109 int index = spapr->htab_save_index; 1110 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1111 1112 assert(!spapr->htab_first_pass); 1113 1114 do { 1115 int chunkstart, invalidstart; 1116 1117 /* Consume non-dirty HPTEs */ 1118 while ((index < htabslots) 1119 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1120 index++; 1121 examined++; 1122 } 1123 1124 chunkstart = index; 1125 /* Consume valid dirty HPTEs */ 1126 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1127 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1128 && HPTE_VALID(HPTE(spapr->htab, index))) { 1129 CLEAN_HPTE(HPTE(spapr->htab, index)); 1130 index++; 1131 examined++; 1132 } 1133 1134 invalidstart = index; 1135 /* Consume invalid dirty HPTEs */ 1136 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1137 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1138 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1139 CLEAN_HPTE(HPTE(spapr->htab, index)); 1140 index++; 1141 examined++; 1142 } 1143 1144 if (index > chunkstart) { 1145 int n_valid = invalidstart - chunkstart; 1146 int n_invalid = index - invalidstart; 1147 1148 qemu_put_be32(f, chunkstart); 1149 qemu_put_be16(f, n_valid); 1150 qemu_put_be16(f, n_invalid); 1151 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1152 HASH_PTE_SIZE_64 * n_valid); 1153 sent += index - chunkstart; 1154 1155 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1156 break; 1157 } 1158 } 1159 1160 if (examined >= htabslots) { 1161 break; 1162 } 1163 1164 if (index >= htabslots) { 1165 assert(index == htabslots); 1166 index = 0; 1167 } 1168 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1169 1170 if (index >= htabslots) { 1171 assert(index == htabslots); 1172 index = 0; 1173 } 1174 1175 spapr->htab_save_index = index; 1176 1177 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1178 } 1179 1180 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1181 #define MAX_KVM_BUF_SIZE 2048 1182 1183 static int htab_save_iterate(QEMUFile *f, void *opaque) 1184 { 1185 sPAPREnvironment *spapr = opaque; 1186 int rc = 0; 1187 1188 /* Iteration header */ 1189 qemu_put_be32(f, 0); 1190 1191 if (!spapr->htab) { 1192 assert(kvm_enabled()); 1193 1194 rc = spapr_check_htab_fd(spapr); 1195 if (rc < 0) { 1196 return rc; 1197 } 1198 1199 rc = kvmppc_save_htab(f, spapr->htab_fd, 1200 MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1201 if (rc < 0) { 1202 return rc; 1203 } 1204 } else if (spapr->htab_first_pass) { 1205 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1206 } else { 1207 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1208 } 1209 1210 /* End marker */ 1211 qemu_put_be32(f, 0); 1212 qemu_put_be16(f, 0); 1213 qemu_put_be16(f, 0); 1214 1215 return rc; 1216 } 1217 1218 static int htab_save_complete(QEMUFile *f, void *opaque) 1219 { 1220 sPAPREnvironment *spapr = opaque; 1221 1222 /* Iteration header */ 1223 qemu_put_be32(f, 0); 1224 1225 if (!spapr->htab) { 1226 int rc; 1227 1228 assert(kvm_enabled()); 1229 1230 rc = spapr_check_htab_fd(spapr); 1231 if (rc < 0) { 1232 return rc; 1233 } 1234 1235 rc = kvmppc_save_htab(f, spapr->htab_fd, MAX_KVM_BUF_SIZE, -1); 1236 if (rc < 0) { 1237 return rc; 1238 } 1239 close(spapr->htab_fd); 1240 spapr->htab_fd = -1; 1241 } else { 1242 htab_save_later_pass(f, spapr, -1); 1243 } 1244 1245 /* End marker */ 1246 qemu_put_be32(f, 0); 1247 qemu_put_be16(f, 0); 1248 qemu_put_be16(f, 0); 1249 1250 return 0; 1251 } 1252 1253 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1254 { 1255 sPAPREnvironment *spapr = opaque; 1256 uint32_t section_hdr; 1257 int fd = -1; 1258 1259 if (version_id < 1 || version_id > 1) { 1260 fprintf(stderr, "htab_load() bad version\n"); 1261 return -EINVAL; 1262 } 1263 1264 section_hdr = qemu_get_be32(f); 1265 1266 if (section_hdr) { 1267 /* First section, just the hash shift */ 1268 if (spapr->htab_shift != section_hdr) { 1269 return -EINVAL; 1270 } 1271 return 0; 1272 } 1273 1274 if (!spapr->htab) { 1275 assert(kvm_enabled()); 1276 1277 fd = kvmppc_get_htab_fd(true); 1278 if (fd < 0) { 1279 fprintf(stderr, "Unable to open fd to restore KVM hash table: %s\n", 1280 strerror(errno)); 1281 } 1282 } 1283 1284 while (true) { 1285 uint32_t index; 1286 uint16_t n_valid, n_invalid; 1287 1288 index = qemu_get_be32(f); 1289 n_valid = qemu_get_be16(f); 1290 n_invalid = qemu_get_be16(f); 1291 1292 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1293 /* End of Stream */ 1294 break; 1295 } 1296 1297 if ((index + n_valid + n_invalid) > 1298 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1299 /* Bad index in stream */ 1300 fprintf(stderr, "htab_load() bad index %d (%hd+%hd entries) " 1301 "in htab stream (htab_shift=%d)\n", index, n_valid, n_invalid, 1302 spapr->htab_shift); 1303 return -EINVAL; 1304 } 1305 1306 if (spapr->htab) { 1307 if (n_valid) { 1308 qemu_get_buffer(f, HPTE(spapr->htab, index), 1309 HASH_PTE_SIZE_64 * n_valid); 1310 } 1311 if (n_invalid) { 1312 memset(HPTE(spapr->htab, index + n_valid), 0, 1313 HASH_PTE_SIZE_64 * n_invalid); 1314 } 1315 } else { 1316 int rc; 1317 1318 assert(fd >= 0); 1319 1320 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1321 if (rc < 0) { 1322 return rc; 1323 } 1324 } 1325 } 1326 1327 if (!spapr->htab) { 1328 assert(fd >= 0); 1329 close(fd); 1330 } 1331 1332 return 0; 1333 } 1334 1335 static SaveVMHandlers savevm_htab_handlers = { 1336 .save_live_setup = htab_save_setup, 1337 .save_live_iterate = htab_save_iterate, 1338 .save_live_complete = htab_save_complete, 1339 .load_state = htab_load, 1340 }; 1341 1342 /* pSeries LPAR / sPAPR hardware init */ 1343 static void ppc_spapr_init(MachineState *machine) 1344 { 1345 ram_addr_t ram_size = machine->ram_size; 1346 const char *cpu_model = machine->cpu_model; 1347 const char *kernel_filename = machine->kernel_filename; 1348 const char *kernel_cmdline = machine->kernel_cmdline; 1349 const char *initrd_filename = machine->initrd_filename; 1350 const char *boot_device = machine->boot_order; 1351 PowerPCCPU *cpu; 1352 CPUPPCState *env; 1353 PCIHostState *phb; 1354 int i; 1355 MemoryRegion *sysmem = get_system_memory(); 1356 MemoryRegion *ram = g_new(MemoryRegion, 1); 1357 MemoryRegion *rma_region; 1358 void *rma = NULL; 1359 hwaddr rma_alloc_size; 1360 hwaddr node0_size = spapr_node0_size(); 1361 uint32_t initrd_base = 0; 1362 long kernel_size = 0, initrd_size = 0; 1363 long load_limit, fw_size; 1364 bool kernel_le = false; 1365 char *filename; 1366 1367 msi_supported = true; 1368 1369 spapr = g_malloc0(sizeof(*spapr)); 1370 QLIST_INIT(&spapr->phbs); 1371 1372 cpu_ppc_hypercall = emulate_spapr_hypercall; 1373 1374 /* Allocate RMA if necessary */ 1375 rma_alloc_size = kvmppc_alloc_rma(&rma); 1376 1377 if (rma_alloc_size == -1) { 1378 hw_error("qemu: Unable to create RMA\n"); 1379 exit(1); 1380 } 1381 1382 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1383 spapr->rma_size = rma_alloc_size; 1384 } else { 1385 spapr->rma_size = node0_size; 1386 1387 /* With KVM, we don't actually know whether KVM supports an 1388 * unbounded RMA (PR KVM) or is limited by the hash table size 1389 * (HV KVM using VRMA), so we always assume the latter 1390 * 1391 * In that case, we also limit the initial allocations for RTAS 1392 * etc... to 256M since we have no way to know what the VRMA size 1393 * is going to be as it depends on the size of the hash table 1394 * isn't determined yet. 1395 */ 1396 if (kvm_enabled()) { 1397 spapr->vrma_adjust = 1; 1398 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1399 } 1400 } 1401 1402 if (spapr->rma_size > node0_size) { 1403 fprintf(stderr, "Error: Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")\n", 1404 spapr->rma_size); 1405 exit(1); 1406 } 1407 1408 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1409 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1410 1411 /* We aim for a hash table of size 1/128 the size of RAM. The 1412 * normal rule of thumb is 1/64 the size of RAM, but that's much 1413 * more than needed for the Linux guests we support. */ 1414 spapr->htab_shift = 18; /* Minimum architected size */ 1415 while (spapr->htab_shift <= 46) { 1416 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) { 1417 break; 1418 } 1419 spapr->htab_shift++; 1420 } 1421 1422 /* Set up Interrupt Controller before we create the VCPUs */ 1423 spapr->icp = xics_system_init(smp_cpus * kvmppc_smt_threads() / smp_threads, 1424 XICS_IRQS); 1425 1426 /* init CPUs */ 1427 if (cpu_model == NULL) { 1428 cpu_model = kvm_enabled() ? "host" : "POWER7"; 1429 } 1430 for (i = 0; i < smp_cpus; i++) { 1431 cpu = cpu_ppc_init(cpu_model); 1432 if (cpu == NULL) { 1433 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 1434 exit(1); 1435 } 1436 env = &cpu->env; 1437 1438 /* Set time-base frequency to 512 MHz */ 1439 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1440 1441 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1442 * MSR[IP] should never be set. 1443 */ 1444 env->msr_mask &= ~(1 << 6); 1445 1446 /* Tell KVM that we're in PAPR mode */ 1447 if (kvm_enabled()) { 1448 kvmppc_set_papr(cpu); 1449 } 1450 1451 if (cpu->max_compat) { 1452 if (ppc_set_compat(cpu, cpu->max_compat) < 0) { 1453 exit(1); 1454 } 1455 } 1456 1457 xics_cpu_setup(spapr->icp, cpu); 1458 1459 qemu_register_reset(spapr_cpu_reset, cpu); 1460 } 1461 1462 /* allocate RAM */ 1463 spapr->ram_limit = ram_size; 1464 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1465 spapr->ram_limit); 1466 memory_region_add_subregion(sysmem, 0, ram); 1467 1468 if (rma_alloc_size && rma) { 1469 rma_region = g_new(MemoryRegion, 1); 1470 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1471 rma_alloc_size, rma); 1472 vmstate_register_ram_global(rma_region); 1473 memory_region_add_subregion(sysmem, 0, rma_region); 1474 } 1475 1476 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1477 spapr->rtas_size = get_image_size(filename); 1478 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1479 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1480 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1481 exit(1); 1482 } 1483 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1484 hw_error("RTAS too big ! 0x%zx bytes (max is 0x%x)\n", 1485 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1486 exit(1); 1487 } 1488 g_free(filename); 1489 1490 /* Set up EPOW events infrastructure */ 1491 spapr_events_init(spapr); 1492 1493 /* Set up VIO bus */ 1494 spapr->vio_bus = spapr_vio_bus_init(); 1495 1496 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1497 if (serial_hds[i]) { 1498 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1499 } 1500 } 1501 1502 /* We always have at least the nvram device on VIO */ 1503 spapr_create_nvram(spapr); 1504 1505 /* Set up PCI */ 1506 spapr_pci_rtas_init(); 1507 1508 phb = spapr_create_phb(spapr, 0); 1509 1510 for (i = 0; i < nb_nics; i++) { 1511 NICInfo *nd = &nd_table[i]; 1512 1513 if (!nd->model) { 1514 nd->model = g_strdup("ibmveth"); 1515 } 1516 1517 if (strcmp(nd->model, "ibmveth") == 0) { 1518 spapr_vlan_create(spapr->vio_bus, nd); 1519 } else { 1520 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1521 } 1522 } 1523 1524 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1525 spapr_vscsi_create(spapr->vio_bus); 1526 } 1527 1528 /* Graphics */ 1529 if (spapr_vga_init(phb->bus)) { 1530 spapr->has_graphics = true; 1531 machine->usb |= defaults_enabled(); 1532 } 1533 1534 if (machine->usb) { 1535 pci_create_simple(phb->bus, -1, "pci-ohci"); 1536 1537 if (spapr->has_graphics) { 1538 USBBus *usb_bus = usb_bus_find(-1); 1539 1540 usb_create_simple(usb_bus, "usb-kbd"); 1541 usb_create_simple(usb_bus, "usb-mouse"); 1542 } 1543 } 1544 1545 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1546 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " 1547 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF); 1548 exit(1); 1549 } 1550 1551 if (kernel_filename) { 1552 uint64_t lowaddr = 0; 1553 1554 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1555 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 1556 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1557 kernel_size = load_elf(kernel_filename, 1558 translate_kernel_address, NULL, 1559 NULL, &lowaddr, NULL, 0, ELF_MACHINE, 0); 1560 kernel_le = kernel_size > 0; 1561 } 1562 if (kernel_size < 0) { 1563 fprintf(stderr, "qemu: error loading %s: %s\n", 1564 kernel_filename, load_elf_strerror(kernel_size)); 1565 exit(1); 1566 } 1567 1568 /* load initrd */ 1569 if (initrd_filename) { 1570 /* Try to locate the initrd in the gap between the kernel 1571 * and the firmware. Add a bit of space just in case 1572 */ 1573 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1574 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1575 load_limit - initrd_base); 1576 if (initrd_size < 0) { 1577 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 1578 initrd_filename); 1579 exit(1); 1580 } 1581 } else { 1582 initrd_base = 0; 1583 initrd_size = 0; 1584 } 1585 } 1586 1587 if (bios_name == NULL) { 1588 bios_name = FW_FILE_NAME; 1589 } 1590 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1591 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1592 if (fw_size < 0) { 1593 hw_error("qemu: could not load LPAR rtas '%s'\n", filename); 1594 exit(1); 1595 } 1596 g_free(filename); 1597 1598 spapr->entry_point = 0x100; 1599 1600 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1601 register_savevm_live(NULL, "spapr/htab", -1, 1, 1602 &savevm_htab_handlers, spapr); 1603 1604 /* Prepare the device tree */ 1605 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 1606 kernel_size, kernel_le, 1607 boot_device, kernel_cmdline, 1608 spapr->epow_irq); 1609 assert(spapr->fdt_skel != NULL); 1610 } 1611 1612 static int spapr_kvm_type(const char *vm_type) 1613 { 1614 if (!vm_type) { 1615 return 0; 1616 } 1617 1618 if (!strcmp(vm_type, "HV")) { 1619 return 1; 1620 } 1621 1622 if (!strcmp(vm_type, "PR")) { 1623 return 2; 1624 } 1625 1626 error_report("Unknown kvm-type specified '%s'", vm_type); 1627 exit(1); 1628 } 1629 1630 /* 1631 * Implementation of an interface to adjust firmware path 1632 * for the bootindex property handling. 1633 */ 1634 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 1635 DeviceState *dev) 1636 { 1637 #define CAST(type, obj, name) \ 1638 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 1639 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 1640 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 1641 1642 if (d) { 1643 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 1644 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 1645 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 1646 1647 if (spapr) { 1648 /* 1649 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 1650 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 1651 * in the top 16 bits of the 64-bit LUN 1652 */ 1653 unsigned id = 0x8000 | (d->id << 8) | d->lun; 1654 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1655 (uint64_t)id << 48); 1656 } else if (virtio) { 1657 /* 1658 * We use SRP luns of the form 01000000 | (target << 8) | lun 1659 * in the top 32 bits of the 64-bit LUN 1660 * Note: the quote above is from SLOF and it is wrong, 1661 * the actual binding is: 1662 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 1663 */ 1664 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 1665 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1666 (uint64_t)id << 32); 1667 } else if (usb) { 1668 /* 1669 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 1670 * in the top 32 bits of the 64-bit LUN 1671 */ 1672 unsigned usb_port = atoi(usb->port->path); 1673 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 1674 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 1675 (uint64_t)id << 32); 1676 } 1677 } 1678 1679 if (phb) { 1680 /* Replace "pci" with "pci@800000020000000" */ 1681 return g_strdup_printf("pci@%"PRIX64, phb->buid); 1682 } 1683 1684 return NULL; 1685 } 1686 1687 static char *spapr_get_kvm_type(Object *obj, Error **errp) 1688 { 1689 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1690 1691 return g_strdup(sm->kvm_type); 1692 } 1693 1694 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 1695 { 1696 sPAPRMachineState *sm = SPAPR_MACHINE(obj); 1697 1698 g_free(sm->kvm_type); 1699 sm->kvm_type = g_strdup(value); 1700 } 1701 1702 static void spapr_machine_initfn(Object *obj) 1703 { 1704 object_property_add_str(obj, "kvm-type", 1705 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 1706 object_property_set_description(obj, "kvm-type", 1707 "Specifies the KVM virtualization mode (HV, PR)", 1708 NULL); 1709 } 1710 1711 static void ppc_cpu_do_nmi_on_cpu(void *arg) 1712 { 1713 CPUState *cs = arg; 1714 1715 cpu_synchronize_state(cs); 1716 ppc_cpu_do_system_reset(cs); 1717 } 1718 1719 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 1720 { 1721 CPUState *cs; 1722 1723 CPU_FOREACH(cs) { 1724 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 1725 } 1726 } 1727 1728 static void spapr_machine_class_init(ObjectClass *oc, void *data) 1729 { 1730 MachineClass *mc = MACHINE_CLASS(oc); 1731 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 1732 NMIClass *nc = NMI_CLASS(oc); 1733 1734 mc->init = ppc_spapr_init; 1735 mc->reset = ppc_spapr_reset; 1736 mc->block_default_type = IF_SCSI; 1737 mc->max_cpus = MAX_CPUS; 1738 mc->no_parallel = 1; 1739 mc->default_boot_order = NULL; 1740 mc->kvm_type = spapr_kvm_type; 1741 mc->has_dynamic_sysbus = true; 1742 1743 fwc->get_dev_path = spapr_get_fw_dev_path; 1744 nc->nmi_monitor_handler = spapr_nmi; 1745 } 1746 1747 static const TypeInfo spapr_machine_info = { 1748 .name = TYPE_SPAPR_MACHINE, 1749 .parent = TYPE_MACHINE, 1750 .abstract = true, 1751 .instance_size = sizeof(sPAPRMachineState), 1752 .instance_init = spapr_machine_initfn, 1753 .class_init = spapr_machine_class_init, 1754 .interfaces = (InterfaceInfo[]) { 1755 { TYPE_FW_PATH_PROVIDER }, 1756 { TYPE_NMI }, 1757 { } 1758 }, 1759 }; 1760 1761 static void spapr_machine_2_1_class_init(ObjectClass *oc, void *data) 1762 { 1763 MachineClass *mc = MACHINE_CLASS(oc); 1764 static GlobalProperty compat_props[] = { 1765 HW_COMPAT_2_1, 1766 { /* end of list */ } 1767 }; 1768 1769 mc->name = "pseries-2.1"; 1770 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.1"; 1771 mc->compat_props = compat_props; 1772 } 1773 1774 static const TypeInfo spapr_machine_2_1_info = { 1775 .name = TYPE_SPAPR_MACHINE "2.1", 1776 .parent = TYPE_SPAPR_MACHINE, 1777 .class_init = spapr_machine_2_1_class_init, 1778 }; 1779 1780 static void spapr_machine_2_2_class_init(ObjectClass *oc, void *data) 1781 { 1782 MachineClass *mc = MACHINE_CLASS(oc); 1783 1784 mc->name = "pseries-2.2"; 1785 mc->desc = "pSeries Logical Partition (PAPR compliant) v2.2"; 1786 mc->alias = "pseries"; 1787 mc->is_default = 1; 1788 } 1789 1790 static const TypeInfo spapr_machine_2_2_info = { 1791 .name = TYPE_SPAPR_MACHINE "2.2", 1792 .parent = TYPE_SPAPR_MACHINE, 1793 .class_init = spapr_machine_2_2_class_init, 1794 }; 1795 1796 static void spapr_machine_register_types(void) 1797 { 1798 type_register_static(&spapr_machine_info); 1799 type_register_static(&spapr_machine_2_1_info); 1800 type_register_static(&spapr_machine_2_2_info); 1801 } 1802 1803 type_init(spapr_machine_register_types) 1804