1 /* 2 * QEMU PowerPC 440 embedded processors emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2018 BALATON Zoltan 6 * 7 * This work is licensed under the GNU GPL license version 2 or later. 8 * 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qemu-common.h" 13 #include "qemu/cutils.h" 14 #include "qemu/error-report.h" 15 #include "qapi/error.h" 16 #include "cpu.h" 17 #include "hw/hw.h" 18 #include "exec/address-spaces.h" 19 #include "exec/memory.h" 20 #include "hw/ppc/ppc.h" 21 #include "hw/pci/pci.h" 22 #include "sysemu/block-backend.h" 23 #include "hw/ppc/ppc440.h" 24 25 /*****************************************************************************/ 26 /* L2 Cache as SRAM */ 27 /* FIXME:fix names */ 28 enum { 29 DCR_L2CACHE_BASE = 0x30, 30 DCR_L2CACHE_CFG = DCR_L2CACHE_BASE, 31 DCR_L2CACHE_CMD, 32 DCR_L2CACHE_ADDR, 33 DCR_L2CACHE_DATA, 34 DCR_L2CACHE_STAT, 35 DCR_L2CACHE_CVER, 36 DCR_L2CACHE_SNP0, 37 DCR_L2CACHE_SNP1, 38 DCR_L2CACHE_END = DCR_L2CACHE_SNP1, 39 }; 40 41 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */ 42 enum { 43 DCR_ISRAM0_BASE = 0x20, 44 DCR_ISRAM0_SB0CR = DCR_ISRAM0_BASE, 45 DCR_ISRAM0_SB1CR, 46 DCR_ISRAM0_SB2CR, 47 DCR_ISRAM0_SB3CR, 48 DCR_ISRAM0_BEAR, 49 DCR_ISRAM0_BESR0, 50 DCR_ISRAM0_BESR1, 51 DCR_ISRAM0_PMEG, 52 DCR_ISRAM0_CID, 53 DCR_ISRAM0_REVID, 54 DCR_ISRAM0_DPC, 55 DCR_ISRAM0_END = DCR_ISRAM0_DPC 56 }; 57 58 enum { 59 DCR_ISRAM1_BASE = 0xb0, 60 DCR_ISRAM1_SB0CR = DCR_ISRAM1_BASE, 61 /* single bank */ 62 DCR_ISRAM1_BEAR = DCR_ISRAM1_BASE + 0x04, 63 DCR_ISRAM1_BESR0, 64 DCR_ISRAM1_BESR1, 65 DCR_ISRAM1_PMEG, 66 DCR_ISRAM1_CID, 67 DCR_ISRAM1_REVID, 68 DCR_ISRAM1_DPC, 69 DCR_ISRAM1_END = DCR_ISRAM1_DPC 70 }; 71 72 typedef struct ppc4xx_l2sram_t { 73 MemoryRegion bank[4]; 74 uint32_t l2cache[8]; 75 uint32_t isram0[11]; 76 } ppc4xx_l2sram_t; 77 78 #ifdef MAP_L2SRAM 79 static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram, 80 uint32_t isarc, uint32_t isacntl, 81 uint32_t dsarc, uint32_t dsacntl) 82 { 83 if (l2sram->isarc != isarc || 84 (l2sram->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 85 if (l2sram->isacntl & 0x80000000) { 86 /* Unmap previously assigned memory region */ 87 memory_region_del_subregion(get_system_memory(), 88 &l2sram->isarc_ram); 89 } 90 if (isacntl & 0x80000000) { 91 /* Map new instruction memory region */ 92 memory_region_add_subregion(get_system_memory(), isarc, 93 &l2sram->isarc_ram); 94 } 95 } 96 if (l2sram->dsarc != dsarc || 97 (l2sram->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 98 if (l2sram->dsacntl & 0x80000000) { 99 /* Beware not to unmap the region we just mapped */ 100 if (!(isacntl & 0x80000000) || l2sram->dsarc != isarc) { 101 /* Unmap previously assigned memory region */ 102 memory_region_del_subregion(get_system_memory(), 103 &l2sram->dsarc_ram); 104 } 105 } 106 if (dsacntl & 0x80000000) { 107 /* Beware not to remap the region we just mapped */ 108 if (!(isacntl & 0x80000000) || dsarc != isarc) { 109 /* Map new data memory region */ 110 memory_region_add_subregion(get_system_memory(), dsarc, 111 &l2sram->dsarc_ram); 112 } 113 } 114 } 115 } 116 #endif 117 118 static uint32_t dcr_read_l2sram(void *opaque, int dcrn) 119 { 120 ppc4xx_l2sram_t *l2sram = opaque; 121 uint32_t ret = 0; 122 123 switch (dcrn) { 124 case DCR_L2CACHE_CFG: 125 case DCR_L2CACHE_CMD: 126 case DCR_L2CACHE_ADDR: 127 case DCR_L2CACHE_DATA: 128 case DCR_L2CACHE_STAT: 129 case DCR_L2CACHE_CVER: 130 case DCR_L2CACHE_SNP0: 131 case DCR_L2CACHE_SNP1: 132 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; 133 break; 134 135 case DCR_ISRAM0_SB0CR: 136 case DCR_ISRAM0_SB1CR: 137 case DCR_ISRAM0_SB2CR: 138 case DCR_ISRAM0_SB3CR: 139 case DCR_ISRAM0_BEAR: 140 case DCR_ISRAM0_BESR0: 141 case DCR_ISRAM0_BESR1: 142 case DCR_ISRAM0_PMEG: 143 case DCR_ISRAM0_CID: 144 case DCR_ISRAM0_REVID: 145 case DCR_ISRAM0_DPC: 146 ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; 147 break; 148 149 default: 150 break; 151 } 152 153 return ret; 154 } 155 156 static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val) 157 { 158 /*ppc4xx_l2sram_t *l2sram = opaque;*/ 159 /* FIXME: Actually handle L2 cache mapping */ 160 161 switch (dcrn) { 162 case DCR_L2CACHE_CFG: 163 case DCR_L2CACHE_CMD: 164 case DCR_L2CACHE_ADDR: 165 case DCR_L2CACHE_DATA: 166 case DCR_L2CACHE_STAT: 167 case DCR_L2CACHE_CVER: 168 case DCR_L2CACHE_SNP0: 169 case DCR_L2CACHE_SNP1: 170 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/ 171 break; 172 173 case DCR_ISRAM0_SB0CR: 174 case DCR_ISRAM0_SB1CR: 175 case DCR_ISRAM0_SB2CR: 176 case DCR_ISRAM0_SB3CR: 177 case DCR_ISRAM0_BEAR: 178 case DCR_ISRAM0_BESR0: 179 case DCR_ISRAM0_BESR1: 180 case DCR_ISRAM0_PMEG: 181 case DCR_ISRAM0_CID: 182 case DCR_ISRAM0_REVID: 183 case DCR_ISRAM0_DPC: 184 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/ 185 break; 186 187 case DCR_ISRAM1_SB0CR: 188 case DCR_ISRAM1_BEAR: 189 case DCR_ISRAM1_BESR0: 190 case DCR_ISRAM1_BESR1: 191 case DCR_ISRAM1_PMEG: 192 case DCR_ISRAM1_CID: 193 case DCR_ISRAM1_REVID: 194 case DCR_ISRAM1_DPC: 195 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/ 196 break; 197 } 198 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ 199 } 200 201 static void l2sram_reset(void *opaque) 202 { 203 ppc4xx_l2sram_t *l2sram = opaque; 204 205 memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache)); 206 l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000; 207 memset(l2sram->isram0, 0, sizeof(l2sram->isram0)); 208 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ 209 } 210 211 void ppc4xx_l2sram_init(CPUPPCState *env) 212 { 213 ppc4xx_l2sram_t *l2sram; 214 215 l2sram = g_malloc0(sizeof(*l2sram)); 216 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */ 217 memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", 218 64 * K_BYTE, &error_abort); 219 memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", 220 64 * K_BYTE, &error_abort); 221 memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", 222 64 * K_BYTE, &error_abort); 223 memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", 224 64 * K_BYTE, &error_abort); 225 qemu_register_reset(&l2sram_reset, l2sram); 226 ppc_dcr_register(env, DCR_L2CACHE_CFG, 227 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 228 ppc_dcr_register(env, DCR_L2CACHE_CMD, 229 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 230 ppc_dcr_register(env, DCR_L2CACHE_ADDR, 231 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 232 ppc_dcr_register(env, DCR_L2CACHE_DATA, 233 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 234 ppc_dcr_register(env, DCR_L2CACHE_STAT, 235 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 236 ppc_dcr_register(env, DCR_L2CACHE_CVER, 237 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 238 ppc_dcr_register(env, DCR_L2CACHE_SNP0, 239 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 240 ppc_dcr_register(env, DCR_L2CACHE_SNP1, 241 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 242 243 ppc_dcr_register(env, DCR_ISRAM0_SB0CR, 244 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 245 ppc_dcr_register(env, DCR_ISRAM0_SB1CR, 246 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 247 ppc_dcr_register(env, DCR_ISRAM0_SB2CR, 248 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 249 ppc_dcr_register(env, DCR_ISRAM0_SB3CR, 250 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 251 ppc_dcr_register(env, DCR_ISRAM0_PMEG, 252 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 253 ppc_dcr_register(env, DCR_ISRAM0_DPC, 254 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 255 256 ppc_dcr_register(env, DCR_ISRAM1_SB0CR, 257 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 258 ppc_dcr_register(env, DCR_ISRAM1_PMEG, 259 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 260 ppc_dcr_register(env, DCR_ISRAM1_DPC, 261 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 262 } 263 264 /*****************************************************************************/ 265 /* Clocking Power on Reset */ 266 enum { 267 CPR0_CFGADDR = 0xC, 268 CPR0_CFGDATA = 0xD, 269 270 CPR0_PLLD = 0x060, 271 CPR0_PLBED = 0x080, 272 CPR0_OPBD = 0x0C0, 273 CPR0_PERD = 0x0E0, 274 CPR0_AHBD = 0x100, 275 }; 276 277 typedef struct ppc4xx_cpr_t { 278 uint32_t addr; 279 } ppc4xx_cpr_t; 280 281 static uint32_t dcr_read_cpr(void *opaque, int dcrn) 282 { 283 ppc4xx_cpr_t *cpr = opaque; 284 uint32_t ret = 0; 285 286 switch (dcrn) { 287 case CPR0_CFGADDR: 288 ret = cpr->addr; 289 break; 290 case CPR0_CFGDATA: 291 switch (cpr->addr) { 292 case CPR0_PLLD: 293 ret = (0xb5 << 24) | (1 << 16) | (9 << 8); 294 break; 295 case CPR0_PLBED: 296 ret = (5 << 24); 297 break; 298 case CPR0_OPBD: 299 ret = (2 << 24); 300 break; 301 case CPR0_PERD: 302 case CPR0_AHBD: 303 ret = (1 << 24); 304 break; 305 default: 306 break; 307 } 308 break; 309 default: 310 break; 311 } 312 313 return ret; 314 } 315 316 static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val) 317 { 318 ppc4xx_cpr_t *cpr = opaque; 319 320 switch (dcrn) { 321 case CPR0_CFGADDR: 322 cpr->addr = val; 323 break; 324 case CPR0_CFGDATA: 325 break; 326 default: 327 break; 328 } 329 } 330 331 static void ppc4xx_cpr_reset(void *opaque) 332 { 333 ppc4xx_cpr_t *cpr = opaque; 334 335 cpr->addr = 0; 336 } 337 338 void ppc4xx_cpr_init(CPUPPCState *env) 339 { 340 ppc4xx_cpr_t *cpr; 341 342 cpr = g_malloc0(sizeof(*cpr)); 343 ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr); 344 ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr); 345 qemu_register_reset(ppc4xx_cpr_reset, cpr); 346 } 347 348 /*****************************************************************************/ 349 /* System DCRs */ 350 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t; 351 struct ppc4xx_sdr_t { 352 uint32_t addr; 353 }; 354 355 enum { 356 SDR0_CFGADDR = 0x00e, 357 SDR0_CFGDATA, 358 SDR0_STRP0 = 0x020, 359 SDR0_STRP1, 360 SDR0_102 = 0x66, 361 SDR0_103, 362 SDR0_128 = 0x80, 363 SDR0_ECID3 = 0x083, 364 SDR0_DDR0 = 0x0e1, 365 SDR0_USB0 = 0x320, 366 }; 367 368 enum { 369 PESDR0_LOOP = 0x303, 370 PESDR0_RCSSET, 371 PESDR0_RCSSTS, 372 PESDR0_RSTSTA = 0x310, 373 PESDR1_LOOP = 0x343, 374 PESDR1_RCSSET, 375 PESDR1_RCSSTS, 376 PESDR1_RSTSTA = 0x365, 377 }; 378 379 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) 380 #define SDR0_DDR0_DDRM_DDR1 0x20000000 381 #define SDR0_DDR0_DDRM_DDR2 0x40000000 382 383 static uint32_t dcr_read_sdr(void *opaque, int dcrn) 384 { 385 ppc4xx_sdr_t *sdr = opaque; 386 uint32_t ret = 0; 387 388 switch (dcrn) { 389 case SDR0_CFGADDR: 390 ret = sdr->addr; 391 break; 392 case SDR0_CFGDATA: 393 switch (sdr->addr) { 394 case SDR0_STRP0: 395 /* FIXME: Is this correct? This breaks timing in U-Boot */ 396 ret = 0; /*(0xb5 << 8) | (1 << 4) | 9 */ 397 break; 398 case SDR0_STRP1: 399 ret = (5 << 29) | (2 << 26) | (1 << 24); 400 break; 401 case SDR0_ECID3: 402 ret = 1 << 20; /* No Security/Kasumi support */ 403 break; 404 case SDR0_DDR0: 405 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; 406 break; 407 case PESDR0_RCSSET: 408 case PESDR1_RCSSET: 409 ret = (1 << 24) | (1 << 16); 410 break; 411 case PESDR0_RCSSTS: 412 case PESDR1_RCSSTS: 413 ret = (1 << 16) | (1 << 12); 414 break; 415 case PESDR0_RSTSTA: 416 case PESDR1_RSTSTA: 417 ret = 1; 418 break; 419 case PESDR0_LOOP: 420 case PESDR1_LOOP: 421 ret = 1 << 12; 422 break; 423 default: 424 break; 425 } 426 break; 427 default: 428 break; 429 } 430 431 return ret; 432 } 433 434 static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val) 435 { 436 ppc4xx_sdr_t *sdr = opaque; 437 438 switch (dcrn) { 439 case SDR0_CFGADDR: 440 sdr->addr = val; 441 break; 442 case SDR0_CFGDATA: 443 switch (sdr->addr) { 444 case 0x00: /* B0CR */ 445 break; 446 default: 447 break; 448 } 449 break; 450 default: 451 break; 452 } 453 } 454 455 static void sdr_reset(void *opaque) 456 { 457 ppc4xx_sdr_t *sdr = opaque; 458 459 sdr->addr = 0; 460 } 461 462 void ppc4xx_sdr_init(CPUPPCState *env) 463 { 464 ppc4xx_sdr_t *sdr; 465 466 sdr = g_malloc0(sizeof(*sdr)); 467 qemu_register_reset(&sdr_reset, sdr); 468 ppc_dcr_register(env, SDR0_CFGADDR, 469 sdr, &dcr_read_sdr, &dcr_write_sdr); 470 ppc_dcr_register(env, SDR0_CFGDATA, 471 sdr, &dcr_read_sdr, &dcr_write_sdr); 472 ppc_dcr_register(env, SDR0_102, 473 sdr, &dcr_read_sdr, &dcr_write_sdr); 474 ppc_dcr_register(env, SDR0_103, 475 sdr, &dcr_read_sdr, &dcr_write_sdr); 476 ppc_dcr_register(env, SDR0_128, 477 sdr, &dcr_read_sdr, &dcr_write_sdr); 478 ppc_dcr_register(env, SDR0_USB0, 479 sdr, &dcr_read_sdr, &dcr_write_sdr); 480 } 481 482 /*****************************************************************************/ 483 /* SDRAM controller */ 484 typedef struct ppc4xx_sdram_t { 485 uint32_t addr; 486 int nbanks; 487 MemoryRegion containers[4]; /* used for clipping */ 488 MemoryRegion *ram_memories; 489 hwaddr ram_bases[4]; 490 hwaddr ram_sizes[4]; 491 uint32_t bcr[4]; 492 } ppc4xx_sdram_t; 493 494 enum { 495 SDRAM0_CFGADDR = 0x10, 496 SDRAM0_CFGDATA, 497 SDRAM_R0BAS = 0x40, 498 SDRAM_R1BAS, 499 SDRAM_R2BAS, 500 SDRAM_R3BAS, 501 SDRAM_CONF1HB = 0x45, 502 SDRAM_PLBADDULL = 0x4a, 503 SDRAM_CONF1LL = 0x4b, 504 SDRAM_CONFPATHB = 0x4f, 505 SDRAM_PLBADDUHB = 0x50, 506 }; 507 508 /* XXX: TOFIX: some patches have made this code become inconsistent: 509 * there are type inconsistencies, mixing hwaddr, target_ulong 510 * and uint32_t 511 */ 512 static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) 513 { 514 uint32_t bcr; 515 516 switch (ram_size) { 517 case (8 * M_BYTE): 518 bcr = 0xffc0; 519 break; 520 case (16 * M_BYTE): 521 bcr = 0xff80; 522 break; 523 case (32 * M_BYTE): 524 bcr = 0xff00; 525 break; 526 case (64 * M_BYTE): 527 bcr = 0xfe00; 528 break; 529 case (128 * M_BYTE): 530 bcr = 0xfc00; 531 break; 532 case (256 * M_BYTE): 533 bcr = 0xf800; 534 break; 535 case (512 * M_BYTE): 536 bcr = 0xf000; 537 break; 538 case (1 * G_BYTE): 539 bcr = 0xe000; 540 break; 541 default: 542 error_report("invalid RAM size " TARGET_FMT_plx, ram_size); 543 return 0; 544 } 545 bcr |= ram_base & 0xFF800000; 546 bcr |= 1; 547 548 return bcr; 549 } 550 551 static inline hwaddr sdram_base(uint32_t bcr) 552 { 553 return bcr & 0xFF800000; 554 } 555 556 static target_ulong sdram_size(uint32_t bcr) 557 { 558 target_ulong size; 559 int sh; 560 561 sh = 1024 - ((bcr >> 6) & 0x3ff); 562 if (sh == 0) { 563 size = -1; 564 } else { 565 size = 8 * M_BYTE * sh; 566 } 567 568 return size; 569 } 570 571 static void sdram_set_bcr(ppc4xx_sdram_t *sdram, 572 uint32_t *bcrp, uint32_t bcr, int enabled) 573 { 574 unsigned n = bcrp - sdram->bcr; 575 576 if (*bcrp & 1) { 577 /* Unmap RAM */ 578 memory_region_del_subregion(get_system_memory(), 579 &sdram->containers[n]); 580 memory_region_del_subregion(&sdram->containers[n], 581 &sdram->ram_memories[n]); 582 object_unparent(OBJECT(&sdram->containers[n])); 583 } 584 *bcrp = bcr & 0xFFDEE001; 585 if (enabled && (bcr & 1)) { 586 memory_region_init(&sdram->containers[n], NULL, "sdram-containers", 587 sdram_size(bcr)); 588 memory_region_add_subregion(&sdram->containers[n], 0, 589 &sdram->ram_memories[n]); 590 memory_region_add_subregion(get_system_memory(), 591 sdram_base(bcr), 592 &sdram->containers[n]); 593 } 594 } 595 596 static void sdram_map_bcr(ppc4xx_sdram_t *sdram) 597 { 598 int i; 599 600 for (i = 0; i < sdram->nbanks; i++) { 601 if (sdram->ram_sizes[i] != 0) { 602 sdram_set_bcr(sdram, 603 &sdram->bcr[i], 604 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), 605 1); 606 } else { 607 sdram_set_bcr(sdram, &sdram->bcr[i], 0, 0); 608 } 609 } 610 } 611 612 static uint32_t dcr_read_sdram(void *opaque, int dcrn) 613 { 614 ppc4xx_sdram_t *sdram = opaque; 615 uint32_t ret = 0; 616 617 switch (dcrn) { 618 case SDRAM_R0BAS: 619 case SDRAM_R1BAS: 620 case SDRAM_R2BAS: 621 case SDRAM_R3BAS: 622 ret = sdram_bcr(sdram->ram_bases[dcrn - SDRAM_R0BAS], 623 sdram->ram_sizes[dcrn - SDRAM_R0BAS]); 624 break; 625 case SDRAM_CONF1HB: 626 case SDRAM_CONF1LL: 627 case SDRAM_CONFPATHB: 628 case SDRAM_PLBADDULL: 629 case SDRAM_PLBADDUHB: 630 break; 631 case SDRAM0_CFGADDR: 632 ret = sdram->addr; 633 break; 634 case SDRAM0_CFGDATA: 635 switch (sdram->addr) { 636 case 0x14: /* SDRAM_MCSTAT (405EX) */ 637 case 0x1F: 638 ret = 0x80000000; 639 break; 640 case 0x21: /* SDRAM_MCOPT2 */ 641 ret = 0x08000000; 642 break; 643 case 0x40: /* SDRAM_MB0CF */ 644 ret = 0x00008001; 645 break; 646 case 0x7A: /* SDRAM_DLCR */ 647 ret = 0x02000000; 648 break; 649 case 0xE1: /* SDR0_DDR0 */ 650 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; 651 break; 652 default: 653 break; 654 } 655 break; 656 default: 657 break; 658 } 659 660 return ret; 661 } 662 663 static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) 664 { 665 ppc4xx_sdram_t *sdram = opaque; 666 667 switch (dcrn) { 668 case SDRAM_R0BAS: 669 case SDRAM_R1BAS: 670 case SDRAM_R2BAS: 671 case SDRAM_R3BAS: 672 case SDRAM_CONF1HB: 673 case SDRAM_CONF1LL: 674 case SDRAM_CONFPATHB: 675 case SDRAM_PLBADDULL: 676 case SDRAM_PLBADDUHB: 677 break; 678 case SDRAM0_CFGADDR: 679 sdram->addr = val; 680 break; 681 case SDRAM0_CFGDATA: 682 switch (sdram->addr) { 683 case 0x00: /* B0CR */ 684 break; 685 default: 686 break; 687 } 688 break; 689 default: 690 break; 691 } 692 } 693 694 static void sdram_reset(void *opaque) 695 { 696 ppc4xx_sdram_t *sdram = opaque; 697 698 sdram->addr = 0; 699 } 700 701 void ppc440_sdram_init(CPUPPCState *env, int nbanks, 702 MemoryRegion *ram_memories, 703 hwaddr *ram_bases, hwaddr *ram_sizes, 704 int do_init) 705 { 706 ppc4xx_sdram_t *sdram; 707 708 sdram = g_malloc0(sizeof(*sdram)); 709 sdram->nbanks = nbanks; 710 sdram->ram_memories = ram_memories; 711 memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr)); 712 memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr)); 713 qemu_register_reset(&sdram_reset, sdram); 714 ppc_dcr_register(env, SDRAM0_CFGADDR, 715 sdram, &dcr_read_sdram, &dcr_write_sdram); 716 ppc_dcr_register(env, SDRAM0_CFGDATA, 717 sdram, &dcr_read_sdram, &dcr_write_sdram); 718 if (do_init) { 719 sdram_map_bcr(sdram); 720 } 721 722 ppc_dcr_register(env, SDRAM_R0BAS, 723 sdram, &dcr_read_sdram, &dcr_write_sdram); 724 ppc_dcr_register(env, SDRAM_R1BAS, 725 sdram, &dcr_read_sdram, &dcr_write_sdram); 726 ppc_dcr_register(env, SDRAM_R2BAS, 727 sdram, &dcr_read_sdram, &dcr_write_sdram); 728 ppc_dcr_register(env, SDRAM_R3BAS, 729 sdram, &dcr_read_sdram, &dcr_write_sdram); 730 ppc_dcr_register(env, SDRAM_CONF1HB, 731 sdram, &dcr_read_sdram, &dcr_write_sdram); 732 ppc_dcr_register(env, SDRAM_PLBADDULL, 733 sdram, &dcr_read_sdram, &dcr_write_sdram); 734 ppc_dcr_register(env, SDRAM_CONF1LL, 735 sdram, &dcr_read_sdram, &dcr_write_sdram); 736 ppc_dcr_register(env, SDRAM_CONFPATHB, 737 sdram, &dcr_read_sdram, &dcr_write_sdram); 738 ppc_dcr_register(env, SDRAM_PLBADDUHB, 739 sdram, &dcr_read_sdram, &dcr_write_sdram); 740 } 741 742 /*****************************************************************************/ 743 /* PLB to AHB bridge */ 744 enum { 745 AHB_TOP = 0xA4, 746 AHB_BOT = 0xA5, 747 }; 748 749 typedef struct ppc4xx_ahb_t { 750 uint32_t top; 751 uint32_t bot; 752 } ppc4xx_ahb_t; 753 754 static uint32_t dcr_read_ahb(void *opaque, int dcrn) 755 { 756 ppc4xx_ahb_t *ahb = opaque; 757 uint32_t ret = 0; 758 759 switch (dcrn) { 760 case AHB_TOP: 761 ret = ahb->top; 762 break; 763 case AHB_BOT: 764 ret = ahb->bot; 765 break; 766 default: 767 break; 768 } 769 770 return ret; 771 } 772 773 static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val) 774 { 775 ppc4xx_ahb_t *ahb = opaque; 776 777 switch (dcrn) { 778 case AHB_TOP: 779 ahb->top = val; 780 break; 781 case AHB_BOT: 782 ahb->bot = val; 783 break; 784 } 785 } 786 787 static void ppc4xx_ahb_reset(void *opaque) 788 { 789 ppc4xx_ahb_t *ahb = opaque; 790 791 /* No error */ 792 ahb->top = 0; 793 ahb->bot = 0; 794 } 795 796 void ppc4xx_ahb_init(CPUPPCState *env) 797 { 798 ppc4xx_ahb_t *ahb; 799 800 ahb = g_malloc0(sizeof(*ahb)); 801 ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb); 802 ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb); 803 qemu_register_reset(ppc4xx_ahb_reset, ahb); 804 } 805 806 /*****************************************************************************/ 807 /* PCI Express controller */ 808 /* FIXME: This is not complete and does not work, only implemented partially 809 * to allow firmware and guests to find an empty bus. Cards should use PCI. 810 */ 811 #include "hw/pci/pcie_host.h" 812 813 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host" 814 #define PPC460EX_PCIE_HOST(obj) \ 815 OBJECT_CHECK(PPC460EXPCIEState, (obj), TYPE_PPC460EX_PCIE_HOST) 816 817 typedef struct PPC460EXPCIEState { 818 PCIExpressHost host; 819 820 MemoryRegion iomem; 821 qemu_irq irq[4]; 822 int32_t dcrn_base; 823 824 uint64_t cfg_base; 825 uint32_t cfg_mask; 826 uint64_t msg_base; 827 uint32_t msg_mask; 828 uint64_t omr1_base; 829 uint64_t omr1_mask; 830 uint64_t omr2_base; 831 uint64_t omr2_mask; 832 uint64_t omr3_base; 833 uint64_t omr3_mask; 834 uint64_t reg_base; 835 uint32_t reg_mask; 836 uint32_t special; 837 uint32_t cfg; 838 } PPC460EXPCIEState; 839 840 #define DCRN_PCIE0_BASE 0x100 841 #define DCRN_PCIE1_BASE 0x120 842 843 enum { 844 PEGPL_CFGBAH = 0x0, 845 PEGPL_CFGBAL, 846 PEGPL_CFGMSK, 847 PEGPL_MSGBAH, 848 PEGPL_MSGBAL, 849 PEGPL_MSGMSK, 850 PEGPL_OMR1BAH, 851 PEGPL_OMR1BAL, 852 PEGPL_OMR1MSKH, 853 PEGPL_OMR1MSKL, 854 PEGPL_OMR2BAH, 855 PEGPL_OMR2BAL, 856 PEGPL_OMR2MSKH, 857 PEGPL_OMR2MSKL, 858 PEGPL_OMR3BAH, 859 PEGPL_OMR3BAL, 860 PEGPL_OMR3MSKH, 861 PEGPL_OMR3MSKL, 862 PEGPL_REGBAH, 863 PEGPL_REGBAL, 864 PEGPL_REGMSK, 865 PEGPL_SPECIAL, 866 PEGPL_CFG, 867 }; 868 869 static uint32_t dcr_read_pcie(void *opaque, int dcrn) 870 { 871 PPC460EXPCIEState *state = opaque; 872 uint32_t ret = 0; 873 874 switch (dcrn - state->dcrn_base) { 875 case PEGPL_CFGBAH: 876 ret = state->cfg_base >> 32; 877 break; 878 case PEGPL_CFGBAL: 879 ret = state->cfg_base; 880 break; 881 case PEGPL_CFGMSK: 882 ret = state->cfg_mask; 883 break; 884 case PEGPL_MSGBAH: 885 ret = state->msg_base >> 32; 886 break; 887 case PEGPL_MSGBAL: 888 ret = state->msg_base; 889 break; 890 case PEGPL_MSGMSK: 891 ret = state->msg_mask; 892 break; 893 case PEGPL_OMR1BAH: 894 ret = state->omr1_base >> 32; 895 break; 896 case PEGPL_OMR1BAL: 897 ret = state->omr1_base; 898 break; 899 case PEGPL_OMR1MSKH: 900 ret = state->omr1_mask >> 32; 901 break; 902 case PEGPL_OMR1MSKL: 903 ret = state->omr1_mask; 904 break; 905 case PEGPL_OMR2BAH: 906 ret = state->omr2_base >> 32; 907 break; 908 case PEGPL_OMR2BAL: 909 ret = state->omr2_base; 910 break; 911 case PEGPL_OMR2MSKH: 912 ret = state->omr2_mask >> 32; 913 break; 914 case PEGPL_OMR2MSKL: 915 ret = state->omr3_mask; 916 break; 917 case PEGPL_OMR3BAH: 918 ret = state->omr3_base >> 32; 919 break; 920 case PEGPL_OMR3BAL: 921 ret = state->omr3_base; 922 break; 923 case PEGPL_OMR3MSKH: 924 ret = state->omr3_mask >> 32; 925 break; 926 case PEGPL_OMR3MSKL: 927 ret = state->omr3_mask; 928 break; 929 case PEGPL_REGBAH: 930 ret = state->reg_base >> 32; 931 break; 932 case PEGPL_REGBAL: 933 ret = state->reg_base; 934 break; 935 case PEGPL_REGMSK: 936 ret = state->reg_mask; 937 break; 938 case PEGPL_SPECIAL: 939 ret = state->special; 940 break; 941 case PEGPL_CFG: 942 ret = state->cfg; 943 break; 944 } 945 946 return ret; 947 } 948 949 static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val) 950 { 951 PPC460EXPCIEState *s = opaque; 952 uint64_t size; 953 954 switch (dcrn - s->dcrn_base) { 955 case PEGPL_CFGBAH: 956 s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff); 957 break; 958 case PEGPL_CFGBAL: 959 s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val; 960 break; 961 case PEGPL_CFGMSK: 962 s->cfg_mask = val; 963 size = ~(val & 0xfffffffe) + 1; 964 qemu_mutex_lock_iothread(); 965 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size); 966 qemu_mutex_unlock_iothread(); 967 break; 968 case PEGPL_MSGBAH: 969 s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff); 970 break; 971 case PEGPL_MSGBAL: 972 s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val; 973 break; 974 case PEGPL_MSGMSK: 975 s->msg_mask = val; 976 break; 977 case PEGPL_OMR1BAH: 978 s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff); 979 break; 980 case PEGPL_OMR1BAL: 981 s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val; 982 break; 983 case PEGPL_OMR1MSKH: 984 s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff); 985 break; 986 case PEGPL_OMR1MSKL: 987 s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val; 988 break; 989 case PEGPL_OMR2BAH: 990 s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff); 991 break; 992 case PEGPL_OMR2BAL: 993 s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val; 994 break; 995 case PEGPL_OMR2MSKH: 996 s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff); 997 break; 998 case PEGPL_OMR2MSKL: 999 s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val; 1000 break; 1001 case PEGPL_OMR3BAH: 1002 s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff); 1003 break; 1004 case PEGPL_OMR3BAL: 1005 s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val; 1006 break; 1007 case PEGPL_OMR3MSKH: 1008 s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff); 1009 break; 1010 case PEGPL_OMR3MSKL: 1011 s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val; 1012 break; 1013 case PEGPL_REGBAH: 1014 s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff); 1015 break; 1016 case PEGPL_REGBAL: 1017 s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val; 1018 break; 1019 case PEGPL_REGMSK: 1020 s->reg_mask = val; 1021 /* FIXME: how is size encoded? */ 1022 size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1); 1023 break; 1024 case PEGPL_SPECIAL: 1025 s->special = val; 1026 break; 1027 case PEGPL_CFG: 1028 s->cfg = val; 1029 break; 1030 } 1031 } 1032 1033 static void ppc460ex_set_irq(void *opaque, int irq_num, int level) 1034 { 1035 PPC460EXPCIEState *s = opaque; 1036 qemu_set_irq(s->irq[irq_num], level); 1037 } 1038 1039 static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) 1040 { 1041 PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev); 1042 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 1043 int i, id; 1044 char buf[16]; 1045 1046 switch (s->dcrn_base) { 1047 case DCRN_PCIE0_BASE: 1048 id = 0; 1049 break; 1050 case DCRN_PCIE1_BASE: 1051 id = 1; 1052 break; 1053 default: 1054 error_setg(errp, "invalid PCIe DCRN base"); 1055 return; 1056 } 1057 snprintf(buf, sizeof(buf), "pcie%d-io", id); 1058 memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); 1059 for (i = 0; i < 4; i++) { 1060 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1061 } 1062 snprintf(buf, sizeof(buf), "pcie.%d", id); 1063 pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, 1064 pci_swizzle_map_irq_fn, s, &s->iomem, 1065 get_system_io(), 0, 4, TYPE_PCIE_BUS); 1066 } 1067 1068 static Property ppc460ex_pcie_props[] = { 1069 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1), 1070 DEFINE_PROP_END_OF_LIST(), 1071 }; 1072 1073 static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data) 1074 { 1075 DeviceClass *dc = DEVICE_CLASS(klass); 1076 1077 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1078 dc->realize = ppc460ex_pcie_realize; 1079 dc->props = ppc460ex_pcie_props; 1080 dc->hotpluggable = false; 1081 } 1082 1083 static const TypeInfo ppc460ex_pcie_host_info = { 1084 .name = TYPE_PPC460EX_PCIE_HOST, 1085 .parent = TYPE_PCIE_HOST_BRIDGE, 1086 .instance_size = sizeof(PPC460EXPCIEState), 1087 .class_init = ppc460ex_pcie_class_init, 1088 }; 1089 1090 static void ppc460ex_pcie_register(void) 1091 { 1092 type_register_static(&ppc460ex_pcie_host_info); 1093 } 1094 1095 type_init(ppc460ex_pcie_register) 1096 1097 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env) 1098 { 1099 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s, 1100 &dcr_read_pcie, &dcr_write_pcie); 1101 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s, 1102 &dcr_read_pcie, &dcr_write_pcie); 1103 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s, 1104 &dcr_read_pcie, &dcr_write_pcie); 1105 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s, 1106 &dcr_read_pcie, &dcr_write_pcie); 1107 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s, 1108 &dcr_read_pcie, &dcr_write_pcie); 1109 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s, 1110 &dcr_read_pcie, &dcr_write_pcie); 1111 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s, 1112 &dcr_read_pcie, &dcr_write_pcie); 1113 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s, 1114 &dcr_read_pcie, &dcr_write_pcie); 1115 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s, 1116 &dcr_read_pcie, &dcr_write_pcie); 1117 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s, 1118 &dcr_read_pcie, &dcr_write_pcie); 1119 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s, 1120 &dcr_read_pcie, &dcr_write_pcie); 1121 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s, 1122 &dcr_read_pcie, &dcr_write_pcie); 1123 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s, 1124 &dcr_read_pcie, &dcr_write_pcie); 1125 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s, 1126 &dcr_read_pcie, &dcr_write_pcie); 1127 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s, 1128 &dcr_read_pcie, &dcr_write_pcie); 1129 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s, 1130 &dcr_read_pcie, &dcr_write_pcie); 1131 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s, 1132 &dcr_read_pcie, &dcr_write_pcie); 1133 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s, 1134 &dcr_read_pcie, &dcr_write_pcie); 1135 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s, 1136 &dcr_read_pcie, &dcr_write_pcie); 1137 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s, 1138 &dcr_read_pcie, &dcr_write_pcie); 1139 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s, 1140 &dcr_read_pcie, &dcr_write_pcie); 1141 ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s, 1142 &dcr_read_pcie, &dcr_write_pcie); 1143 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s, 1144 &dcr_read_pcie, &dcr_write_pcie); 1145 } 1146 1147 void ppc460ex_pcie_init(CPUPPCState *env) 1148 { 1149 DeviceState *dev; 1150 1151 dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST); 1152 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE); 1153 qdev_init_nofail(dev); 1154 object_property_set_bool(OBJECT(dev), true, "realized", NULL); 1155 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1156 1157 dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST); 1158 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE); 1159 qdev_init_nofail(dev); 1160 object_property_set_bool(OBJECT(dev), true, "realized", NULL); 1161 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1162 } 1163