1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "qapi/type-helpers.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 #include "hw/pci-host/pnv_phb.h" 48 #include "hw/pci-host/pnv_phb3.h" 49 #include "hw/pci-host/pnv_phb4.h" 50 51 #include "hw/ppc/xics.h" 52 #include "hw/qdev-properties.h" 53 #include "hw/ppc/pnv_chip.h" 54 #include "hw/ppc/pnv_xscom.h" 55 #include "hw/ppc/pnv_pnor.h" 56 57 #include "hw/isa/isa.h" 58 #include "hw/char/serial.h" 59 #include "hw/rtc/mc146818rtc.h" 60 61 #include <libfdt.h> 62 63 #define FDT_MAX_SIZE (1 * MiB) 64 65 #define FW_FILE_NAME "skiboot.lid" 66 #define FW_LOAD_ADDR 0x0 67 #define FW_MAX_SIZE (16 * MiB) 68 69 #define KERNEL_LOAD_ADDR 0x20000000 70 #define KERNEL_MAX_SIZE (128 * MiB) 71 #define INITRD_LOAD_ADDR 0x28000000 72 #define INITRD_MAX_SIZE (128 * MiB) 73 74 static const char *pnv_chip_core_typename(const PnvChip *o) 75 { 76 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 77 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 78 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 79 const char *core_type = object_class_get_name(object_class_by_name(s)); 80 g_free(s); 81 return core_type; 82 } 83 84 /* 85 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 86 * 4 * 4 sockets * 12 cores * 8 threads = 1536 87 * Let's make it 2^11 88 */ 89 #define MAX_CPUS 2048 90 91 /* 92 * Memory nodes are created by hostboot, one for each range of memory 93 * that has a different "affinity". In practice, it means one range 94 * per chip. 95 */ 96 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 97 { 98 char *mem_name; 99 uint64_t mem_reg_property[2]; 100 int off; 101 102 mem_reg_property[0] = cpu_to_be64(start); 103 mem_reg_property[1] = cpu_to_be64(size); 104 105 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 106 off = fdt_add_subnode(fdt, 0, mem_name); 107 g_free(mem_name); 108 109 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 110 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 111 sizeof(mem_reg_property)))); 112 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 113 } 114 115 static int get_cpus_node(void *fdt) 116 { 117 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 118 119 if (cpus_offset < 0) { 120 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 121 if (cpus_offset) { 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 123 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 124 } 125 } 126 _FDT(cpus_offset); 127 return cpus_offset; 128 } 129 130 /* 131 * The PowerNV cores (and threads) need to use real HW ids and not an 132 * incremental index like it has been done on other platforms. This HW 133 * id is stored in the CPU PIR, it is used to create cpu nodes in the 134 * device tree, used in XSCOM to address cores and in interrupt 135 * servers. 136 */ 137 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 138 { 139 PowerPCCPU *cpu = pc->threads[0]; 140 CPUState *cs = CPU(cpu); 141 DeviceClass *dc = DEVICE_GET_CLASS(cs); 142 int smt_threads = CPU_CORE(pc)->nr_threads; 143 CPUPPCState *env = &cpu->env; 144 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 145 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 146 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 147 int i; 148 uint32_t pir; 149 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 150 0xffffffff, 0xffffffff}; 151 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 152 uint32_t cpufreq = 1000000000; 153 uint32_t page_sizes_prop[64]; 154 size_t page_sizes_prop_size; 155 int offset; 156 char *nodename; 157 int cpus_offset = get_cpus_node(fdt); 158 159 pir = pnv_cc->chip_pir(chip, pc->hwid, 0); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i)); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(*servers_prop) * smt_threads))); 245 246 return offset; 247 } 248 249 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 250 uint32_t nr_threads) 251 { 252 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 253 uint32_t pir = pcc->chip_pir(chip, hwid, 0); 254 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 255 char *name; 256 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 257 uint32_t irange[2], i, rsize; 258 uint64_t *reg; 259 int offset; 260 261 irange[0] = cpu_to_be32(pir); 262 irange[1] = cpu_to_be32(nr_threads); 263 264 rsize = sizeof(uint64_t) * 2 * nr_threads; 265 reg = g_malloc(rsize); 266 for (i = 0; i < nr_threads; i++) { 267 /* We know P8 PIR is linear with thread id */ 268 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 269 reg[i * 2 + 1] = cpu_to_be64(0x1000); 270 } 271 272 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 273 offset = fdt_add_subnode(fdt, 0, name); 274 _FDT(offset); 275 g_free(name); 276 277 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 278 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 279 _FDT((fdt_setprop_string(fdt, offset, "device_type", 280 "PowerPC-External-Interrupt-Presentation"))); 281 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 282 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 283 irange, sizeof(irange)))); 284 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 285 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 286 g_free(reg); 287 } 288 289 /* 290 * Adds a PnvPHB to the chip on P8. 291 * Implemented here, like for defaults PHBs 292 */ 293 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 294 { 295 Pnv8Chip *chip8 = PNV8_CHIP(chip); 296 297 phb->chip = chip; 298 299 chip8->phbs[chip8->num_phbs] = phb; 300 chip8->num_phbs++; 301 return chip; 302 } 303 304 /* 305 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 306 * HTM is always enabled because TCG does implement HTM, it's just a 307 * degenerate implementation. 308 */ 309 static const uint8_t pa_features_207[] = { 24, 0, 310 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 311 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 312 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 313 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 314 315 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 316 { 317 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 318 int i; 319 320 pnv_dt_xscom(chip, fdt, 0, 321 cpu_to_be64(PNV_XSCOM_BASE(chip)), 322 cpu_to_be64(PNV_XSCOM_SIZE), 323 compat, sizeof(compat)); 324 325 for (i = 0; i < chip->nr_cores; i++) { 326 PnvCore *pnv_core = chip->cores[i]; 327 int offset; 328 329 offset = pnv_dt_core(chip, pnv_core, fdt); 330 331 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 332 pa_features_207, sizeof(pa_features_207)))); 333 334 /* Interrupt Control Presenters (ICP). One per core. */ 335 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 336 } 337 338 if (chip->ram_size) { 339 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 340 } 341 } 342 343 /* 344 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 345 */ 346 static const uint8_t pa_features_300[] = { 66, 0, 347 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 348 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 349 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 350 /* 6: DS207 */ 351 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 352 /* 16: Vector */ 353 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 354 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 355 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 356 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 357 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 358 /* 32: LE atomic, 34: EBB + ext EBB */ 359 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 360 /* 40: Radix MMU */ 361 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 362 /* 42: PM, 44: PC RA, 46: SC vec'd */ 363 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 364 /* 48: SIMD, 50: QP BFP, 52: String */ 365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 366 /* 54: DecFP, 56: DecI, 58: SHA */ 367 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 368 /* 60: NM atomic, 62: RNG */ 369 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 370 }; 371 372 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 373 { 374 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 375 int i; 376 377 pnv_dt_xscom(chip, fdt, 0, 378 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 379 cpu_to_be64(PNV9_XSCOM_SIZE), 380 compat, sizeof(compat)); 381 382 for (i = 0; i < chip->nr_cores; i++) { 383 PnvCore *pnv_core = chip->cores[i]; 384 int offset; 385 386 offset = pnv_dt_core(chip, pnv_core, fdt); 387 388 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 389 pa_features_300, sizeof(pa_features_300)))); 390 } 391 392 if (chip->ram_size) { 393 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 394 } 395 396 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 397 } 398 399 /* 400 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 401 * always disables copy/paste. 402 */ 403 static const uint8_t pa_features_31[] = { 74, 0, 404 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 405 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 406 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 407 /* 6: DS207 */ 408 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 409 /* 16: Vector */ 410 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 411 /* 18: Vec. Scalar, 20: Vec. XOR */ 412 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 413 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 414 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 415 /* 32: LE atomic, 34: EBB + ext EBB */ 416 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 417 /* 40: Radix MMU */ 418 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 419 /* 42: PM, 44: PC RA, 46: SC vec'd */ 420 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 421 /* 48: SIMD, 50: QP BFP, 52: String */ 422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 423 /* 54: DecFP, 56: DecI, 58: SHA */ 424 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 425 /* 60: NM atomic, 62: RNG */ 426 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 427 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 428 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 429 /* 72: [P]HASHST/[P]HASHCHK */ 430 0x80, 0x00, /* 72 - 73 */ 431 }; 432 433 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 434 { 435 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 436 int i; 437 438 pnv_dt_xscom(chip, fdt, 0, 439 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 440 cpu_to_be64(PNV10_XSCOM_SIZE), 441 compat, sizeof(compat)); 442 443 for (i = 0; i < chip->nr_cores; i++) { 444 PnvCore *pnv_core = chip->cores[i]; 445 int offset; 446 447 offset = pnv_dt_core(chip, pnv_core, fdt); 448 449 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 450 pa_features_31, sizeof(pa_features_31)))); 451 } 452 453 if (chip->ram_size) { 454 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 455 } 456 457 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 458 } 459 460 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 461 { 462 uint32_t io_base = d->ioport_id; 463 uint32_t io_regs[] = { 464 cpu_to_be32(1), 465 cpu_to_be32(io_base), 466 cpu_to_be32(2) 467 }; 468 char *name; 469 int node; 470 471 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 472 node = fdt_add_subnode(fdt, lpc_off, name); 473 _FDT(node); 474 g_free(name); 475 476 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 477 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 478 } 479 480 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 481 { 482 const char compatible[] = "ns16550\0pnpPNP,501"; 483 uint32_t io_base = d->ioport_id; 484 uint32_t io_regs[] = { 485 cpu_to_be32(1), 486 cpu_to_be32(io_base), 487 cpu_to_be32(8) 488 }; 489 uint32_t irq; 490 char *name; 491 int node; 492 493 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 494 495 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 496 node = fdt_add_subnode(fdt, lpc_off, name); 497 _FDT(node); 498 g_free(name); 499 500 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 501 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 502 sizeof(compatible)))); 503 504 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 505 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 506 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 507 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 508 fdt_get_phandle(fdt, lpc_off)))); 509 510 /* This is needed by Linux */ 511 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 512 } 513 514 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 515 { 516 const char compatible[] = "bt\0ipmi-bt"; 517 uint32_t io_base; 518 uint32_t io_regs[] = { 519 cpu_to_be32(1), 520 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 521 cpu_to_be32(3) 522 }; 523 uint32_t irq; 524 char *name; 525 int node; 526 527 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 528 io_regs[1] = cpu_to_be32(io_base); 529 530 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 531 532 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 533 node = fdt_add_subnode(fdt, lpc_off, name); 534 _FDT(node); 535 g_free(name); 536 537 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 538 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 539 sizeof(compatible)))); 540 541 /* Mark it as reserved to avoid Linux trying to claim it */ 542 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 543 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 544 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 545 fdt_get_phandle(fdt, lpc_off)))); 546 } 547 548 typedef struct ForeachPopulateArgs { 549 void *fdt; 550 int offset; 551 } ForeachPopulateArgs; 552 553 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 554 { 555 ForeachPopulateArgs *args = opaque; 556 ISADevice *d = ISA_DEVICE(dev); 557 558 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 559 pnv_dt_rtc(d, args->fdt, args->offset); 560 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 561 pnv_dt_serial(d, args->fdt, args->offset); 562 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 563 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 564 } else { 565 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 566 d->ioport_id); 567 } 568 569 return 0; 570 } 571 572 /* 573 * The default LPC bus of a multichip system is on chip 0. It's 574 * recognized by the firmware (skiboot) using a "primary" property. 575 */ 576 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 577 { 578 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 579 ForeachPopulateArgs args = { 580 .fdt = fdt, 581 .offset = isa_offset, 582 }; 583 uint32_t phandle; 584 585 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 586 587 phandle = qemu_fdt_alloc_phandle(fdt); 588 assert(phandle > 0); 589 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 590 591 /* 592 * ISA devices are not necessarily parented to the ISA bus so we 593 * can not use object_child_foreach() 594 */ 595 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 596 &args); 597 } 598 599 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 600 { 601 int off; 602 603 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 604 off = fdt_add_subnode(fdt, off, "power-mgt"); 605 606 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 607 } 608 609 static void *pnv_dt_create(MachineState *machine) 610 { 611 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 612 PnvMachineState *pnv = PNV_MACHINE(machine); 613 void *fdt; 614 char *buf; 615 int off; 616 int i; 617 618 fdt = g_malloc0(FDT_MAX_SIZE); 619 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 620 621 /* /qemu node */ 622 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 623 624 /* Root node */ 625 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 626 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 627 _FDT((fdt_setprop_string(fdt, 0, "model", 628 "IBM PowerNV (emulated by qemu)"))); 629 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 630 631 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 632 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 633 if (qemu_uuid_set) { 634 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 635 } 636 g_free(buf); 637 638 off = fdt_add_subnode(fdt, 0, "chosen"); 639 if (machine->kernel_cmdline) { 640 _FDT((fdt_setprop_string(fdt, off, "bootargs", 641 machine->kernel_cmdline))); 642 } 643 644 if (pnv->initrd_size) { 645 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 646 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 647 648 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 649 &start_prop, sizeof(start_prop)))); 650 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 651 &end_prop, sizeof(end_prop)))); 652 } 653 654 /* Populate device tree for each chip */ 655 for (i = 0; i < pnv->num_chips; i++) { 656 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 657 } 658 659 /* Populate ISA devices on chip 0 */ 660 pnv_dt_isa(pnv, fdt); 661 662 if (pnv->bmc) { 663 pnv_dt_bmc_sensors(pnv->bmc, fdt); 664 } 665 666 /* Create an extra node for power management on machines that support it */ 667 if (pmc->dt_power_mgt) { 668 pmc->dt_power_mgt(pnv, fdt); 669 } 670 671 return fdt; 672 } 673 674 static void pnv_powerdown_notify(Notifier *n, void *opaque) 675 { 676 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 677 678 if (pnv->bmc) { 679 pnv_bmc_powerdown(pnv->bmc); 680 } 681 } 682 683 static void pnv_reset(MachineState *machine, ShutdownCause reason) 684 { 685 PnvMachineState *pnv = PNV_MACHINE(machine); 686 IPMIBmc *bmc; 687 void *fdt; 688 689 qemu_devices_reset(reason); 690 691 /* 692 * The machine should provide by default an internal BMC simulator. 693 * If not, try to use the BMC device that was provided on the command 694 * line. 695 */ 696 bmc = pnv_bmc_find(&error_fatal); 697 if (!pnv->bmc) { 698 if (!bmc) { 699 if (!qtest_enabled()) { 700 warn_report("machine has no BMC device. Use '-device " 701 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 702 "to define one"); 703 } 704 } else { 705 pnv_bmc_set_pnor(bmc, pnv->pnor); 706 pnv->bmc = bmc; 707 } 708 } 709 710 fdt = pnv_dt_create(machine); 711 712 /* Pack resulting tree */ 713 _FDT((fdt_pack(fdt))); 714 715 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 716 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 717 718 /* 719 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 720 * the existing machine->fdt to avoid leaking it during 721 * a reset. 722 */ 723 g_free(machine->fdt); 724 machine->fdt = fdt; 725 } 726 727 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 728 { 729 Pnv8Chip *chip8 = PNV8_CHIP(chip); 730 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 731 732 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 733 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 734 } 735 736 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 737 { 738 Pnv8Chip *chip8 = PNV8_CHIP(chip); 739 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 740 741 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 742 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 743 } 744 745 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 746 { 747 Pnv9Chip *chip9 = PNV9_CHIP(chip); 748 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 749 750 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 751 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 752 } 753 754 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 755 { 756 Pnv10Chip *chip10 = PNV10_CHIP(chip); 757 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 758 759 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 760 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 761 } 762 763 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 764 { 765 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 766 } 767 768 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 769 { 770 Pnv8Chip *chip8 = PNV8_CHIP(chip); 771 int i; 772 773 g_autoptr(GString) buf = g_string_new(""); 774 g_autoptr(HumanReadableText) info = NULL; 775 776 ics_pic_print_info(&chip8->psi.ics, buf); 777 778 for (i = 0; i < chip8->num_phbs; i++) { 779 PnvPHB *phb = chip8->phbs[i]; 780 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 781 782 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 783 ics_pic_print_info(&phb3->lsis, buf); 784 } 785 786 info = human_readable_text_from_str(buf); 787 monitor_puts(mon, info->human_readable_text); 788 } 789 790 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 791 { 792 GString *buf = opaque; 793 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 794 795 if (!phb) { 796 return 0; 797 } 798 799 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 800 801 return 0; 802 } 803 804 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 805 { 806 Pnv9Chip *chip9 = PNV9_CHIP(chip); 807 g_autoptr(GString) buf = g_string_new(""); 808 g_autoptr(HumanReadableText) info = NULL; 809 810 pnv_xive_pic_print_info(&chip9->xive, buf); 811 pnv_psi_pic_print_info(&chip9->psi, buf); 812 object_child_foreach_recursive(OBJECT(chip), 813 pnv_chip_power9_pic_print_info_child, buf); 814 815 info = human_readable_text_from_str(buf); 816 monitor_puts(mon, info->human_readable_text); 817 } 818 819 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 820 uint32_t core_id) 821 { 822 return PNV_XSCOM_EX_BASE(core_id); 823 } 824 825 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 826 uint32_t core_id) 827 { 828 return PNV9_XSCOM_EC_BASE(core_id); 829 } 830 831 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 832 uint32_t core_id) 833 { 834 return PNV10_XSCOM_EC_BASE(core_id); 835 } 836 837 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 838 { 839 PowerPCCPUClass *ppc_default = 840 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 841 PowerPCCPUClass *ppc = 842 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 843 844 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 845 } 846 847 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 848 { 849 ISADevice *dev = isa_new("isa-ipmi-bt"); 850 851 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 852 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 853 isa_realize_and_unref(dev, bus, &error_fatal); 854 } 855 856 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 857 { 858 Pnv10Chip *chip10 = PNV10_CHIP(chip); 859 g_autoptr(GString) buf = g_string_new(""); 860 g_autoptr(HumanReadableText) info = NULL; 861 862 pnv_xive2_pic_print_info(&chip10->xive, buf); 863 pnv_psi_pic_print_info(&chip10->psi, buf); 864 object_child_foreach_recursive(OBJECT(chip), 865 pnv_chip_power9_pic_print_info_child, buf); 866 867 info = human_readable_text_from_str(buf); 868 monitor_puts(mon, info->human_readable_text); 869 } 870 871 /* Always give the first 1GB to chip 0 else we won't boot */ 872 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 873 { 874 MachineState *machine = MACHINE(pnv); 875 uint64_t ram_per_chip; 876 877 assert(machine->ram_size >= 1 * GiB); 878 879 ram_per_chip = machine->ram_size / pnv->num_chips; 880 if (ram_per_chip >= 1 * GiB) { 881 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 882 } 883 884 assert(pnv->num_chips > 1); 885 886 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 887 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 888 } 889 890 static void pnv_init(MachineState *machine) 891 { 892 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 893 PnvMachineState *pnv = PNV_MACHINE(machine); 894 MachineClass *mc = MACHINE_GET_CLASS(machine); 895 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 896 char *fw_filename; 897 long fw_size; 898 uint64_t chip_ram_start = 0; 899 int i; 900 char *chip_typename; 901 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 902 DeviceState *dev; 903 904 if (kvm_enabled()) { 905 error_report("machine %s does not support the KVM accelerator", 906 mc->name); 907 exit(EXIT_FAILURE); 908 } 909 910 /* allocate RAM */ 911 if (machine->ram_size < mc->default_ram_size) { 912 char *sz = size_to_str(mc->default_ram_size); 913 error_report("Invalid RAM size, should be bigger than %s", sz); 914 g_free(sz); 915 exit(EXIT_FAILURE); 916 } 917 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 918 919 /* 920 * Create our simple PNOR device 921 */ 922 dev = qdev_new(TYPE_PNV_PNOR); 923 if (pnor) { 924 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 925 } 926 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 927 pnv->pnor = PNV_PNOR(dev); 928 929 /* load skiboot firmware */ 930 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 931 if (!fw_filename) { 932 error_report("Could not find OPAL firmware '%s'", bios_name); 933 exit(1); 934 } 935 936 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 937 if (fw_size < 0) { 938 error_report("Could not load OPAL firmware '%s'", fw_filename); 939 exit(1); 940 } 941 g_free(fw_filename); 942 943 /* load kernel */ 944 if (machine->kernel_filename) { 945 long kernel_size; 946 947 kernel_size = load_image_targphys(machine->kernel_filename, 948 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 949 if (kernel_size < 0) { 950 error_report("Could not load kernel '%s'", 951 machine->kernel_filename); 952 exit(1); 953 } 954 } 955 956 /* load initrd */ 957 if (machine->initrd_filename) { 958 pnv->initrd_base = INITRD_LOAD_ADDR; 959 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 960 pnv->initrd_base, INITRD_MAX_SIZE); 961 if (pnv->initrd_size < 0) { 962 error_report("Could not load initial ram disk '%s'", 963 machine->initrd_filename); 964 exit(1); 965 } 966 } 967 968 /* MSIs are supported on this platform */ 969 msi_nonbroken = true; 970 971 /* 972 * Check compatibility of the specified CPU with the machine 973 * default. 974 */ 975 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 976 error_report("invalid CPU model '%s' for %s machine", 977 machine->cpu_type, mc->name); 978 exit(1); 979 } 980 981 /* Create the processor chips */ 982 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 983 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 984 i, machine->cpu_type); 985 if (!object_class_by_name(chip_typename)) { 986 error_report("invalid chip model '%.*s' for %s machine", 987 i, machine->cpu_type, mc->name); 988 exit(1); 989 } 990 991 pnv->num_chips = 992 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 993 994 if (machine->smp.threads > 8) { 995 error_report("Cannot support more than 8 threads/core " 996 "on a powernv machine"); 997 exit(1); 998 } 999 if (!is_power_of_2(machine->smp.threads)) { 1000 error_report("Cannot support %d threads/core on a powernv" 1001 "machine because it must be a power of 2", 1002 machine->smp.threads); 1003 exit(1); 1004 } 1005 /* 1006 * TODO: should we decide on how many chips we can create based 1007 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1008 */ 1009 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1010 error_report("invalid number of chips: '%d'", pnv->num_chips); 1011 error_printf( 1012 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1013 exit(1); 1014 } 1015 1016 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1017 for (i = 0; i < pnv->num_chips; i++) { 1018 char chip_name[32]; 1019 Object *chip = OBJECT(qdev_new(chip_typename)); 1020 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1021 1022 pnv->chips[i] = PNV_CHIP(chip); 1023 1024 /* Distribute RAM among the chips */ 1025 object_property_set_int(chip, "ram-start", chip_ram_start, 1026 &error_fatal); 1027 object_property_set_int(chip, "ram-size", chip_ram_size, 1028 &error_fatal); 1029 chip_ram_start += chip_ram_size; 1030 1031 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1032 object_property_add_child(OBJECT(pnv), chip_name, chip); 1033 object_property_set_int(chip, "chip-id", i, &error_fatal); 1034 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1035 &error_fatal); 1036 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1037 &error_fatal); 1038 /* 1039 * The POWER8 machine use the XICS interrupt interface. 1040 * Propagate the XICS fabric to the chip and its controllers. 1041 */ 1042 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1043 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1044 } 1045 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1046 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1047 &error_abort); 1048 } 1049 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1050 } 1051 g_free(chip_typename); 1052 1053 /* Instantiate ISA bus on chip 0 */ 1054 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1055 1056 /* Create serial port */ 1057 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1058 1059 /* Create an RTC ISA device too */ 1060 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1061 1062 /* 1063 * Create the machine BMC simulator and the IPMI BT device for 1064 * communication with the BMC 1065 */ 1066 if (defaults_enabled()) { 1067 pnv->bmc = pnv_bmc_create(pnv->pnor); 1068 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1069 } 1070 1071 /* 1072 * The PNOR is mapped on the LPC FW address space by the BMC. 1073 * Since we can not reach the remote BMC machine with LPC memops, 1074 * map it always for now. 1075 */ 1076 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1077 &pnv->pnor->mmio); 1078 1079 /* 1080 * OpenPOWER systems use a IPMI SEL Event message to notify the 1081 * host to powerdown 1082 */ 1083 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1084 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1085 1086 /* 1087 * Create/Connect any machine-specific I2C devices 1088 */ 1089 if (pmc->i2c_init) { 1090 pmc->i2c_init(pnv); 1091 } 1092 } 1093 1094 /* 1095 * 0:21 Reserved - Read as zeros 1096 * 22:24 Chip ID 1097 * 25:28 Core number 1098 * 29:31 Thread ID 1099 */ 1100 static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, 1101 uint32_t thread_id) 1102 { 1103 return (chip->chip_id << 7) | (core_id << 3) | thread_id; 1104 } 1105 1106 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1107 Error **errp) 1108 { 1109 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1110 Error *local_err = NULL; 1111 Object *obj; 1112 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1113 1114 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1115 if (local_err) { 1116 error_propagate(errp, local_err); 1117 return; 1118 } 1119 1120 pnv_cpu->intc = obj; 1121 } 1122 1123 1124 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1125 { 1126 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1127 1128 icp_reset(ICP(pnv_cpu->intc)); 1129 } 1130 1131 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1132 { 1133 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1134 1135 icp_destroy(ICP(pnv_cpu->intc)); 1136 pnv_cpu->intc = NULL; 1137 } 1138 1139 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1140 GString *buf) 1141 { 1142 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1143 } 1144 1145 /* 1146 * 0:48 Reserved - Read as zeroes 1147 * 49:52 Node ID 1148 * 53:55 Chip ID 1149 * 56 Reserved - Read as zero 1150 * 57:61 Core number 1151 * 62:63 Thread ID 1152 * 1153 * We only care about the lower bits. uint32_t is fine for the moment. 1154 */ 1155 static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, 1156 uint32_t thread_id) 1157 { 1158 if (chip->nr_threads == 8) { 1159 return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) | 1160 (thread_id >> 1); 1161 } else { 1162 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1163 } 1164 } 1165 1166 /* 1167 * 0:48 Reserved - Read as zeroes 1168 * 49:52 Node ID 1169 * 53:55 Chip ID 1170 * 56 Reserved - Read as zero 1171 * 57:59 Quad ID 1172 * 60 Core Chiplet Pair ID 1173 * 61:63 Thread/Core Chiplet ID t0-t2 1174 * 1175 * We only care about the lower bits. uint32_t is fine for the moment. 1176 */ 1177 static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, 1178 uint32_t thread_id) 1179 { 1180 if (chip->nr_threads == 8) { 1181 return (chip->chip_id << 8) | ((core_id / 4) << 4) | 1182 ((core_id % 2) << 3) | thread_id; 1183 } else { 1184 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1185 } 1186 } 1187 1188 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1189 Error **errp) 1190 { 1191 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1192 Error *local_err = NULL; 1193 Object *obj; 1194 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1195 1196 /* 1197 * The core creates its interrupt presenter but the XIVE interrupt 1198 * controller object is initialized afterwards. Hopefully, it's 1199 * only used at runtime. 1200 */ 1201 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1202 &local_err); 1203 if (local_err) { 1204 error_propagate(errp, local_err); 1205 return; 1206 } 1207 1208 pnv_cpu->intc = obj; 1209 } 1210 1211 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1212 { 1213 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1214 1215 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1216 } 1217 1218 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1219 { 1220 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1221 1222 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1223 pnv_cpu->intc = NULL; 1224 } 1225 1226 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1227 GString *buf) 1228 { 1229 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1230 } 1231 1232 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1233 Error **errp) 1234 { 1235 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1236 Error *local_err = NULL; 1237 Object *obj; 1238 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1239 1240 /* 1241 * The core creates its interrupt presenter but the XIVE2 interrupt 1242 * controller object is initialized afterwards. Hopefully, it's 1243 * only used at runtime. 1244 */ 1245 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1246 &local_err); 1247 if (local_err) { 1248 error_propagate(errp, local_err); 1249 return; 1250 } 1251 1252 pnv_cpu->intc = obj; 1253 } 1254 1255 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1256 { 1257 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1258 1259 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1260 } 1261 1262 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1263 { 1264 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1265 1266 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1267 pnv_cpu->intc = NULL; 1268 } 1269 1270 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1271 GString *buf) 1272 { 1273 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1274 } 1275 1276 /* 1277 * Allowed core identifiers on a POWER8 Processor Chip : 1278 * 1279 * <EX0 reserved> 1280 * EX1 - Venice only 1281 * EX2 - Venice only 1282 * EX3 - Venice only 1283 * EX4 1284 * EX5 1285 * EX6 1286 * <EX7,8 reserved> <reserved> 1287 * EX9 - Venice only 1288 * EX10 - Venice only 1289 * EX11 - Venice only 1290 * EX12 1291 * EX13 1292 * EX14 1293 * <EX15 reserved> 1294 */ 1295 #define POWER8E_CORE_MASK (0x7070ull) 1296 #define POWER8_CORE_MASK (0x7e7eull) 1297 1298 /* 1299 * POWER9 has 24 cores, ids starting at 0x0 1300 */ 1301 #define POWER9_CORE_MASK (0xffffffffffffffull) 1302 1303 1304 #define POWER10_CORE_MASK (0xffffffffffffffull) 1305 1306 static void pnv_chip_power8_instance_init(Object *obj) 1307 { 1308 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1309 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1310 int i; 1311 1312 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1313 (Object **)&chip8->xics, 1314 object_property_allow_set_link, 1315 OBJ_PROP_LINK_STRONG); 1316 1317 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1318 1319 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1320 1321 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1322 1323 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1324 1325 if (defaults_enabled()) { 1326 chip8->num_phbs = pcc->num_phbs; 1327 1328 for (i = 0; i < chip8->num_phbs; i++) { 1329 Object *phb = object_new(TYPE_PNV_PHB); 1330 1331 /* 1332 * We need the chip to parent the PHB to allow the DT 1333 * to build correctly (via pnv_xscom_dt()). 1334 * 1335 * TODO: the PHB should be parented by a PEC device that, at 1336 * this moment, is not modelled powernv8/phb3. 1337 */ 1338 object_property_add_child(obj, "phb[*]", phb); 1339 chip8->phbs[i] = PNV_PHB(phb); 1340 } 1341 } 1342 1343 } 1344 1345 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1346 { 1347 PnvChip *chip = PNV_CHIP(chip8); 1348 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1349 int i, j; 1350 char *name; 1351 1352 name = g_strdup_printf("icp-%x", chip->chip_id); 1353 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1354 g_free(name); 1355 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1356 &chip8->icp_mmio); 1357 1358 /* Map the ICP registers for each thread */ 1359 for (i = 0; i < chip->nr_cores; i++) { 1360 PnvCore *pnv_core = chip->cores[i]; 1361 int core_hwid = CPU_CORE(pnv_core)->core_id; 1362 1363 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1364 uint32_t pir = pcc->chip_pir(chip, core_hwid, j); 1365 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1366 1367 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1368 &icp->mmio); 1369 } 1370 } 1371 } 1372 1373 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1374 { 1375 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1376 PnvChip *chip = PNV_CHIP(dev); 1377 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1378 Pnv8Psi *psi8 = &chip8->psi; 1379 Error *local_err = NULL; 1380 int i; 1381 1382 assert(chip8->xics); 1383 1384 /* XSCOM bridge is first */ 1385 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1386 1387 pcc->parent_realize(dev, &local_err); 1388 if (local_err) { 1389 error_propagate(errp, local_err); 1390 return; 1391 } 1392 1393 /* Processor Service Interface (PSI) Host Bridge */ 1394 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1395 &error_fatal); 1396 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1397 OBJECT(chip8->xics), &error_abort); 1398 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1399 return; 1400 } 1401 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1402 &PNV_PSI(psi8)->xscom_regs); 1403 1404 /* Create LPC controller */ 1405 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1406 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1407 1408 chip->fw_mr = &chip8->lpc.isa_fw; 1409 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1410 (uint64_t) PNV_XSCOM_BASE(chip), 1411 PNV_XSCOM_LPC_BASE); 1412 1413 /* 1414 * Interrupt Management Area. This is the memory region holding 1415 * all the Interrupt Control Presenter (ICP) registers 1416 */ 1417 pnv_chip_icp_realize(chip8, &local_err); 1418 if (local_err) { 1419 error_propagate(errp, local_err); 1420 return; 1421 } 1422 1423 /* Create the simplified OCC model */ 1424 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1425 return; 1426 } 1427 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1428 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1429 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1430 1431 /* OCC SRAM model */ 1432 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1433 &chip8->occ.sram_regs); 1434 1435 /* HOMER */ 1436 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1437 &error_abort); 1438 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1439 return; 1440 } 1441 /* Homer Xscom region */ 1442 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1443 1444 /* Homer mmio region */ 1445 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1446 &chip8->homer.regs); 1447 1448 /* PHB controllers */ 1449 for (i = 0; i < chip8->num_phbs; i++) { 1450 PnvPHB *phb = chip8->phbs[i]; 1451 1452 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1453 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1454 &error_fatal); 1455 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1456 &error_fatal); 1457 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1458 return; 1459 } 1460 } 1461 } 1462 1463 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1464 { 1465 addr &= (PNV_XSCOM_SIZE - 1); 1466 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1467 } 1468 1469 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1470 { 1471 DeviceClass *dc = DEVICE_CLASS(klass); 1472 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1473 1474 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1475 k->cores_mask = POWER8E_CORE_MASK; 1476 k->num_phbs = 3; 1477 k->chip_pir = pnv_chip_pir_p8; 1478 k->intc_create = pnv_chip_power8_intc_create; 1479 k->intc_reset = pnv_chip_power8_intc_reset; 1480 k->intc_destroy = pnv_chip_power8_intc_destroy; 1481 k->intc_print_info = pnv_chip_power8_intc_print_info; 1482 k->isa_create = pnv_chip_power8_isa_create; 1483 k->dt_populate = pnv_chip_power8_dt_populate; 1484 k->pic_print_info = pnv_chip_power8_pic_print_info; 1485 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1486 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1487 dc->desc = "PowerNV Chip POWER8E"; 1488 1489 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1490 &k->parent_realize); 1491 } 1492 1493 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1494 { 1495 DeviceClass *dc = DEVICE_CLASS(klass); 1496 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1497 1498 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1499 k->cores_mask = POWER8_CORE_MASK; 1500 k->num_phbs = 3; 1501 k->chip_pir = pnv_chip_pir_p8; 1502 k->intc_create = pnv_chip_power8_intc_create; 1503 k->intc_reset = pnv_chip_power8_intc_reset; 1504 k->intc_destroy = pnv_chip_power8_intc_destroy; 1505 k->intc_print_info = pnv_chip_power8_intc_print_info; 1506 k->isa_create = pnv_chip_power8_isa_create; 1507 k->dt_populate = pnv_chip_power8_dt_populate; 1508 k->pic_print_info = pnv_chip_power8_pic_print_info; 1509 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1510 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1511 dc->desc = "PowerNV Chip POWER8"; 1512 1513 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1514 &k->parent_realize); 1515 } 1516 1517 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1518 { 1519 DeviceClass *dc = DEVICE_CLASS(klass); 1520 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1521 1522 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1523 k->cores_mask = POWER8_CORE_MASK; 1524 k->num_phbs = 4; 1525 k->chip_pir = pnv_chip_pir_p8; 1526 k->intc_create = pnv_chip_power8_intc_create; 1527 k->intc_reset = pnv_chip_power8_intc_reset; 1528 k->intc_destroy = pnv_chip_power8_intc_destroy; 1529 k->intc_print_info = pnv_chip_power8_intc_print_info; 1530 k->isa_create = pnv_chip_power8nvl_isa_create; 1531 k->dt_populate = pnv_chip_power8_dt_populate; 1532 k->pic_print_info = pnv_chip_power8_pic_print_info; 1533 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1534 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1535 dc->desc = "PowerNV Chip POWER8NVL"; 1536 1537 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1538 &k->parent_realize); 1539 } 1540 1541 static void pnv_chip_power9_instance_init(Object *obj) 1542 { 1543 PnvChip *chip = PNV_CHIP(obj); 1544 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1545 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1546 int i; 1547 1548 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1549 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1550 "xive-fabric"); 1551 1552 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1553 1554 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1555 1556 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1557 1558 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1559 1560 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1561 1562 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1563 1564 /* Number of PECs is the chip default */ 1565 chip->num_pecs = pcc->num_pecs; 1566 1567 for (i = 0; i < chip->num_pecs; i++) { 1568 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1569 TYPE_PNV_PHB4_PEC); 1570 } 1571 1572 for (i = 0; i < pcc->i2c_num_engines; i++) { 1573 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1574 } 1575 } 1576 1577 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1578 PnvCore *pnv_core, 1579 const char *type) 1580 { 1581 char eq_name[32]; 1582 int core_id = CPU_CORE(pnv_core)->core_id; 1583 1584 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1585 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1586 sizeof(*eq), type, 1587 &error_fatal, NULL); 1588 1589 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1590 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1591 } 1592 1593 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1594 { 1595 PnvChip *chip = PNV_CHIP(chip9); 1596 int i; 1597 1598 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1599 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1600 1601 for (i = 0; i < chip9->nr_quads; i++) { 1602 PnvQuad *eq = &chip9->quads[i]; 1603 1604 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1605 PNV_QUAD_TYPE_NAME("power9")); 1606 1607 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1608 &eq->xscom_regs); 1609 } 1610 } 1611 1612 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1613 { 1614 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1615 int i; 1616 1617 for (i = 0; i < chip->num_pecs; i++) { 1618 PnvPhb4PecState *pec = &chip9->pecs[i]; 1619 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1620 uint32_t pec_nest_base; 1621 uint32_t pec_pci_base; 1622 1623 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1624 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1625 &error_fatal); 1626 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1627 &error_fatal); 1628 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1629 return; 1630 } 1631 1632 pec_nest_base = pecc->xscom_nest_base(pec); 1633 pec_pci_base = pecc->xscom_pci_base(pec); 1634 1635 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1636 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1637 } 1638 } 1639 1640 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1641 { 1642 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1643 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1644 PnvChip *chip = PNV_CHIP(dev); 1645 Pnv9Psi *psi9 = &chip9->psi; 1646 Error *local_err = NULL; 1647 int i; 1648 1649 /* XSCOM bridge is first */ 1650 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1651 1652 pcc->parent_realize(dev, &local_err); 1653 if (local_err) { 1654 error_propagate(errp, local_err); 1655 return; 1656 } 1657 1658 pnv_chip_quad_realize(chip9, &local_err); 1659 if (local_err) { 1660 error_propagate(errp, local_err); 1661 return; 1662 } 1663 1664 /* XIVE interrupt controller (POWER9) */ 1665 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1666 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1667 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1668 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1669 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1670 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1671 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1672 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1673 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1674 &error_abort); 1675 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1676 return; 1677 } 1678 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1679 &chip9->xive.xscom_regs); 1680 1681 /* Processor Service Interface (PSI) Host Bridge */ 1682 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1683 &error_fatal); 1684 /* This is the only device with 4k ESB pages */ 1685 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1686 &error_fatal); 1687 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1688 return; 1689 } 1690 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1691 &PNV_PSI(psi9)->xscom_regs); 1692 1693 /* LPC */ 1694 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1695 return; 1696 } 1697 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1698 &chip9->lpc.xscom_regs); 1699 1700 chip->fw_mr = &chip9->lpc.isa_fw; 1701 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1702 (uint64_t) PNV9_LPCM_BASE(chip)); 1703 1704 /* ChipTOD */ 1705 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1706 chip->chip_id == 0, &error_abort); 1707 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1708 chip->chip_id == 1, &error_abort); 1709 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1710 &error_abort); 1711 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1712 return; 1713 } 1714 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1715 &chip9->chiptod.xscom_regs); 1716 1717 /* Create the simplified OCC model */ 1718 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1719 return; 1720 } 1721 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1722 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1723 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1724 1725 /* OCC SRAM model */ 1726 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1727 &chip9->occ.sram_regs); 1728 1729 /* SBE */ 1730 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1731 return; 1732 } 1733 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1734 &chip9->sbe.xscom_ctrl_regs); 1735 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1736 &chip9->sbe.xscom_mbox_regs); 1737 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1738 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1739 1740 /* HOMER */ 1741 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1742 &error_abort); 1743 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1744 return; 1745 } 1746 /* Homer Xscom region */ 1747 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1748 1749 /* Homer mmio region */ 1750 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1751 &chip9->homer.regs); 1752 1753 /* PEC PHBs */ 1754 pnv_chip_power9_pec_realize(chip, &local_err); 1755 if (local_err) { 1756 error_propagate(errp, local_err); 1757 return; 1758 } 1759 1760 /* 1761 * I2C 1762 */ 1763 for (i = 0; i < pcc->i2c_num_engines; i++) { 1764 Object *obj = OBJECT(&chip9->i2c[i]); 1765 1766 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1767 object_property_set_int(obj, "num-busses", 1768 pcc->i2c_ports_per_engine[i], 1769 &error_fatal); 1770 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1771 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1772 return; 1773 } 1774 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1775 (chip9->i2c[i].engine - 1) * 1776 PNV9_XSCOM_I2CM_SIZE, 1777 &chip9->i2c[i].xscom_regs); 1778 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1779 qdev_get_gpio_in(DEVICE(psi9), 1780 PSIHB9_IRQ_SBE_I2C)); 1781 } 1782 } 1783 1784 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1785 { 1786 addr &= (PNV9_XSCOM_SIZE - 1); 1787 return addr >> 3; 1788 } 1789 1790 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1791 { 1792 DeviceClass *dc = DEVICE_CLASS(klass); 1793 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1794 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1795 1796 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1797 k->cores_mask = POWER9_CORE_MASK; 1798 k->chip_pir = pnv_chip_pir_p9; 1799 k->intc_create = pnv_chip_power9_intc_create; 1800 k->intc_reset = pnv_chip_power9_intc_reset; 1801 k->intc_destroy = pnv_chip_power9_intc_destroy; 1802 k->intc_print_info = pnv_chip_power9_intc_print_info; 1803 k->isa_create = pnv_chip_power9_isa_create; 1804 k->dt_populate = pnv_chip_power9_dt_populate; 1805 k->pic_print_info = pnv_chip_power9_pic_print_info; 1806 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1807 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1808 dc->desc = "PowerNV Chip POWER9"; 1809 k->num_pecs = PNV9_CHIP_MAX_PEC; 1810 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1811 k->i2c_ports_per_engine = i2c_ports_per_engine; 1812 1813 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1814 &k->parent_realize); 1815 } 1816 1817 static void pnv_chip_power10_instance_init(Object *obj) 1818 { 1819 PnvChip *chip = PNV_CHIP(obj); 1820 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1821 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1822 int i; 1823 1824 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1825 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1826 "xive-fabric"); 1827 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1828 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1829 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1830 TYPE_PNV10_CHIPTOD); 1831 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1832 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1833 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1834 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1835 TYPE_PNV_N1_CHIPLET); 1836 1837 chip->num_pecs = pcc->num_pecs; 1838 1839 for (i = 0; i < chip->num_pecs; i++) { 1840 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1841 TYPE_PNV_PHB5_PEC); 1842 } 1843 1844 for (i = 0; i < pcc->i2c_num_engines; i++) { 1845 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1846 } 1847 } 1848 1849 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1850 { 1851 PnvChip *chip = PNV_CHIP(chip10); 1852 int i; 1853 1854 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1855 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1856 1857 for (i = 0; i < chip10->nr_quads; i++) { 1858 PnvQuad *eq = &chip10->quads[i]; 1859 1860 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1861 PNV_QUAD_TYPE_NAME("power10")); 1862 1863 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1864 &eq->xscom_regs); 1865 1866 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1867 &eq->xscom_qme_regs); 1868 } 1869 } 1870 1871 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1872 { 1873 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1874 int i; 1875 1876 for (i = 0; i < chip->num_pecs; i++) { 1877 PnvPhb4PecState *pec = &chip10->pecs[i]; 1878 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1879 uint32_t pec_nest_base; 1880 uint32_t pec_pci_base; 1881 1882 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1883 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1884 &error_fatal); 1885 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1886 &error_fatal); 1887 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1888 return; 1889 } 1890 1891 pec_nest_base = pecc->xscom_nest_base(pec); 1892 pec_pci_base = pecc->xscom_pci_base(pec); 1893 1894 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1895 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1896 } 1897 } 1898 1899 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1900 { 1901 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1902 PnvChip *chip = PNV_CHIP(dev); 1903 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1904 Error *local_err = NULL; 1905 int i; 1906 1907 /* XSCOM bridge is first */ 1908 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1909 1910 pcc->parent_realize(dev, &local_err); 1911 if (local_err) { 1912 error_propagate(errp, local_err); 1913 return; 1914 } 1915 1916 pnv_chip_power10_quad_realize(chip10, &local_err); 1917 if (local_err) { 1918 error_propagate(errp, local_err); 1919 return; 1920 } 1921 1922 /* XIVE2 interrupt controller (POWER10) */ 1923 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1924 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1925 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1926 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1927 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1928 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1929 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1930 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1931 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1932 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1933 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1934 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1935 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1936 &error_abort); 1937 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1938 return; 1939 } 1940 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1941 &chip10->xive.xscom_regs); 1942 1943 /* Processor Service Interface (PSI) Host Bridge */ 1944 object_property_set_int(OBJECT(&chip10->psi), "bar", 1945 PNV10_PSIHB_BASE(chip), &error_fatal); 1946 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1947 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1948 &error_fatal); 1949 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1950 return; 1951 } 1952 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1953 &PNV_PSI(&chip10->psi)->xscom_regs); 1954 1955 /* LPC */ 1956 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1957 return; 1958 } 1959 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1960 &chip10->lpc.xscom_regs); 1961 1962 chip->fw_mr = &chip10->lpc.isa_fw; 1963 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1964 (uint64_t) PNV10_LPCM_BASE(chip)); 1965 1966 /* ChipTOD */ 1967 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 1968 chip->chip_id == 0, &error_abort); 1969 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 1970 chip->chip_id == 1, &error_abort); 1971 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 1972 &error_abort); 1973 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 1974 return; 1975 } 1976 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 1977 &chip10->chiptod.xscom_regs); 1978 1979 /* Create the simplified OCC model */ 1980 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1981 return; 1982 } 1983 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1984 &chip10->occ.xscom_regs); 1985 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1986 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1987 1988 /* OCC SRAM model */ 1989 memory_region_add_subregion(get_system_memory(), 1990 PNV10_OCC_SENSOR_BASE(chip), 1991 &chip10->occ.sram_regs); 1992 1993 /* SBE */ 1994 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1995 return; 1996 } 1997 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1998 &chip10->sbe.xscom_ctrl_regs); 1999 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2000 &chip10->sbe.xscom_mbox_regs); 2001 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2002 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2003 2004 /* HOMER */ 2005 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2006 &error_abort); 2007 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2008 return; 2009 } 2010 /* Homer Xscom region */ 2011 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2012 &chip10->homer.pba_regs); 2013 2014 /* Homer mmio region */ 2015 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2016 &chip10->homer.regs); 2017 2018 /* N1 chiplet */ 2019 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2020 return; 2021 } 2022 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2023 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2024 2025 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2026 &chip10->n1_chiplet.xscom_pb_eq_mr); 2027 2028 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2029 &chip10->n1_chiplet.xscom_pb_es_mr); 2030 2031 /* PHBs */ 2032 pnv_chip_power10_phb_realize(chip, &local_err); 2033 if (local_err) { 2034 error_propagate(errp, local_err); 2035 return; 2036 } 2037 2038 2039 /* 2040 * I2C 2041 */ 2042 for (i = 0; i < pcc->i2c_num_engines; i++) { 2043 Object *obj = OBJECT(&chip10->i2c[i]); 2044 2045 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2046 object_property_set_int(obj, "num-busses", 2047 pcc->i2c_ports_per_engine[i], 2048 &error_fatal); 2049 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2050 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2051 return; 2052 } 2053 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2054 (chip10->i2c[i].engine - 1) * 2055 PNV10_XSCOM_I2CM_SIZE, 2056 &chip10->i2c[i].xscom_regs); 2057 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2058 qdev_get_gpio_in(DEVICE(&chip10->psi), 2059 PSIHB9_IRQ_SBE_I2C)); 2060 } 2061 2062 } 2063 2064 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2065 { 2066 int i; 2067 for (i = 0; i < pnv->num_chips; i++) { 2068 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2069 2070 /* 2071 * Add a PCA9552 I2C device for PCIe hotplug control 2072 * to engine 2, bus 1, address 0x63 2073 */ 2074 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2075 "pca9552", 0x63); 2076 2077 /* 2078 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2079 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2080 * after hypervisor code sets a SLOTx_EN pin high. 2081 */ 2082 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2083 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2084 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2085 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2086 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2087 2088 /* 2089 * Add a PCA9554 I2C device for cable card presence detection 2090 * to engine 2, bus 1, address 0x25 2091 */ 2092 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2093 } 2094 } 2095 2096 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2097 { 2098 addr &= (PNV10_XSCOM_SIZE - 1); 2099 return addr >> 3; 2100 } 2101 2102 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2103 { 2104 DeviceClass *dc = DEVICE_CLASS(klass); 2105 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2106 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2107 2108 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 2109 k->cores_mask = POWER10_CORE_MASK; 2110 k->chip_pir = pnv_chip_pir_p10; 2111 k->intc_create = pnv_chip_power10_intc_create; 2112 k->intc_reset = pnv_chip_power10_intc_reset; 2113 k->intc_destroy = pnv_chip_power10_intc_destroy; 2114 k->intc_print_info = pnv_chip_power10_intc_print_info; 2115 k->isa_create = pnv_chip_power10_isa_create; 2116 k->dt_populate = pnv_chip_power10_dt_populate; 2117 k->pic_print_info = pnv_chip_power10_pic_print_info; 2118 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2119 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2120 dc->desc = "PowerNV Chip POWER10"; 2121 k->num_pecs = PNV10_CHIP_MAX_PEC; 2122 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2123 k->i2c_ports_per_engine = i2c_ports_per_engine; 2124 2125 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2126 &k->parent_realize); 2127 } 2128 2129 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2130 { 2131 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2132 int cores_max; 2133 2134 /* 2135 * No custom mask for this chip, let's use the default one from * 2136 * the chip class 2137 */ 2138 if (!chip->cores_mask) { 2139 chip->cores_mask = pcc->cores_mask; 2140 } 2141 2142 /* filter alien core ids ! some are reserved */ 2143 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2144 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2145 chip->cores_mask); 2146 return; 2147 } 2148 chip->cores_mask &= pcc->cores_mask; 2149 2150 /* now that we have a sane layout, let check the number of cores */ 2151 cores_max = ctpop64(chip->cores_mask); 2152 if (chip->nr_cores > cores_max) { 2153 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2154 cores_max); 2155 return; 2156 } 2157 } 2158 2159 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2160 { 2161 Error *error = NULL; 2162 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2163 const char *typename = pnv_chip_core_typename(chip); 2164 int i, core_hwid; 2165 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2166 2167 if (!object_class_by_name(typename)) { 2168 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2169 return; 2170 } 2171 2172 /* Cores */ 2173 pnv_chip_core_sanitize(chip, &error); 2174 if (error) { 2175 error_propagate(errp, error); 2176 return; 2177 } 2178 2179 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2180 2181 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2182 && (i < chip->nr_cores); core_hwid++) { 2183 char core_name[32]; 2184 PnvCore *pnv_core; 2185 uint64_t xscom_core_base; 2186 2187 if (!(chip->cores_mask & (1ull << core_hwid))) { 2188 continue; 2189 } 2190 2191 pnv_core = PNV_CORE(object_new(typename)); 2192 2193 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2194 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2195 chip->cores[i] = pnv_core; 2196 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2197 chip->nr_threads, &error_fatal); 2198 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2199 core_hwid, &error_fatal); 2200 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2201 &error_fatal); 2202 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2203 &error_fatal); 2204 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2205 &error_abort); 2206 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2207 2208 /* Each core has an XSCOM MMIO region */ 2209 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2210 2211 pnv_xscom_add_subregion(chip, xscom_core_base, 2212 &pnv_core->xscom_regs); 2213 i++; 2214 } 2215 } 2216 2217 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2218 { 2219 PnvChip *chip = PNV_CHIP(dev); 2220 Error *error = NULL; 2221 2222 /* Cores */ 2223 pnv_chip_core_realize(chip, &error); 2224 if (error) { 2225 error_propagate(errp, error); 2226 return; 2227 } 2228 } 2229 2230 static Property pnv_chip_properties[] = { 2231 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2232 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2233 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2234 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2235 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2236 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2237 DEFINE_PROP_END_OF_LIST(), 2238 }; 2239 2240 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2241 { 2242 DeviceClass *dc = DEVICE_CLASS(klass); 2243 2244 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2245 dc->realize = pnv_chip_realize; 2246 device_class_set_props(dc, pnv_chip_properties); 2247 dc->desc = "PowerNV Chip"; 2248 } 2249 2250 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2251 { 2252 int i; 2253 2254 for (i = 0; i < chip->nr_cores; i++) { 2255 PnvCore *pc = chip->cores[i]; 2256 CPUCore *cc = CPU_CORE(pc); 2257 2258 if (cc->core_id == core_id) { 2259 return pc; 2260 } 2261 } 2262 return NULL; 2263 } 2264 2265 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2266 { 2267 int i, j; 2268 2269 for (i = 0; i < chip->nr_cores; i++) { 2270 PnvCore *pc = chip->cores[i]; 2271 CPUCore *cc = CPU_CORE(pc); 2272 2273 for (j = 0; j < cc->nr_threads; j++) { 2274 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2275 return pc->threads[j]; 2276 } 2277 } 2278 } 2279 return NULL; 2280 } 2281 2282 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2283 { 2284 PnvMachineState *pnv = PNV_MACHINE(xi); 2285 int i, j; 2286 2287 for (i = 0; i < pnv->num_chips; i++) { 2288 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2289 2290 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2291 return &chip8->psi.ics; 2292 } 2293 2294 for (j = 0; j < chip8->num_phbs; j++) { 2295 PnvPHB *phb = chip8->phbs[j]; 2296 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2297 2298 if (ics_valid_irq(&phb3->lsis, irq)) { 2299 return &phb3->lsis; 2300 } 2301 2302 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2303 return ICS(&phb3->msis); 2304 } 2305 } 2306 } 2307 return NULL; 2308 } 2309 2310 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2311 { 2312 int i; 2313 2314 for (i = 0; i < pnv->num_chips; i++) { 2315 PnvChip *chip = pnv->chips[i]; 2316 if (chip->chip_id == chip_id) { 2317 return chip; 2318 } 2319 } 2320 return NULL; 2321 } 2322 2323 static void pnv_ics_resend(XICSFabric *xi) 2324 { 2325 PnvMachineState *pnv = PNV_MACHINE(xi); 2326 int i, j; 2327 2328 for (i = 0; i < pnv->num_chips; i++) { 2329 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2330 2331 ics_resend(&chip8->psi.ics); 2332 2333 for (j = 0; j < chip8->num_phbs; j++) { 2334 PnvPHB *phb = chip8->phbs[j]; 2335 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2336 2337 ics_resend(&phb3->lsis); 2338 ics_resend(ICS(&phb3->msis)); 2339 } 2340 } 2341 } 2342 2343 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2344 { 2345 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2346 2347 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2348 } 2349 2350 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2351 Monitor *mon) 2352 { 2353 PnvMachineState *pnv = PNV_MACHINE(obj); 2354 int i; 2355 CPUState *cs; 2356 g_autoptr(GString) buf = g_string_new(""); 2357 g_autoptr(HumanReadableText) info = NULL; 2358 2359 CPU_FOREACH(cs) { 2360 PowerPCCPU *cpu = POWERPC_CPU(cs); 2361 2362 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2363 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2364 buf); 2365 } 2366 info = human_readable_text_from_str(buf); 2367 monitor_puts(mon, info->human_readable_text); 2368 2369 for (i = 0; i < pnv->num_chips; i++) { 2370 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2371 } 2372 } 2373 2374 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2375 uint8_t nvt_blk, uint32_t nvt_idx, 2376 bool cam_ignore, uint8_t priority, 2377 uint32_t logic_serv, 2378 XiveTCTXMatch *match) 2379 { 2380 PnvMachineState *pnv = PNV_MACHINE(xfb); 2381 int total_count = 0; 2382 int i; 2383 2384 for (i = 0; i < pnv->num_chips; i++) { 2385 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2386 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2387 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2388 int count; 2389 2390 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2391 priority, logic_serv, match); 2392 2393 if (count < 0) { 2394 return count; 2395 } 2396 2397 total_count += count; 2398 } 2399 2400 return total_count; 2401 } 2402 2403 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2404 uint8_t nvt_blk, uint32_t nvt_idx, 2405 bool cam_ignore, uint8_t priority, 2406 uint32_t logic_serv, 2407 XiveTCTXMatch *match) 2408 { 2409 PnvMachineState *pnv = PNV_MACHINE(xfb); 2410 int total_count = 0; 2411 int i; 2412 2413 for (i = 0; i < pnv->num_chips; i++) { 2414 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2415 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2416 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2417 int count; 2418 2419 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2420 priority, logic_serv, match); 2421 2422 if (count < 0) { 2423 return count; 2424 } 2425 2426 total_count += count; 2427 } 2428 2429 return total_count; 2430 } 2431 2432 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2433 { 2434 MachineClass *mc = MACHINE_CLASS(oc); 2435 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2436 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2437 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2438 2439 static GlobalProperty phb_compat[] = { 2440 { TYPE_PNV_PHB, "version", "3" }, 2441 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2442 }; 2443 2444 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2445 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2446 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2447 2448 xic->icp_get = pnv_icp_get; 2449 xic->ics_get = pnv_ics_get; 2450 xic->ics_resend = pnv_ics_resend; 2451 2452 pmc->compat = compat; 2453 pmc->compat_size = sizeof(compat); 2454 2455 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2456 } 2457 2458 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2459 { 2460 MachineClass *mc = MACHINE_CLASS(oc); 2461 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2462 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2463 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2464 2465 static GlobalProperty phb_compat[] = { 2466 { TYPE_PNV_PHB, "version", "4" }, 2467 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2468 }; 2469 2470 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2471 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2472 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2473 2474 xfc->match_nvt = pnv_match_nvt; 2475 2476 pmc->compat = compat; 2477 pmc->compat_size = sizeof(compat); 2478 pmc->dt_power_mgt = pnv_dt_power_mgt; 2479 2480 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2481 } 2482 2483 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2484 { 2485 MachineClass *mc = MACHINE_CLASS(oc); 2486 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2487 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2488 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2489 2490 static GlobalProperty phb_compat[] = { 2491 { TYPE_PNV_PHB, "version", "5" }, 2492 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2493 }; 2494 2495 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2496 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2497 2498 mc->alias = "powernv"; 2499 2500 pmc->compat = compat; 2501 pmc->compat_size = sizeof(compat); 2502 pmc->dt_power_mgt = pnv_dt_power_mgt; 2503 2504 xfc->match_nvt = pnv10_xive_match_nvt; 2505 2506 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2507 } 2508 2509 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2510 { 2511 MachineClass *mc = MACHINE_CLASS(oc); 2512 2513 pnv_machine_p10_common_class_init(oc, data); 2514 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2515 } 2516 2517 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2518 { 2519 MachineClass *mc = MACHINE_CLASS(oc); 2520 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2521 2522 pnv_machine_p10_common_class_init(oc, data); 2523 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2524 pmc->i2c_init = pnv_rainier_i2c_init; 2525 } 2526 2527 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2528 { 2529 PnvMachineState *pnv = PNV_MACHINE(obj); 2530 2531 return !!pnv->fw_load_addr; 2532 } 2533 2534 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2535 { 2536 PnvMachineState *pnv = PNV_MACHINE(obj); 2537 2538 if (value) { 2539 pnv->fw_load_addr = 0x8000000; 2540 } 2541 } 2542 2543 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2544 { 2545 CPUPPCState *env = cpu_env(cs); 2546 2547 cpu_synchronize_state(cs); 2548 ppc_cpu_do_system_reset(cs); 2549 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2550 /* 2551 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2552 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2553 * (PPC_BIT(43)). 2554 */ 2555 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2556 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2557 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2558 } 2559 } else { 2560 /* 2561 * For non-powersave system resets, SRR1[42:45] are defined to be 2562 * implementation-dependent. The POWER9 User Manual specifies that 2563 * an external (SCOM driven, which may come from a BMC nmi command or 2564 * another CPU requesting a NMI IPI) system reset exception should be 2565 * 0b0010 (PPC_BIT(44)). 2566 */ 2567 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2568 } 2569 } 2570 2571 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2572 { 2573 CPUState *cs; 2574 2575 CPU_FOREACH(cs) { 2576 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2577 } 2578 } 2579 2580 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2581 { 2582 MachineClass *mc = MACHINE_CLASS(oc); 2583 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2584 NMIClass *nc = NMI_CLASS(oc); 2585 2586 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2587 mc->init = pnv_init; 2588 mc->reset = pnv_reset; 2589 mc->max_cpus = MAX_CPUS; 2590 /* Pnv provides a AHCI device for storage */ 2591 mc->block_default_type = IF_IDE; 2592 mc->no_parallel = 1; 2593 mc->default_boot_order = NULL; 2594 /* 2595 * RAM defaults to less than 2048 for 32-bit hosts, and large 2596 * enough to fit the maximum initrd size at it's load address 2597 */ 2598 mc->default_ram_size = 1 * GiB; 2599 mc->default_ram_id = "pnv.ram"; 2600 ispc->print_info = pnv_pic_print_info; 2601 nc->nmi_monitor_handler = pnv_nmi; 2602 2603 object_class_property_add_bool(oc, "hb-mode", 2604 pnv_machine_get_hb, pnv_machine_set_hb); 2605 object_class_property_set_description(oc, "hb-mode", 2606 "Use a hostboot like boot loader"); 2607 } 2608 2609 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2610 { \ 2611 .name = type, \ 2612 .class_init = class_initfn, \ 2613 .parent = TYPE_PNV8_CHIP, \ 2614 } 2615 2616 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2617 { \ 2618 .name = type, \ 2619 .class_init = class_initfn, \ 2620 .parent = TYPE_PNV9_CHIP, \ 2621 } 2622 2623 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2624 { \ 2625 .name = type, \ 2626 .class_init = class_initfn, \ 2627 .parent = TYPE_PNV10_CHIP, \ 2628 } 2629 2630 static const TypeInfo types[] = { 2631 { 2632 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2633 .parent = MACHINE_TYPE_NAME("powernv10"), 2634 .class_init = pnv_machine_p10_rainier_class_init, 2635 }, 2636 { 2637 .name = MACHINE_TYPE_NAME("powernv10"), 2638 .parent = TYPE_PNV_MACHINE, 2639 .class_init = pnv_machine_power10_class_init, 2640 .interfaces = (InterfaceInfo[]) { 2641 { TYPE_XIVE_FABRIC }, 2642 { }, 2643 }, 2644 }, 2645 { 2646 .name = MACHINE_TYPE_NAME("powernv9"), 2647 .parent = TYPE_PNV_MACHINE, 2648 .class_init = pnv_machine_power9_class_init, 2649 .interfaces = (InterfaceInfo[]) { 2650 { TYPE_XIVE_FABRIC }, 2651 { }, 2652 }, 2653 }, 2654 { 2655 .name = MACHINE_TYPE_NAME("powernv8"), 2656 .parent = TYPE_PNV_MACHINE, 2657 .class_init = pnv_machine_power8_class_init, 2658 .interfaces = (InterfaceInfo[]) { 2659 { TYPE_XICS_FABRIC }, 2660 { }, 2661 }, 2662 }, 2663 { 2664 .name = TYPE_PNV_MACHINE, 2665 .parent = TYPE_MACHINE, 2666 .abstract = true, 2667 .instance_size = sizeof(PnvMachineState), 2668 .class_init = pnv_machine_class_init, 2669 .class_size = sizeof(PnvMachineClass), 2670 .interfaces = (InterfaceInfo[]) { 2671 { TYPE_INTERRUPT_STATS_PROVIDER }, 2672 { TYPE_NMI }, 2673 { }, 2674 }, 2675 }, 2676 { 2677 .name = TYPE_PNV_CHIP, 2678 .parent = TYPE_SYS_BUS_DEVICE, 2679 .class_init = pnv_chip_class_init, 2680 .instance_size = sizeof(PnvChip), 2681 .class_size = sizeof(PnvChipClass), 2682 .abstract = true, 2683 }, 2684 2685 /* 2686 * P10 chip and variants 2687 */ 2688 { 2689 .name = TYPE_PNV10_CHIP, 2690 .parent = TYPE_PNV_CHIP, 2691 .instance_init = pnv_chip_power10_instance_init, 2692 .instance_size = sizeof(Pnv10Chip), 2693 }, 2694 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2695 2696 /* 2697 * P9 chip and variants 2698 */ 2699 { 2700 .name = TYPE_PNV9_CHIP, 2701 .parent = TYPE_PNV_CHIP, 2702 .instance_init = pnv_chip_power9_instance_init, 2703 .instance_size = sizeof(Pnv9Chip), 2704 }, 2705 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2706 2707 /* 2708 * P8 chip and variants 2709 */ 2710 { 2711 .name = TYPE_PNV8_CHIP, 2712 .parent = TYPE_PNV_CHIP, 2713 .instance_init = pnv_chip_power8_instance_init, 2714 .instance_size = sizeof(Pnv8Chip), 2715 }, 2716 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2717 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2718 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2719 pnv_chip_power8nvl_class_init), 2720 }; 2721 2722 DEFINE_TYPES(types) 2723