1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "hw/intc/intc.h" 42 #include "hw/ipmi/ipmi.h" 43 #include "target/ppc/mmu-hash64.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci-host/pnv_phb.h" 46 #include "hw/pci-host/pnv_phb3.h" 47 #include "hw/pci-host/pnv_phb4.h" 48 49 #include "hw/ppc/xics.h" 50 #include "hw/qdev-properties.h" 51 #include "hw/ppc/pnv_chip.h" 52 #include "hw/ppc/pnv_xscom.h" 53 #include "hw/ppc/pnv_pnor.h" 54 55 #include "hw/isa/isa.h" 56 #include "hw/char/serial.h" 57 #include "hw/rtc/mc146818rtc.h" 58 59 #include <libfdt.h> 60 61 #define FDT_MAX_SIZE (1 * MiB) 62 63 #define FW_FILE_NAME "skiboot.lid" 64 #define FW_LOAD_ADDR 0x0 65 #define FW_MAX_SIZE (16 * MiB) 66 67 #define KERNEL_LOAD_ADDR 0x20000000 68 #define KERNEL_MAX_SIZE (128 * MiB) 69 #define INITRD_LOAD_ADDR 0x28000000 70 #define INITRD_MAX_SIZE (128 * MiB) 71 72 static const char *pnv_chip_core_typename(const PnvChip *o) 73 { 74 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 76 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 77 const char *core_type = object_class_get_name(object_class_by_name(s)); 78 g_free(s); 79 return core_type; 80 } 81 82 /* 83 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 84 * 4 * 4 sockets * 12 cores * 8 threads = 1536 85 * Let's make it 2^11 86 */ 87 #define MAX_CPUS 2048 88 89 /* 90 * Memory nodes are created by hostboot, one for each range of memory 91 * that has a different "affinity". In practice, it means one range 92 * per chip. 93 */ 94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 95 { 96 char *mem_name; 97 uint64_t mem_reg_property[2]; 98 int off; 99 100 mem_reg_property[0] = cpu_to_be64(start); 101 mem_reg_property[1] = cpu_to_be64(size); 102 103 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 104 off = fdt_add_subnode(fdt, 0, mem_name); 105 g_free(mem_name); 106 107 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 108 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 109 sizeof(mem_reg_property)))); 110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 111 } 112 113 static int get_cpus_node(void *fdt) 114 { 115 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 116 117 if (cpus_offset < 0) { 118 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 119 if (cpus_offset) { 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 122 } 123 } 124 _FDT(cpus_offset); 125 return cpus_offset; 126 } 127 128 /* 129 * The PowerNV cores (and threads) need to use real HW ids and not an 130 * incremental index like it has been done on other platforms. This HW 131 * id is stored in the CPU PIR, it is used to create cpu nodes in the 132 * device tree, used in XSCOM to address cores and in interrupt 133 * servers. 134 */ 135 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 136 { 137 PowerPCCPU *cpu = pc->threads[0]; 138 CPUState *cs = CPU(cpu); 139 DeviceClass *dc = DEVICE_GET_CLASS(cs); 140 int smt_threads = CPU_CORE(pc)->nr_threads; 141 CPUPPCState *env = &cpu->env; 142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 143 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 144 uint32_t *servers_prop; 145 int i; 146 uint32_t pir, tir; 147 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 148 0xffffffff, 0xffffffff}; 149 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 150 uint32_t cpufreq = 1000000000; 151 uint32_t page_sizes_prop[64]; 152 size_t page_sizes_prop_size; 153 int offset; 154 char *nodename; 155 int cpus_offset = get_cpus_node(fdt); 156 157 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); 158 159 /* Only one DT node per (big) core */ 160 g_assert(tir == 0); 161 162 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 163 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 164 _FDT(offset); 165 g_free(nodename); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 170 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 171 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 172 173 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 174 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 175 env->dcache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 177 env->dcache_line_size))); 178 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 179 env->icache_line_size))); 180 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 181 env->icache_line_size))); 182 183 if (pcc->l1_dcache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 185 pcc->l1_dcache_size))); 186 } else { 187 warn_report("Unknown L1 dcache size for cpu"); 188 } 189 if (pcc->l1_icache_size) { 190 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 191 pcc->l1_icache_size))); 192 } else { 193 warn_report("Unknown L1 icache size for cpu"); 194 } 195 196 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 198 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 199 cpu->hash64_opts->slb_size))); 200 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 201 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 202 203 if (ppc_has_spr(cpu, SPR_PURR)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 205 } 206 207 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 208 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 209 segs, sizeof(segs)))); 210 } 211 212 /* 213 * Advertise VMX/VSX (vector extensions) if available 214 * 0 / no property == no vector extensions 215 * 1 == VMX / Altivec available 216 * 2 == VSX available 217 */ 218 if (env->insns_flags & PPC_ALTIVEC) { 219 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 220 221 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 222 } 223 224 /* 225 * Advertise DFP (Decimal Floating Point) if available 226 * 0 / no property == no DFP 227 * 1 == DFP available 228 */ 229 if (env->insns_flags2 & PPC2_DFP) { 230 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 231 } 232 233 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 234 sizeof(page_sizes_prop)); 235 if (page_sizes_prop_size) { 236 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 237 page_sizes_prop, page_sizes_prop_size))); 238 } 239 240 /* Build interrupt servers properties */ 241 if (pc->big_core) { 242 servers_prop = g_new(uint32_t, smt_threads * 2); 243 for (i = 0; i < smt_threads; i++) { 244 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 245 servers_prop[i * 2] = cpu_to_be32(pir); 246 247 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); 248 servers_prop[i * 2 + 1] = cpu_to_be32(pir); 249 } 250 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 251 servers_prop, sizeof(*servers_prop) * smt_threads 252 * 2))); 253 } else { 254 servers_prop = g_new(uint32_t, smt_threads); 255 for (i = 0; i < smt_threads; i++) { 256 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 257 servers_prop[i] = cpu_to_be32(pir); 258 } 259 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 260 servers_prop, sizeof(*servers_prop) * smt_threads))); 261 } 262 g_free(servers_prop); 263 264 return offset; 265 } 266 267 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 268 uint32_t nr_threads) 269 { 270 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 271 uint32_t pir; 272 uint64_t addr; 273 char *name; 274 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 275 uint32_t irange[2], i, rsize; 276 uint64_t *reg; 277 int offset; 278 279 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); 280 addr = PNV_ICP_BASE(chip) | (pir << 12); 281 282 irange[0] = cpu_to_be32(pir); 283 irange[1] = cpu_to_be32(nr_threads); 284 285 rsize = sizeof(uint64_t) * 2 * nr_threads; 286 reg = g_malloc(rsize); 287 for (i = 0; i < nr_threads; i++) { 288 /* We know P8 PIR is linear with thread id */ 289 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 290 reg[i * 2 + 1] = cpu_to_be64(0x1000); 291 } 292 293 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 294 offset = fdt_add_subnode(fdt, 0, name); 295 _FDT(offset); 296 g_free(name); 297 298 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 299 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 300 _FDT((fdt_setprop_string(fdt, offset, "device_type", 301 "PowerPC-External-Interrupt-Presentation"))); 302 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 303 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 304 irange, sizeof(irange)))); 305 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 306 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 307 g_free(reg); 308 } 309 310 /* 311 * Adds a PnvPHB to the chip on P8. 312 * Implemented here, like for defaults PHBs 313 */ 314 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 315 { 316 Pnv8Chip *chip8 = PNV8_CHIP(chip); 317 318 phb->chip = chip; 319 320 chip8->phbs[chip8->num_phbs] = phb; 321 chip8->num_phbs++; 322 return chip; 323 } 324 325 /* 326 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 327 * HTM is always enabled because TCG does implement HTM, it's just a 328 * degenerate implementation. 329 */ 330 static const uint8_t pa_features_207[] = { 24, 0, 331 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 332 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 333 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 334 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 335 336 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 337 { 338 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 339 int i; 340 341 pnv_dt_xscom(chip, fdt, 0, 342 cpu_to_be64(PNV_XSCOM_BASE(chip)), 343 cpu_to_be64(PNV_XSCOM_SIZE), 344 compat, sizeof(compat)); 345 346 for (i = 0; i < chip->nr_cores; i++) { 347 PnvCore *pnv_core = chip->cores[i]; 348 int offset; 349 350 offset = pnv_dt_core(chip, pnv_core, fdt); 351 352 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 353 pa_features_207, sizeof(pa_features_207)))); 354 355 /* Interrupt Control Presenters (ICP). One per core. */ 356 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 357 } 358 359 if (chip->ram_size) { 360 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 361 } 362 } 363 364 /* 365 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 366 */ 367 static const uint8_t pa_features_300[] = { 66, 0, 368 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 369 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 370 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 371 /* 6: DS207 */ 372 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 373 /* 16: Vector */ 374 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 375 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 376 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 377 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 378 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 379 /* 32: LE atomic, 34: EBB + ext EBB */ 380 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 381 /* 40: Radix MMU */ 382 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 383 /* 42: PM, 44: PC RA, 46: SC vec'd */ 384 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 385 /* 48: SIMD, 50: QP BFP, 52: String */ 386 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 387 /* 54: DecFP, 56: DecI, 58: SHA */ 388 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 389 /* 60: NM atomic, 62: RNG */ 390 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 391 }; 392 393 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 394 { 395 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 396 int i; 397 398 pnv_dt_xscom(chip, fdt, 0, 399 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 400 cpu_to_be64(PNV9_XSCOM_SIZE), 401 compat, sizeof(compat)); 402 403 for (i = 0; i < chip->nr_cores; i++) { 404 PnvCore *pnv_core = chip->cores[i]; 405 int offset; 406 407 offset = pnv_dt_core(chip, pnv_core, fdt); 408 409 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 410 pa_features_300, sizeof(pa_features_300)))); 411 412 if (pnv_core->big_core) { 413 i++; /* Big-core groups two QEMU cores */ 414 } 415 } 416 417 if (chip->ram_size) { 418 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 419 } 420 421 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 422 } 423 424 /* 425 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 426 * always disables copy/paste. 427 */ 428 static const uint8_t pa_features_31[] = { 74, 0, 429 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 430 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 431 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 432 /* 6: DS207 */ 433 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 434 /* 16: Vector */ 435 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 436 /* 18: Vec. Scalar, 20: Vec. XOR */ 437 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 438 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 439 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 440 /* 32: LE atomic, 34: EBB + ext EBB */ 441 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 442 /* 40: Radix MMU */ 443 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 444 /* 42: PM, 44: PC RA, 46: SC vec'd */ 445 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 446 /* 48: SIMD, 50: QP BFP, 52: String */ 447 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 448 /* 54: DecFP, 56: DecI, 58: SHA */ 449 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 450 /* 60: NM atomic, 62: RNG */ 451 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 452 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 453 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 454 /* 72: [P]HASHST/[P]HASHCHK */ 455 0x80, 0x00, /* 72 - 73 */ 456 }; 457 458 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 459 { 460 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 461 int i; 462 463 pnv_dt_xscom(chip, fdt, 0, 464 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 465 cpu_to_be64(PNV10_XSCOM_SIZE), 466 compat, sizeof(compat)); 467 468 for (i = 0; i < chip->nr_cores; i++) { 469 PnvCore *pnv_core = chip->cores[i]; 470 int offset; 471 472 offset = pnv_dt_core(chip, pnv_core, fdt); 473 474 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 475 pa_features_31, sizeof(pa_features_31)))); 476 477 if (pnv_core->big_core) { 478 i++; /* Big-core groups two QEMU cores */ 479 } 480 } 481 482 if (chip->ram_size) { 483 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 484 } 485 486 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 487 } 488 489 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 490 { 491 uint32_t io_base = d->ioport_id; 492 uint32_t io_regs[] = { 493 cpu_to_be32(1), 494 cpu_to_be32(io_base), 495 cpu_to_be32(2) 496 }; 497 char *name; 498 int node; 499 500 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 501 node = fdt_add_subnode(fdt, lpc_off, name); 502 _FDT(node); 503 g_free(name); 504 505 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 506 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 507 } 508 509 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 510 { 511 const char compatible[] = "ns16550\0pnpPNP,501"; 512 uint32_t io_base = d->ioport_id; 513 uint32_t io_regs[] = { 514 cpu_to_be32(1), 515 cpu_to_be32(io_base), 516 cpu_to_be32(8) 517 }; 518 uint32_t irq; 519 char *name; 520 int node; 521 522 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 523 524 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 525 node = fdt_add_subnode(fdt, lpc_off, name); 526 _FDT(node); 527 g_free(name); 528 529 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 530 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 531 sizeof(compatible)))); 532 533 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 534 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 535 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 536 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 537 fdt_get_phandle(fdt, lpc_off)))); 538 539 /* This is needed by Linux */ 540 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 541 } 542 543 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 544 { 545 const char compatible[] = "bt\0ipmi-bt"; 546 uint32_t io_base; 547 uint32_t io_regs[] = { 548 cpu_to_be32(1), 549 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 550 cpu_to_be32(3) 551 }; 552 uint32_t irq; 553 char *name; 554 int node; 555 556 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 557 io_regs[1] = cpu_to_be32(io_base); 558 559 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 560 561 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 562 node = fdt_add_subnode(fdt, lpc_off, name); 563 _FDT(node); 564 g_free(name); 565 566 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 567 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 568 sizeof(compatible)))); 569 570 /* Mark it as reserved to avoid Linux trying to claim it */ 571 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 572 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 573 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 574 fdt_get_phandle(fdt, lpc_off)))); 575 } 576 577 typedef struct ForeachPopulateArgs { 578 void *fdt; 579 int offset; 580 } ForeachPopulateArgs; 581 582 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 583 { 584 ForeachPopulateArgs *args = opaque; 585 ISADevice *d = ISA_DEVICE(dev); 586 587 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 588 pnv_dt_rtc(d, args->fdt, args->offset); 589 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 590 pnv_dt_serial(d, args->fdt, args->offset); 591 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 592 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 593 } else { 594 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 595 d->ioport_id); 596 } 597 598 return 0; 599 } 600 601 /* 602 * The default LPC bus of a multichip system is on chip 0. It's 603 * recognized by the firmware (skiboot) using a "primary" property. 604 */ 605 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 606 { 607 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 608 ForeachPopulateArgs args = { 609 .fdt = fdt, 610 .offset = isa_offset, 611 }; 612 uint32_t phandle; 613 614 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 615 616 phandle = qemu_fdt_alloc_phandle(fdt); 617 assert(phandle > 0); 618 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 619 620 /* 621 * ISA devices are not necessarily parented to the ISA bus so we 622 * can not use object_child_foreach() 623 */ 624 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 625 &args); 626 } 627 628 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 629 { 630 int off; 631 632 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 633 off = fdt_add_subnode(fdt, off, "power-mgt"); 634 635 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 636 } 637 638 static void *pnv_dt_create(MachineState *machine) 639 { 640 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 641 PnvMachineState *pnv = PNV_MACHINE(machine); 642 void *fdt; 643 char *buf; 644 int off; 645 int i; 646 647 fdt = g_malloc0(FDT_MAX_SIZE); 648 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 649 650 /* /qemu node */ 651 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 652 653 /* Root node */ 654 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 655 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 656 _FDT((fdt_setprop_string(fdt, 0, "model", 657 "IBM PowerNV (emulated by qemu)"))); 658 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 659 660 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 661 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 662 if (qemu_uuid_set) { 663 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 664 } 665 g_free(buf); 666 667 off = fdt_add_subnode(fdt, 0, "chosen"); 668 if (machine->kernel_cmdline) { 669 _FDT((fdt_setprop_string(fdt, off, "bootargs", 670 machine->kernel_cmdline))); 671 } 672 673 if (pnv->initrd_size) { 674 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 675 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 676 677 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 678 &start_prop, sizeof(start_prop)))); 679 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 680 &end_prop, sizeof(end_prop)))); 681 } 682 683 /* Populate device tree for each chip */ 684 for (i = 0; i < pnv->num_chips; i++) { 685 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 686 } 687 688 /* Populate ISA devices on chip 0 */ 689 pnv_dt_isa(pnv, fdt); 690 691 if (pnv->bmc) { 692 pnv_dt_bmc_sensors(pnv->bmc, fdt); 693 } 694 695 /* Create an extra node for power management on machines that support it */ 696 if (pmc->dt_power_mgt) { 697 pmc->dt_power_mgt(pnv, fdt); 698 } 699 700 return fdt; 701 } 702 703 static void pnv_powerdown_notify(Notifier *n, void *opaque) 704 { 705 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 706 707 if (pnv->bmc) { 708 pnv_bmc_powerdown(pnv->bmc); 709 } 710 } 711 712 static void pnv_reset(MachineState *machine, ShutdownCause reason) 713 { 714 PnvMachineState *pnv = PNV_MACHINE(machine); 715 IPMIBmc *bmc; 716 void *fdt; 717 718 qemu_devices_reset(reason); 719 720 /* 721 * The machine should provide by default an internal BMC simulator. 722 * If not, try to use the BMC device that was provided on the command 723 * line. 724 */ 725 bmc = pnv_bmc_find(&error_fatal); 726 if (!pnv->bmc) { 727 if (!bmc) { 728 if (!qtest_enabled()) { 729 warn_report("machine has no BMC device. Use '-device " 730 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 731 "to define one"); 732 } 733 } else { 734 pnv_bmc_set_pnor(bmc, pnv->pnor); 735 pnv->bmc = bmc; 736 } 737 } 738 739 fdt = pnv_dt_create(machine); 740 741 /* Pack resulting tree */ 742 _FDT((fdt_pack(fdt))); 743 744 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 745 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 746 747 /* 748 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 749 * the existing machine->fdt to avoid leaking it during 750 * a reset. 751 */ 752 g_free(machine->fdt); 753 machine->fdt = fdt; 754 } 755 756 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 757 { 758 Pnv8Chip *chip8 = PNV8_CHIP(chip); 759 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 760 761 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 762 763 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 764 } 765 766 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 767 { 768 Pnv8Chip *chip8 = PNV8_CHIP(chip); 769 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 770 771 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 772 773 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 774 } 775 776 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 777 { 778 Pnv9Chip *chip9 = PNV9_CHIP(chip); 779 qemu_irq irq; 780 781 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 782 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 783 784 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 785 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 786 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 787 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 788 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 789 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 790 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 791 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 792 793 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 794 } 795 796 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 797 { 798 Pnv10Chip *chip10 = PNV10_CHIP(chip); 799 qemu_irq irq; 800 801 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 802 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 803 804 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 805 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 806 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 807 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 808 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 809 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 810 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 811 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 812 813 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 814 } 815 816 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 817 { 818 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 819 } 820 821 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 822 { 823 Pnv8Chip *chip8 = PNV8_CHIP(chip); 824 int i; 825 826 ics_pic_print_info(&chip8->psi.ics, buf); 827 828 for (i = 0; i < chip8->num_phbs; i++) { 829 PnvPHB *phb = chip8->phbs[i]; 830 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 831 832 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 833 ics_pic_print_info(&phb3->lsis, buf); 834 } 835 } 836 837 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 838 { 839 GString *buf = opaque; 840 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 841 842 if (!phb) { 843 return 0; 844 } 845 846 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 847 848 return 0; 849 } 850 851 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 852 { 853 Pnv9Chip *chip9 = PNV9_CHIP(chip); 854 855 pnv_xive_pic_print_info(&chip9->xive, buf); 856 pnv_psi_pic_print_info(&chip9->psi, buf); 857 object_child_foreach_recursive(OBJECT(chip), 858 pnv_chip_power9_pic_print_info_child, buf); 859 } 860 861 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 862 uint32_t core_id) 863 { 864 return PNV_XSCOM_EX_BASE(core_id); 865 } 866 867 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 868 uint32_t core_id) 869 { 870 return PNV9_XSCOM_EC_BASE(core_id); 871 } 872 873 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 874 uint32_t core_id) 875 { 876 return PNV10_XSCOM_EC_BASE(core_id); 877 } 878 879 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 880 { 881 PowerPCCPUClass *ppc_default = 882 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 883 PowerPCCPUClass *ppc = 884 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 885 886 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 887 } 888 889 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 890 { 891 ISADevice *dev = isa_new("isa-ipmi-bt"); 892 893 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 894 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 895 isa_realize_and_unref(dev, bus, &error_fatal); 896 } 897 898 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 899 { 900 Pnv10Chip *chip10 = PNV10_CHIP(chip); 901 902 pnv_xive2_pic_print_info(&chip10->xive, buf); 903 pnv_psi_pic_print_info(&chip10->psi, buf); 904 object_child_foreach_recursive(OBJECT(chip), 905 pnv_chip_power9_pic_print_info_child, buf); 906 } 907 908 /* Always give the first 1GB to chip 0 else we won't boot */ 909 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 910 { 911 MachineState *machine = MACHINE(pnv); 912 uint64_t ram_per_chip; 913 914 assert(machine->ram_size >= 1 * GiB); 915 916 ram_per_chip = machine->ram_size / pnv->num_chips; 917 if (ram_per_chip >= 1 * GiB) { 918 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 919 } 920 921 assert(pnv->num_chips > 1); 922 923 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 924 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 925 } 926 927 static void pnv_init(MachineState *machine) 928 { 929 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 930 PnvMachineState *pnv = PNV_MACHINE(machine); 931 MachineClass *mc = MACHINE_GET_CLASS(machine); 932 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 933 int max_smt_threads = pmc->max_smt_threads; 934 char *fw_filename; 935 long fw_size; 936 uint64_t chip_ram_start = 0; 937 int i; 938 char *chip_typename; 939 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 940 DeviceState *dev; 941 942 if (kvm_enabled()) { 943 error_report("machine %s does not support the KVM accelerator", 944 mc->name); 945 exit(EXIT_FAILURE); 946 } 947 948 /* allocate RAM */ 949 if (machine->ram_size < mc->default_ram_size) { 950 char *sz = size_to_str(mc->default_ram_size); 951 error_report("Invalid RAM size, should be bigger than %s", sz); 952 g_free(sz); 953 exit(EXIT_FAILURE); 954 } 955 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 956 957 /* 958 * Create our simple PNOR device 959 */ 960 dev = qdev_new(TYPE_PNV_PNOR); 961 if (pnor) { 962 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 963 } 964 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 965 pnv->pnor = PNV_PNOR(dev); 966 967 /* load skiboot firmware */ 968 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 969 if (!fw_filename) { 970 error_report("Could not find OPAL firmware '%s'", bios_name); 971 exit(1); 972 } 973 974 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 975 if (fw_size < 0) { 976 error_report("Could not load OPAL firmware '%s'", fw_filename); 977 exit(1); 978 } 979 g_free(fw_filename); 980 981 /* load kernel */ 982 if (machine->kernel_filename) { 983 long kernel_size; 984 985 kernel_size = load_image_targphys(machine->kernel_filename, 986 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 987 if (kernel_size < 0) { 988 error_report("Could not load kernel '%s'", 989 machine->kernel_filename); 990 exit(1); 991 } 992 } 993 994 /* load initrd */ 995 if (machine->initrd_filename) { 996 pnv->initrd_base = INITRD_LOAD_ADDR; 997 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 998 pnv->initrd_base, INITRD_MAX_SIZE); 999 if (pnv->initrd_size < 0) { 1000 error_report("Could not load initial ram disk '%s'", 1001 machine->initrd_filename); 1002 exit(1); 1003 } 1004 } 1005 1006 /* MSIs are supported on this platform */ 1007 msi_nonbroken = true; 1008 1009 /* 1010 * Check compatibility of the specified CPU with the machine 1011 * default. 1012 */ 1013 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 1014 error_report("invalid CPU model '%s' for %s machine", 1015 machine->cpu_type, mc->name); 1016 exit(1); 1017 } 1018 1019 /* Create the processor chips */ 1020 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 1021 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 1022 i, machine->cpu_type); 1023 if (!object_class_by_name(chip_typename)) { 1024 error_report("invalid chip model '%.*s' for %s machine", 1025 i, machine->cpu_type, mc->name); 1026 exit(1); 1027 } 1028 1029 pnv->num_chips = 1030 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 1031 1032 if (pnv->big_core) { 1033 if (machine->smp.threads % 2 == 1) { 1034 error_report("Cannot support %d threads with big-core option " 1035 "because it must be an even number", 1036 machine->smp.threads); 1037 exit(1); 1038 } 1039 max_smt_threads *= 2; 1040 } 1041 1042 if (machine->smp.threads > max_smt_threads) { 1043 error_report("Cannot support more than %d threads/core " 1044 "on %s machine", max_smt_threads, mc->desc); 1045 if (pmc->max_smt_threads == 4) { 1046 error_report("(use big-core=on for 8 threads per core)"); 1047 } 1048 exit(1); 1049 } 1050 1051 if (pnv->big_core) { 1052 /* 1053 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore 1054 * per core, so adjust topology here. pnv_dt_core() processor 1055 * device-tree and TCG SMT code make the 2 cores appear as one big core 1056 * from software point of view. pnv pervasive models and xscoms tend to 1057 * see the big core as 2 small core halves. 1058 */ 1059 machine->smp.cores *= 2; 1060 machine->smp.threads /= 2; 1061 } 1062 1063 if (!is_power_of_2(machine->smp.threads)) { 1064 error_report("Cannot support %d threads/core on a powernv " 1065 "machine because it must be a power of 2", 1066 machine->smp.threads); 1067 exit(1); 1068 } 1069 1070 /* 1071 * TODO: should we decide on how many chips we can create based 1072 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1073 */ 1074 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1075 error_report("invalid number of chips: '%d'", pnv->num_chips); 1076 error_printf( 1077 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1078 exit(1); 1079 } 1080 1081 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1082 for (i = 0; i < pnv->num_chips; i++) { 1083 char chip_name[32]; 1084 Object *chip = OBJECT(qdev_new(chip_typename)); 1085 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1086 1087 pnv->chips[i] = PNV_CHIP(chip); 1088 1089 /* Distribute RAM among the chips */ 1090 object_property_set_int(chip, "ram-start", chip_ram_start, 1091 &error_fatal); 1092 object_property_set_int(chip, "ram-size", chip_ram_size, 1093 &error_fatal); 1094 chip_ram_start += chip_ram_size; 1095 1096 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1097 object_property_add_child(OBJECT(pnv), chip_name, chip); 1098 object_property_set_int(chip, "chip-id", i, &error_fatal); 1099 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1100 &error_fatal); 1101 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1102 &error_fatal); 1103 object_property_set_bool(chip, "big-core", pnv->big_core, 1104 &error_fatal); 1105 /* 1106 * The POWER8 machine use the XICS interrupt interface. 1107 * Propagate the XICS fabric to the chip and its controllers. 1108 */ 1109 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1110 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1111 } 1112 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1113 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1114 &error_abort); 1115 } 1116 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1117 } 1118 g_free(chip_typename); 1119 1120 /* Instantiate ISA bus on chip 0 */ 1121 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1122 1123 /* Create serial port */ 1124 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1125 1126 /* Create an RTC ISA device too */ 1127 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1128 1129 /* 1130 * Create the machine BMC simulator and the IPMI BT device for 1131 * communication with the BMC 1132 */ 1133 if (defaults_enabled()) { 1134 pnv->bmc = pnv_bmc_create(pnv->pnor); 1135 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1136 } 1137 1138 /* 1139 * The PNOR is mapped on the LPC FW address space by the BMC. 1140 * Since we can not reach the remote BMC machine with LPC memops, 1141 * map it always for now. 1142 */ 1143 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1144 &pnv->pnor->mmio); 1145 1146 /* 1147 * OpenPOWER systems use a IPMI SEL Event message to notify the 1148 * host to powerdown 1149 */ 1150 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1151 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1152 1153 /* 1154 * Create/Connect any machine-specific I2C devices 1155 */ 1156 if (pmc->i2c_init) { 1157 pmc->i2c_init(pnv); 1158 } 1159 } 1160 1161 /* 1162 * 0:21 Reserved - Read as zeros 1163 * 22:24 Chip ID 1164 * 25:28 Core number 1165 * 29:31 Thread ID 1166 */ 1167 static void pnv_get_pir_tir_p8(PnvChip *chip, 1168 uint32_t core_id, uint32_t thread_id, 1169 uint32_t *pir, uint32_t *tir) 1170 { 1171 if (pir) { 1172 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; 1173 } 1174 if (tir) { 1175 *tir = thread_id; 1176 } 1177 } 1178 1179 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1180 Error **errp) 1181 { 1182 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1183 Error *local_err = NULL; 1184 Object *obj; 1185 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1186 1187 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1188 if (local_err) { 1189 error_propagate(errp, local_err); 1190 return; 1191 } 1192 1193 pnv_cpu->intc = obj; 1194 } 1195 1196 1197 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1198 { 1199 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1200 1201 icp_reset(ICP(pnv_cpu->intc)); 1202 } 1203 1204 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1205 { 1206 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1207 1208 icp_destroy(ICP(pnv_cpu->intc)); 1209 pnv_cpu->intc = NULL; 1210 } 1211 1212 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1213 GString *buf) 1214 { 1215 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1216 } 1217 1218 /* 1219 * 0:48 Reserved - Read as zeroes 1220 * 49:52 Node ID 1221 * 53:55 Chip ID 1222 * 56 Reserved - Read as zero 1223 * 57:61 Core number 1224 * 62:63 Thread ID 1225 * 1226 * We only care about the lower bits. uint32_t is fine for the moment. 1227 */ 1228 static void pnv_get_pir_tir_p9(PnvChip *chip, 1229 uint32_t core_id, uint32_t thread_id, 1230 uint32_t *pir, uint32_t *tir) 1231 { 1232 if (chip->big_core) { 1233 /* Big-core interleaves thread ID between small-cores */ 1234 thread_id <<= 1; 1235 thread_id |= core_id & 1; 1236 core_id >>= 1; 1237 1238 if (pir) { 1239 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1240 } 1241 } else { 1242 if (pir) { 1243 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1244 } 1245 } 1246 if (tir) { 1247 *tir = thread_id; 1248 } 1249 } 1250 1251 /* 1252 * 0:48 Reserved - Read as zeroes 1253 * 49:52 Node ID 1254 * 53:55 Chip ID 1255 * 56 Reserved - Read as zero 1256 * 57:59 Quad ID 1257 * 60 Core Chiplet Pair ID 1258 * 61:63 Thread/Core Chiplet ID t0-t2 1259 * 1260 * We only care about the lower bits. uint32_t is fine for the moment. 1261 */ 1262 static void pnv_get_pir_tir_p10(PnvChip *chip, 1263 uint32_t core_id, uint32_t thread_id, 1264 uint32_t *pir, uint32_t *tir) 1265 { 1266 if (chip->big_core) { 1267 /* Big-core interleaves thread ID between small-cores */ 1268 thread_id <<= 1; 1269 thread_id |= core_id & 1; 1270 core_id >>= 1; 1271 1272 if (pir) { 1273 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1274 } 1275 } else { 1276 if (pir) { 1277 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1278 } 1279 } 1280 if (tir) { 1281 *tir = thread_id; 1282 } 1283 } 1284 1285 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1286 Error **errp) 1287 { 1288 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1289 Error *local_err = NULL; 1290 Object *obj; 1291 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1292 1293 /* 1294 * The core creates its interrupt presenter but the XIVE interrupt 1295 * controller object is initialized afterwards. Hopefully, it's 1296 * only used at runtime. 1297 */ 1298 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1299 &local_err); 1300 if (local_err) { 1301 error_propagate(errp, local_err); 1302 return; 1303 } 1304 1305 pnv_cpu->intc = obj; 1306 } 1307 1308 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1309 { 1310 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1311 1312 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1313 } 1314 1315 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1316 { 1317 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1318 1319 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1320 pnv_cpu->intc = NULL; 1321 } 1322 1323 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1324 GString *buf) 1325 { 1326 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1327 } 1328 1329 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1330 Error **errp) 1331 { 1332 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1333 Error *local_err = NULL; 1334 Object *obj; 1335 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1336 1337 /* 1338 * The core creates its interrupt presenter but the XIVE2 interrupt 1339 * controller object is initialized afterwards. Hopefully, it's 1340 * only used at runtime. 1341 */ 1342 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1343 &local_err); 1344 if (local_err) { 1345 error_propagate(errp, local_err); 1346 return; 1347 } 1348 1349 pnv_cpu->intc = obj; 1350 } 1351 1352 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1353 { 1354 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1355 1356 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1357 } 1358 1359 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1360 { 1361 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1362 1363 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1364 pnv_cpu->intc = NULL; 1365 } 1366 1367 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1368 GString *buf) 1369 { 1370 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1371 } 1372 1373 /* 1374 * Allowed core identifiers on a POWER8 Processor Chip : 1375 * 1376 * <EX0 reserved> 1377 * EX1 - Venice only 1378 * EX2 - Venice only 1379 * EX3 - Venice only 1380 * EX4 1381 * EX5 1382 * EX6 1383 * <EX7,8 reserved> <reserved> 1384 * EX9 - Venice only 1385 * EX10 - Venice only 1386 * EX11 - Venice only 1387 * EX12 1388 * EX13 1389 * EX14 1390 * <EX15 reserved> 1391 */ 1392 #define POWER8E_CORE_MASK (0x7070ull) 1393 #define POWER8_CORE_MASK (0x7e7eull) 1394 1395 /* 1396 * POWER9 has 24 cores, ids starting at 0x0 1397 */ 1398 #define POWER9_CORE_MASK (0xffffffffffffffull) 1399 1400 1401 #define POWER10_CORE_MASK (0xffffffffffffffull) 1402 1403 static void pnv_chip_power8_instance_init(Object *obj) 1404 { 1405 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1406 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1407 int i; 1408 1409 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1410 (Object **)&chip8->xics, 1411 object_property_allow_set_link, 1412 OBJ_PROP_LINK_STRONG); 1413 1414 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1415 1416 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1417 1418 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1419 1420 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1421 1422 if (defaults_enabled()) { 1423 chip8->num_phbs = pcc->num_phbs; 1424 1425 for (i = 0; i < chip8->num_phbs; i++) { 1426 Object *phb = object_new(TYPE_PNV_PHB); 1427 1428 /* 1429 * We need the chip to parent the PHB to allow the DT 1430 * to build correctly (via pnv_xscom_dt()). 1431 * 1432 * TODO: the PHB should be parented by a PEC device that, at 1433 * this moment, is not modelled powernv8/phb3. 1434 */ 1435 object_property_add_child(obj, "phb[*]", phb); 1436 chip8->phbs[i] = PNV_PHB(phb); 1437 } 1438 } 1439 1440 } 1441 1442 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1443 { 1444 PnvChip *chip = PNV_CHIP(chip8); 1445 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1446 int i, j; 1447 char *name; 1448 1449 name = g_strdup_printf("icp-%x", chip->chip_id); 1450 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1451 g_free(name); 1452 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1453 &chip8->icp_mmio); 1454 1455 /* Map the ICP registers for each thread */ 1456 for (i = 0; i < chip->nr_cores; i++) { 1457 PnvCore *pnv_core = chip->cores[i]; 1458 int core_hwid = CPU_CORE(pnv_core)->core_id; 1459 1460 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1461 uint32_t pir; 1462 PnvICPState *icp; 1463 1464 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); 1465 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1466 1467 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1468 &icp->mmio); 1469 } 1470 } 1471 } 1472 1473 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1474 { 1475 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1476 PnvChip *chip = PNV_CHIP(dev); 1477 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1478 Pnv8Psi *psi8 = &chip8->psi; 1479 Error *local_err = NULL; 1480 int i; 1481 1482 assert(chip8->xics); 1483 1484 /* XSCOM bridge is first */ 1485 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1486 1487 pcc->parent_realize(dev, &local_err); 1488 if (local_err) { 1489 error_propagate(errp, local_err); 1490 return; 1491 } 1492 1493 /* Processor Service Interface (PSI) Host Bridge */ 1494 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1495 &error_fatal); 1496 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1497 OBJECT(chip8->xics), &error_abort); 1498 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1499 return; 1500 } 1501 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1502 &PNV_PSI(psi8)->xscom_regs); 1503 1504 /* Create LPC controller */ 1505 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1506 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1507 1508 chip->fw_mr = &chip8->lpc.isa_fw; 1509 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1510 (uint64_t) PNV_XSCOM_BASE(chip), 1511 PNV_XSCOM_LPC_BASE); 1512 1513 /* 1514 * Interrupt Management Area. This is the memory region holding 1515 * all the Interrupt Control Presenter (ICP) registers 1516 */ 1517 pnv_chip_icp_realize(chip8, &local_err); 1518 if (local_err) { 1519 error_propagate(errp, local_err); 1520 return; 1521 } 1522 1523 /* Create the simplified OCC model */ 1524 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1525 return; 1526 } 1527 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1528 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1529 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1530 1531 /* OCC SRAM model */ 1532 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1533 &chip8->occ.sram_regs); 1534 1535 /* HOMER */ 1536 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1537 &error_abort); 1538 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1539 return; 1540 } 1541 /* Homer Xscom region */ 1542 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1543 1544 /* Homer mmio region */ 1545 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1546 &chip8->homer.regs); 1547 1548 /* PHB controllers */ 1549 for (i = 0; i < chip8->num_phbs; i++) { 1550 PnvPHB *phb = chip8->phbs[i]; 1551 1552 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1553 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1554 &error_fatal); 1555 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1556 &error_fatal); 1557 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1558 return; 1559 } 1560 } 1561 } 1562 1563 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1564 { 1565 addr &= (PNV_XSCOM_SIZE - 1); 1566 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1567 } 1568 1569 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1570 { 1571 DeviceClass *dc = DEVICE_CLASS(klass); 1572 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1573 1574 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1575 k->cores_mask = POWER8E_CORE_MASK; 1576 k->num_phbs = 3; 1577 k->get_pir_tir = pnv_get_pir_tir_p8; 1578 k->intc_create = pnv_chip_power8_intc_create; 1579 k->intc_reset = pnv_chip_power8_intc_reset; 1580 k->intc_destroy = pnv_chip_power8_intc_destroy; 1581 k->intc_print_info = pnv_chip_power8_intc_print_info; 1582 k->isa_create = pnv_chip_power8_isa_create; 1583 k->dt_populate = pnv_chip_power8_dt_populate; 1584 k->pic_print_info = pnv_chip_power8_pic_print_info; 1585 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1586 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1587 dc->desc = "PowerNV Chip POWER8E"; 1588 1589 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1590 &k->parent_realize); 1591 } 1592 1593 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1594 { 1595 DeviceClass *dc = DEVICE_CLASS(klass); 1596 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1597 1598 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1599 k->cores_mask = POWER8_CORE_MASK; 1600 k->num_phbs = 3; 1601 k->get_pir_tir = pnv_get_pir_tir_p8; 1602 k->intc_create = pnv_chip_power8_intc_create; 1603 k->intc_reset = pnv_chip_power8_intc_reset; 1604 k->intc_destroy = pnv_chip_power8_intc_destroy; 1605 k->intc_print_info = pnv_chip_power8_intc_print_info; 1606 k->isa_create = pnv_chip_power8_isa_create; 1607 k->dt_populate = pnv_chip_power8_dt_populate; 1608 k->pic_print_info = pnv_chip_power8_pic_print_info; 1609 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1610 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1611 dc->desc = "PowerNV Chip POWER8"; 1612 1613 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1614 &k->parent_realize); 1615 } 1616 1617 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1618 { 1619 DeviceClass *dc = DEVICE_CLASS(klass); 1620 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1621 1622 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1623 k->cores_mask = POWER8_CORE_MASK; 1624 k->num_phbs = 4; 1625 k->get_pir_tir = pnv_get_pir_tir_p8; 1626 k->intc_create = pnv_chip_power8_intc_create; 1627 k->intc_reset = pnv_chip_power8_intc_reset; 1628 k->intc_destroy = pnv_chip_power8_intc_destroy; 1629 k->intc_print_info = pnv_chip_power8_intc_print_info; 1630 k->isa_create = pnv_chip_power8nvl_isa_create; 1631 k->dt_populate = pnv_chip_power8_dt_populate; 1632 k->pic_print_info = pnv_chip_power8_pic_print_info; 1633 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1634 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1635 dc->desc = "PowerNV Chip POWER8NVL"; 1636 1637 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1638 &k->parent_realize); 1639 } 1640 1641 static void pnv_chip_power9_instance_init(Object *obj) 1642 { 1643 PnvChip *chip = PNV_CHIP(obj); 1644 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1645 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1646 int i; 1647 1648 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1649 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1650 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1651 "xive-fabric"); 1652 1653 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1654 1655 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1656 1657 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1658 1659 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1660 1661 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1662 1663 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1664 1665 /* Number of PECs is the chip default */ 1666 chip->num_pecs = pcc->num_pecs; 1667 1668 for (i = 0; i < chip->num_pecs; i++) { 1669 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1670 TYPE_PNV_PHB4_PEC); 1671 } 1672 1673 for (i = 0; i < pcc->i2c_num_engines; i++) { 1674 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1675 } 1676 } 1677 1678 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1679 PnvCore *pnv_core, 1680 const char *type) 1681 { 1682 char eq_name[32]; 1683 int core_id = CPU_CORE(pnv_core)->core_id; 1684 1685 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1686 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1687 sizeof(*eq), type, 1688 &error_fatal, NULL); 1689 1690 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1691 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1692 } 1693 1694 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1695 { 1696 PnvChip *chip = PNV_CHIP(chip9); 1697 int i; 1698 1699 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1700 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1701 1702 for (i = 0; i < chip9->nr_quads; i++) { 1703 PnvQuad *eq = &chip9->quads[i]; 1704 1705 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1706 PNV_QUAD_TYPE_NAME("power9")); 1707 1708 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1709 &eq->xscom_regs); 1710 } 1711 } 1712 1713 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1714 { 1715 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1716 int i; 1717 1718 for (i = 0; i < chip->num_pecs; i++) { 1719 PnvPhb4PecState *pec = &chip9->pecs[i]; 1720 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1721 uint32_t pec_nest_base; 1722 uint32_t pec_pci_base; 1723 1724 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1725 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1726 &error_fatal); 1727 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1728 &error_fatal); 1729 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1730 return; 1731 } 1732 1733 pec_nest_base = pecc->xscom_nest_base(pec); 1734 pec_pci_base = pecc->xscom_pci_base(pec); 1735 1736 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1737 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1738 } 1739 } 1740 1741 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1742 { 1743 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1744 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1745 PnvChip *chip = PNV_CHIP(dev); 1746 Pnv9Psi *psi9 = &chip9->psi; 1747 Error *local_err = NULL; 1748 int i; 1749 1750 /* XSCOM bridge is first */ 1751 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1752 1753 pcc->parent_realize(dev, &local_err); 1754 if (local_err) { 1755 error_propagate(errp, local_err); 1756 return; 1757 } 1758 1759 /* ADU */ 1760 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), 1761 &error_abort); 1762 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1763 return; 1764 } 1765 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 1766 &chip9->adu.xscom_regs); 1767 1768 pnv_chip_quad_realize(chip9, &local_err); 1769 if (local_err) { 1770 error_propagate(errp, local_err); 1771 return; 1772 } 1773 1774 /* XIVE interrupt controller (POWER9) */ 1775 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1776 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1777 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1778 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1779 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1780 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1781 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1782 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1783 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1784 &error_abort); 1785 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1786 return; 1787 } 1788 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1789 &chip9->xive.xscom_regs); 1790 1791 /* Processor Service Interface (PSI) Host Bridge */ 1792 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1793 &error_fatal); 1794 /* This is the only device with 4k ESB pages */ 1795 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1796 &error_fatal); 1797 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1798 return; 1799 } 1800 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1801 &PNV_PSI(psi9)->xscom_regs); 1802 1803 /* LPC */ 1804 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1805 return; 1806 } 1807 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1808 &chip9->lpc.xscom_regs); 1809 1810 chip->fw_mr = &chip9->lpc.isa_fw; 1811 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1812 (uint64_t) PNV9_LPCM_BASE(chip)); 1813 1814 /* ChipTOD */ 1815 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1816 chip->chip_id == 0, &error_abort); 1817 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1818 chip->chip_id == 1, &error_abort); 1819 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1820 &error_abort); 1821 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1822 return; 1823 } 1824 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1825 &chip9->chiptod.xscom_regs); 1826 1827 /* Create the simplified OCC model */ 1828 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1829 return; 1830 } 1831 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1832 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1833 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1834 1835 /* OCC SRAM model */ 1836 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1837 &chip9->occ.sram_regs); 1838 1839 /* SBE */ 1840 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1841 return; 1842 } 1843 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1844 &chip9->sbe.xscom_ctrl_regs); 1845 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1846 &chip9->sbe.xscom_mbox_regs); 1847 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1848 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1849 1850 /* HOMER */ 1851 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1852 &error_abort); 1853 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1854 return; 1855 } 1856 /* Homer Xscom region */ 1857 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1858 1859 /* Homer mmio region */ 1860 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1861 &chip9->homer.regs); 1862 1863 /* PEC PHBs */ 1864 pnv_chip_power9_pec_realize(chip, &local_err); 1865 if (local_err) { 1866 error_propagate(errp, local_err); 1867 return; 1868 } 1869 1870 /* 1871 * I2C 1872 */ 1873 for (i = 0; i < pcc->i2c_num_engines; i++) { 1874 Object *obj = OBJECT(&chip9->i2c[i]); 1875 1876 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1877 object_property_set_int(obj, "num-busses", 1878 pcc->i2c_ports_per_engine[i], 1879 &error_fatal); 1880 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1881 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1882 return; 1883 } 1884 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1885 (chip9->i2c[i].engine - 1) * 1886 PNV9_XSCOM_I2CM_SIZE, 1887 &chip9->i2c[i].xscom_regs); 1888 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1889 qdev_get_gpio_in(DEVICE(psi9), 1890 PSIHB9_IRQ_SBE_I2C)); 1891 } 1892 } 1893 1894 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1895 { 1896 addr &= (PNV9_XSCOM_SIZE - 1); 1897 return addr >> 3; 1898 } 1899 1900 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1901 { 1902 DeviceClass *dc = DEVICE_CLASS(klass); 1903 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1904 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1905 1906 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1907 k->cores_mask = POWER9_CORE_MASK; 1908 k->get_pir_tir = pnv_get_pir_tir_p9; 1909 k->intc_create = pnv_chip_power9_intc_create; 1910 k->intc_reset = pnv_chip_power9_intc_reset; 1911 k->intc_destroy = pnv_chip_power9_intc_destroy; 1912 k->intc_print_info = pnv_chip_power9_intc_print_info; 1913 k->isa_create = pnv_chip_power9_isa_create; 1914 k->dt_populate = pnv_chip_power9_dt_populate; 1915 k->pic_print_info = pnv_chip_power9_pic_print_info; 1916 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1917 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1918 dc->desc = "PowerNV Chip POWER9"; 1919 k->num_pecs = PNV9_CHIP_MAX_PEC; 1920 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1921 k->i2c_ports_per_engine = i2c_ports_per_engine; 1922 1923 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1924 &k->parent_realize); 1925 } 1926 1927 static void pnv_chip_power10_instance_init(Object *obj) 1928 { 1929 PnvChip *chip = PNV_CHIP(obj); 1930 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1931 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1932 int i; 1933 1934 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 1935 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1936 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1937 "xive-fabric"); 1938 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1939 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1940 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1941 TYPE_PNV10_CHIPTOD); 1942 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1943 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1944 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1945 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1946 TYPE_PNV_N1_CHIPLET); 1947 1948 chip->num_pecs = pcc->num_pecs; 1949 1950 for (i = 0; i < chip->num_pecs; i++) { 1951 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1952 TYPE_PNV_PHB5_PEC); 1953 } 1954 1955 for (i = 0; i < pcc->i2c_num_engines; i++) { 1956 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1957 } 1958 } 1959 1960 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1961 { 1962 PnvChip *chip = PNV_CHIP(chip10); 1963 int i; 1964 1965 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1966 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1967 1968 for (i = 0; i < chip10->nr_quads; i++) { 1969 PnvQuad *eq = &chip10->quads[i]; 1970 1971 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1972 PNV_QUAD_TYPE_NAME("power10")); 1973 1974 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1975 &eq->xscom_regs); 1976 1977 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1978 &eq->xscom_qme_regs); 1979 } 1980 } 1981 1982 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1983 { 1984 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1985 int i; 1986 1987 for (i = 0; i < chip->num_pecs; i++) { 1988 PnvPhb4PecState *pec = &chip10->pecs[i]; 1989 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1990 uint32_t pec_nest_base; 1991 uint32_t pec_pci_base; 1992 1993 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1994 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1995 &error_fatal); 1996 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1997 &error_fatal); 1998 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1999 return; 2000 } 2001 2002 pec_nest_base = pecc->xscom_nest_base(pec); 2003 pec_pci_base = pecc->xscom_pci_base(pec); 2004 2005 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 2006 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 2007 } 2008 } 2009 2010 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 2011 { 2012 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 2013 PnvChip *chip = PNV_CHIP(dev); 2014 Pnv10Chip *chip10 = PNV10_CHIP(dev); 2015 Error *local_err = NULL; 2016 int i; 2017 2018 /* XSCOM bridge is first */ 2019 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 2020 2021 pcc->parent_realize(dev, &local_err); 2022 if (local_err) { 2023 error_propagate(errp, local_err); 2024 return; 2025 } 2026 2027 /* ADU */ 2028 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), 2029 &error_abort); 2030 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 2031 return; 2032 } 2033 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 2034 &chip10->adu.xscom_regs); 2035 2036 pnv_chip_power10_quad_realize(chip10, &local_err); 2037 if (local_err) { 2038 error_propagate(errp, local_err); 2039 return; 2040 } 2041 2042 /* XIVE2 interrupt controller (POWER10) */ 2043 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 2044 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 2045 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 2046 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 2047 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 2048 PNV10_XIVE2_END_BASE(chip), &error_fatal); 2049 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 2050 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 2051 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 2052 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 2053 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 2054 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 2055 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 2056 &error_abort); 2057 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 2058 return; 2059 } 2060 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 2061 &chip10->xive.xscom_regs); 2062 2063 /* Processor Service Interface (PSI) Host Bridge */ 2064 object_property_set_int(OBJECT(&chip10->psi), "bar", 2065 PNV10_PSIHB_BASE(chip), &error_fatal); 2066 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 2067 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 2068 &error_fatal); 2069 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 2070 return; 2071 } 2072 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 2073 &PNV_PSI(&chip10->psi)->xscom_regs); 2074 2075 /* LPC */ 2076 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 2077 return; 2078 } 2079 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 2080 &chip10->lpc.xscom_regs); 2081 2082 chip->fw_mr = &chip10->lpc.isa_fw; 2083 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2084 (uint64_t) PNV10_LPCM_BASE(chip)); 2085 2086 /* ChipTOD */ 2087 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 2088 chip->chip_id == 0, &error_abort); 2089 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 2090 chip->chip_id == 1, &error_abort); 2091 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 2092 &error_abort); 2093 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 2094 return; 2095 } 2096 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 2097 &chip10->chiptod.xscom_regs); 2098 2099 /* Create the simplified OCC model */ 2100 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2101 return; 2102 } 2103 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2104 &chip10->occ.xscom_regs); 2105 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2106 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2107 2108 /* OCC SRAM model */ 2109 memory_region_add_subregion(get_system_memory(), 2110 PNV10_OCC_SENSOR_BASE(chip), 2111 &chip10->occ.sram_regs); 2112 2113 /* SBE */ 2114 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2115 return; 2116 } 2117 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2118 &chip10->sbe.xscom_ctrl_regs); 2119 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2120 &chip10->sbe.xscom_mbox_regs); 2121 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2122 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2123 2124 /* HOMER */ 2125 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2126 &error_abort); 2127 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2128 return; 2129 } 2130 /* Homer Xscom region */ 2131 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2132 &chip10->homer.pba_regs); 2133 2134 /* Homer mmio region */ 2135 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2136 &chip10->homer.regs); 2137 2138 /* N1 chiplet */ 2139 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2140 return; 2141 } 2142 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2143 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2144 2145 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2146 &chip10->n1_chiplet.xscom_pb_eq_mr); 2147 2148 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2149 &chip10->n1_chiplet.xscom_pb_es_mr); 2150 2151 /* PHBs */ 2152 pnv_chip_power10_phb_realize(chip, &local_err); 2153 if (local_err) { 2154 error_propagate(errp, local_err); 2155 return; 2156 } 2157 2158 2159 /* 2160 * I2C 2161 */ 2162 for (i = 0; i < pcc->i2c_num_engines; i++) { 2163 Object *obj = OBJECT(&chip10->i2c[i]); 2164 2165 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2166 object_property_set_int(obj, "num-busses", 2167 pcc->i2c_ports_per_engine[i], 2168 &error_fatal); 2169 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2170 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2171 return; 2172 } 2173 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2174 (chip10->i2c[i].engine - 1) * 2175 PNV10_XSCOM_I2CM_SIZE, 2176 &chip10->i2c[i].xscom_regs); 2177 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2178 qdev_get_gpio_in(DEVICE(&chip10->psi), 2179 PSIHB9_IRQ_SBE_I2C)); 2180 } 2181 2182 } 2183 2184 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2185 { 2186 int i; 2187 for (i = 0; i < pnv->num_chips; i++) { 2188 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2189 2190 /* 2191 * Add a PCA9552 I2C device for PCIe hotplug control 2192 * to engine 2, bus 1, address 0x63 2193 */ 2194 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2195 "pca9552", 0x63); 2196 2197 /* 2198 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2199 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2200 * after hypervisor code sets a SLOTx_EN pin high. 2201 */ 2202 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2203 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2204 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2205 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2206 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2207 2208 /* 2209 * Add a PCA9554 I2C device for cable card presence detection 2210 * to engine 2, bus 1, address 0x25 2211 */ 2212 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2213 } 2214 } 2215 2216 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2217 { 2218 addr &= (PNV10_XSCOM_SIZE - 1); 2219 return addr >> 3; 2220 } 2221 2222 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2223 { 2224 DeviceClass *dc = DEVICE_CLASS(klass); 2225 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2226 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2227 2228 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2229 k->cores_mask = POWER10_CORE_MASK; 2230 k->get_pir_tir = pnv_get_pir_tir_p10; 2231 k->intc_create = pnv_chip_power10_intc_create; 2232 k->intc_reset = pnv_chip_power10_intc_reset; 2233 k->intc_destroy = pnv_chip_power10_intc_destroy; 2234 k->intc_print_info = pnv_chip_power10_intc_print_info; 2235 k->isa_create = pnv_chip_power10_isa_create; 2236 k->dt_populate = pnv_chip_power10_dt_populate; 2237 k->pic_print_info = pnv_chip_power10_pic_print_info; 2238 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2239 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2240 dc->desc = "PowerNV Chip POWER10"; 2241 k->num_pecs = PNV10_CHIP_MAX_PEC; 2242 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2243 k->i2c_ports_per_engine = i2c_ports_per_engine; 2244 2245 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2246 &k->parent_realize); 2247 } 2248 2249 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, 2250 Error **errp) 2251 { 2252 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2253 int cores_max; 2254 2255 /* 2256 * No custom mask for this chip, let's use the default one from * 2257 * the chip class 2258 */ 2259 if (!chip->cores_mask) { 2260 chip->cores_mask = pcc->cores_mask; 2261 } 2262 2263 /* filter alien core ids ! some are reserved */ 2264 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2265 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2266 chip->cores_mask); 2267 return; 2268 } 2269 chip->cores_mask &= pcc->cores_mask; 2270 2271 /* Ensure small-cores a paired up in big-core mode */ 2272 if (pnv->big_core) { 2273 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; 2274 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; 2275 2276 if (even_cores ^ (odd_cores >> 1)) { 2277 error_setg(errp, "warning: unpaired cores in big-core mode !"); 2278 return; 2279 } 2280 } 2281 2282 /* now that we have a sane layout, let check the number of cores */ 2283 cores_max = ctpop64(chip->cores_mask); 2284 if (chip->nr_cores > cores_max) { 2285 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2286 cores_max); 2287 return; 2288 } 2289 } 2290 2291 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2292 { 2293 Error *error = NULL; 2294 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2295 const char *typename = pnv_chip_core_typename(chip); 2296 int i, core_hwid; 2297 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2298 2299 if (!object_class_by_name(typename)) { 2300 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2301 return; 2302 } 2303 2304 /* Cores */ 2305 pnv_chip_core_sanitize(pnv, chip, &error); 2306 if (error) { 2307 error_propagate(errp, error); 2308 return; 2309 } 2310 2311 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2312 2313 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2314 && (i < chip->nr_cores); core_hwid++) { 2315 char core_name[32]; 2316 PnvCore *pnv_core; 2317 uint64_t xscom_core_base; 2318 2319 if (!(chip->cores_mask & (1ull << core_hwid))) { 2320 continue; 2321 } 2322 2323 pnv_core = PNV_CORE(object_new(typename)); 2324 2325 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2326 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2327 chip->cores[i] = pnv_core; 2328 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2329 chip->nr_threads, &error_fatal); 2330 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2331 core_hwid, &error_fatal); 2332 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2333 &error_fatal); 2334 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2335 &error_fatal); 2336 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, 2337 &error_fatal); 2338 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2339 &error_abort); 2340 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2341 2342 /* Each core has an XSCOM MMIO region */ 2343 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2344 2345 pnv_xscom_add_subregion(chip, xscom_core_base, 2346 &pnv_core->xscom_regs); 2347 i++; 2348 } 2349 } 2350 2351 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2352 { 2353 PnvChip *chip = PNV_CHIP(dev); 2354 Error *error = NULL; 2355 2356 /* Cores */ 2357 pnv_chip_core_realize(chip, &error); 2358 if (error) { 2359 error_propagate(errp, error); 2360 return; 2361 } 2362 } 2363 2364 static Property pnv_chip_properties[] = { 2365 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2366 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2367 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2368 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2369 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2370 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2371 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false), 2372 DEFINE_PROP_END_OF_LIST(), 2373 }; 2374 2375 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2376 { 2377 DeviceClass *dc = DEVICE_CLASS(klass); 2378 2379 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2380 dc->realize = pnv_chip_realize; 2381 device_class_set_props(dc, pnv_chip_properties); 2382 dc->desc = "PowerNV Chip"; 2383 } 2384 2385 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2386 { 2387 int i; 2388 2389 for (i = 0; i < chip->nr_cores; i++) { 2390 PnvCore *pc = chip->cores[i]; 2391 CPUCore *cc = CPU_CORE(pc); 2392 2393 if (cc->core_id == core_id) { 2394 return pc; 2395 } 2396 } 2397 return NULL; 2398 } 2399 2400 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2401 { 2402 int i, j; 2403 2404 for (i = 0; i < chip->nr_cores; i++) { 2405 PnvCore *pc = chip->cores[i]; 2406 CPUCore *cc = CPU_CORE(pc); 2407 2408 for (j = 0; j < cc->nr_threads; j++) { 2409 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2410 return pc->threads[j]; 2411 } 2412 } 2413 } 2414 return NULL; 2415 } 2416 2417 static void pnv_chip_foreach_cpu(PnvChip *chip, 2418 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 2419 void *opaque) 2420 { 2421 int i, j; 2422 2423 for (i = 0; i < chip->nr_cores; i++) { 2424 PnvCore *pc = chip->cores[i]; 2425 2426 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 2427 fn(chip, pc->threads[j], opaque); 2428 } 2429 } 2430 } 2431 2432 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2433 { 2434 PnvMachineState *pnv = PNV_MACHINE(xi); 2435 int i, j; 2436 2437 for (i = 0; i < pnv->num_chips; i++) { 2438 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2439 2440 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2441 return &chip8->psi.ics; 2442 } 2443 2444 for (j = 0; j < chip8->num_phbs; j++) { 2445 PnvPHB *phb = chip8->phbs[j]; 2446 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2447 2448 if (ics_valid_irq(&phb3->lsis, irq)) { 2449 return &phb3->lsis; 2450 } 2451 2452 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2453 return ICS(&phb3->msis); 2454 } 2455 } 2456 } 2457 return NULL; 2458 } 2459 2460 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2461 { 2462 int i; 2463 2464 for (i = 0; i < pnv->num_chips; i++) { 2465 PnvChip *chip = pnv->chips[i]; 2466 if (chip->chip_id == chip_id) { 2467 return chip; 2468 } 2469 } 2470 return NULL; 2471 } 2472 2473 static void pnv_ics_resend(XICSFabric *xi) 2474 { 2475 PnvMachineState *pnv = PNV_MACHINE(xi); 2476 int i, j; 2477 2478 for (i = 0; i < pnv->num_chips; i++) { 2479 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2480 2481 ics_resend(&chip8->psi.ics); 2482 2483 for (j = 0; j < chip8->num_phbs; j++) { 2484 PnvPHB *phb = chip8->phbs[j]; 2485 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2486 2487 ics_resend(&phb3->lsis); 2488 ics_resend(ICS(&phb3->msis)); 2489 } 2490 } 2491 } 2492 2493 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2494 { 2495 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2496 2497 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2498 } 2499 2500 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 2501 void *opaque) 2502 { 2503 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 2504 } 2505 2506 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 2507 { 2508 PnvMachineState *pnv = PNV_MACHINE(obj); 2509 int i; 2510 2511 for (i = 0; i < pnv->num_chips; i++) { 2512 PnvChip *chip = pnv->chips[i]; 2513 2514 /* First CPU presenters */ 2515 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 2516 2517 /* Then other devices, PHB, PSI, XIVE */ 2518 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 2519 } 2520 } 2521 2522 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2523 uint8_t nvt_blk, uint32_t nvt_idx, 2524 bool cam_ignore, uint8_t priority, 2525 uint32_t logic_serv, 2526 XiveTCTXMatch *match) 2527 { 2528 PnvMachineState *pnv = PNV_MACHINE(xfb); 2529 int total_count = 0; 2530 int i; 2531 2532 for (i = 0; i < pnv->num_chips; i++) { 2533 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2534 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2535 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2536 int count; 2537 2538 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2539 priority, logic_serv, match); 2540 2541 if (count < 0) { 2542 return count; 2543 } 2544 2545 total_count += count; 2546 } 2547 2548 return total_count; 2549 } 2550 2551 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2552 uint8_t nvt_blk, uint32_t nvt_idx, 2553 bool cam_ignore, uint8_t priority, 2554 uint32_t logic_serv, 2555 XiveTCTXMatch *match) 2556 { 2557 PnvMachineState *pnv = PNV_MACHINE(xfb); 2558 int total_count = 0; 2559 int i; 2560 2561 for (i = 0; i < pnv->num_chips; i++) { 2562 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2563 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2564 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2565 int count; 2566 2567 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2568 priority, logic_serv, match); 2569 2570 if (count < 0) { 2571 return count; 2572 } 2573 2574 total_count += count; 2575 } 2576 2577 return total_count; 2578 } 2579 2580 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2581 { 2582 MachineClass *mc = MACHINE_CLASS(oc); 2583 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2584 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2585 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2586 2587 static GlobalProperty phb_compat[] = { 2588 { TYPE_PNV_PHB, "version", "3" }, 2589 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2590 }; 2591 2592 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2593 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2594 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2595 2596 xic->icp_get = pnv_icp_get; 2597 xic->ics_get = pnv_ics_get; 2598 xic->ics_resend = pnv_ics_resend; 2599 2600 pmc->compat = compat; 2601 pmc->compat_size = sizeof(compat); 2602 pmc->max_smt_threads = 8; 2603 2604 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2605 } 2606 2607 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2608 { 2609 MachineClass *mc = MACHINE_CLASS(oc); 2610 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2611 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2612 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2613 2614 static GlobalProperty phb_compat[] = { 2615 { TYPE_PNV_PHB, "version", "4" }, 2616 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2617 }; 2618 2619 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2620 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2621 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2622 2623 xfc->match_nvt = pnv_match_nvt; 2624 2625 pmc->compat = compat; 2626 pmc->compat_size = sizeof(compat); 2627 pmc->max_smt_threads = 4; 2628 pmc->dt_power_mgt = pnv_dt_power_mgt; 2629 2630 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2631 } 2632 2633 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2634 { 2635 MachineClass *mc = MACHINE_CLASS(oc); 2636 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2637 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2638 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2639 2640 static GlobalProperty phb_compat[] = { 2641 { TYPE_PNV_PHB, "version", "5" }, 2642 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2643 }; 2644 2645 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2646 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2647 2648 mc->alias = "powernv"; 2649 2650 pmc->compat = compat; 2651 pmc->compat_size = sizeof(compat); 2652 pmc->max_smt_threads = 4; 2653 pmc->dt_power_mgt = pnv_dt_power_mgt; 2654 2655 xfc->match_nvt = pnv10_xive_match_nvt; 2656 2657 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2658 } 2659 2660 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2661 { 2662 MachineClass *mc = MACHINE_CLASS(oc); 2663 2664 pnv_machine_p10_common_class_init(oc, data); 2665 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2666 } 2667 2668 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2669 { 2670 MachineClass *mc = MACHINE_CLASS(oc); 2671 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2672 2673 pnv_machine_p10_common_class_init(oc, data); 2674 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2675 pmc->i2c_init = pnv_rainier_i2c_init; 2676 } 2677 2678 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2679 { 2680 PnvMachineState *pnv = PNV_MACHINE(obj); 2681 2682 return !!pnv->fw_load_addr; 2683 } 2684 2685 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2686 { 2687 PnvMachineState *pnv = PNV_MACHINE(obj); 2688 2689 if (value) { 2690 pnv->fw_load_addr = 0x8000000; 2691 } 2692 } 2693 2694 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2695 { 2696 CPUPPCState *env = cpu_env(cs); 2697 2698 cpu_synchronize_state(cs); 2699 ppc_cpu_do_system_reset(cs); 2700 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2701 /* 2702 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2703 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2704 * (PPC_BIT(43)). 2705 */ 2706 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2707 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2708 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2709 } 2710 } else { 2711 /* 2712 * For non-powersave system resets, SRR1[42:45] are defined to be 2713 * implementation-dependent. The POWER9 User Manual specifies that 2714 * an external (SCOM driven, which may come from a BMC nmi command or 2715 * another CPU requesting a NMI IPI) system reset exception should be 2716 * 0b0010 (PPC_BIT(44)). 2717 */ 2718 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2719 } 2720 } 2721 2722 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 2723 { 2724 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2725 } 2726 2727 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2728 { 2729 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2730 int i; 2731 2732 for (i = 0; i < pnv->num_chips; i++) { 2733 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 2734 } 2735 } 2736 2737 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2738 { 2739 MachineClass *mc = MACHINE_CLASS(oc); 2740 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2741 NMIClass *nc = NMI_CLASS(oc); 2742 2743 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2744 mc->init = pnv_init; 2745 mc->reset = pnv_reset; 2746 mc->max_cpus = MAX_CPUS; 2747 /* Pnv provides a AHCI device for storage */ 2748 mc->block_default_type = IF_IDE; 2749 mc->no_parallel = 1; 2750 mc->default_boot_order = NULL; 2751 /* 2752 * RAM defaults to less than 2048 for 32-bit hosts, and large 2753 * enough to fit the maximum initrd size at it's load address 2754 */ 2755 mc->default_ram_size = 1 * GiB; 2756 mc->default_ram_id = "pnv.ram"; 2757 ispc->print_info = pnv_pic_print_info; 2758 nc->nmi_monitor_handler = pnv_nmi; 2759 2760 object_class_property_add_bool(oc, "hb-mode", 2761 pnv_machine_get_hb, pnv_machine_set_hb); 2762 object_class_property_set_description(oc, "hb-mode", 2763 "Use a hostboot like boot loader"); 2764 } 2765 2766 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2767 { \ 2768 .name = type, \ 2769 .class_init = class_initfn, \ 2770 .parent = TYPE_PNV8_CHIP, \ 2771 } 2772 2773 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2774 { \ 2775 .name = type, \ 2776 .class_init = class_initfn, \ 2777 .parent = TYPE_PNV9_CHIP, \ 2778 } 2779 2780 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2781 { \ 2782 .name = type, \ 2783 .class_init = class_initfn, \ 2784 .parent = TYPE_PNV10_CHIP, \ 2785 } 2786 2787 static const TypeInfo types[] = { 2788 { 2789 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2790 .parent = MACHINE_TYPE_NAME("powernv10"), 2791 .class_init = pnv_machine_p10_rainier_class_init, 2792 }, 2793 { 2794 .name = MACHINE_TYPE_NAME("powernv10"), 2795 .parent = TYPE_PNV_MACHINE, 2796 .class_init = pnv_machine_power10_class_init, 2797 .interfaces = (InterfaceInfo[]) { 2798 { TYPE_XIVE_FABRIC }, 2799 { }, 2800 }, 2801 }, 2802 { 2803 .name = MACHINE_TYPE_NAME("powernv9"), 2804 .parent = TYPE_PNV_MACHINE, 2805 .class_init = pnv_machine_power9_class_init, 2806 .interfaces = (InterfaceInfo[]) { 2807 { TYPE_XIVE_FABRIC }, 2808 { }, 2809 }, 2810 }, 2811 { 2812 .name = MACHINE_TYPE_NAME("powernv8"), 2813 .parent = TYPE_PNV_MACHINE, 2814 .class_init = pnv_machine_power8_class_init, 2815 .interfaces = (InterfaceInfo[]) { 2816 { TYPE_XICS_FABRIC }, 2817 { }, 2818 }, 2819 }, 2820 { 2821 .name = TYPE_PNV_MACHINE, 2822 .parent = TYPE_MACHINE, 2823 .abstract = true, 2824 .instance_size = sizeof(PnvMachineState), 2825 .class_init = pnv_machine_class_init, 2826 .class_size = sizeof(PnvMachineClass), 2827 .interfaces = (InterfaceInfo[]) { 2828 { TYPE_INTERRUPT_STATS_PROVIDER }, 2829 { TYPE_NMI }, 2830 { }, 2831 }, 2832 }, 2833 { 2834 .name = TYPE_PNV_CHIP, 2835 .parent = TYPE_SYS_BUS_DEVICE, 2836 .class_init = pnv_chip_class_init, 2837 .instance_size = sizeof(PnvChip), 2838 .class_size = sizeof(PnvChipClass), 2839 .abstract = true, 2840 }, 2841 2842 /* 2843 * P10 chip and variants 2844 */ 2845 { 2846 .name = TYPE_PNV10_CHIP, 2847 .parent = TYPE_PNV_CHIP, 2848 .instance_init = pnv_chip_power10_instance_init, 2849 .instance_size = sizeof(Pnv10Chip), 2850 }, 2851 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2852 2853 /* 2854 * P9 chip and variants 2855 */ 2856 { 2857 .name = TYPE_PNV9_CHIP, 2858 .parent = TYPE_PNV_CHIP, 2859 .instance_init = pnv_chip_power9_instance_init, 2860 .instance_size = sizeof(Pnv9Chip), 2861 }, 2862 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2863 2864 /* 2865 * P8 chip and variants 2866 */ 2867 { 2868 .name = TYPE_PNV8_CHIP, 2869 .parent = TYPE_PNV_CHIP, 2870 .instance_init = pnv_chip_power8_instance_init, 2871 .instance_size = sizeof(Pnv8Chip), 2872 }, 2873 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2874 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2875 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2876 pnv_chip_power8nvl_class_init), 2877 }; 2878 2879 DEFINE_TYPES(types) 2880