1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "hw/intc/intc.h" 42 #include "hw/ipmi/ipmi.h" 43 #include "target/ppc/mmu-hash64.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci-host/pnv_phb.h" 46 #include "hw/pci-host/pnv_phb3.h" 47 #include "hw/pci-host/pnv_phb4.h" 48 49 #include "hw/ppc/xics.h" 50 #include "hw/qdev-properties.h" 51 #include "hw/ppc/pnv_chip.h" 52 #include "hw/ppc/pnv_xscom.h" 53 #include "hw/ppc/pnv_pnor.h" 54 55 #include "hw/isa/isa.h" 56 #include "hw/char/serial.h" 57 #include "hw/rtc/mc146818rtc.h" 58 59 #include <libfdt.h> 60 61 #define FDT_MAX_SIZE (1 * MiB) 62 63 #define FW_FILE_NAME "skiboot.lid" 64 #define FW_LOAD_ADDR 0x0 65 #define FW_MAX_SIZE (16 * MiB) 66 67 #define KERNEL_LOAD_ADDR 0x20000000 68 #define KERNEL_MAX_SIZE (128 * MiB) 69 #define INITRD_LOAD_ADDR 0x28000000 70 #define INITRD_MAX_SIZE (128 * MiB) 71 72 static const char *pnv_chip_core_typename(const PnvChip *o) 73 { 74 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 76 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 77 const char *core_type = object_class_get_name(object_class_by_name(s)); 78 g_free(s); 79 return core_type; 80 } 81 82 /* 83 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 84 * 4 * 4 sockets * 12 cores * 8 threads = 1536 85 * Let's make it 2^11 86 */ 87 #define MAX_CPUS 2048 88 89 /* 90 * Memory nodes are created by hostboot, one for each range of memory 91 * that has a different "affinity". In practice, it means one range 92 * per chip. 93 */ 94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 95 { 96 char *mem_name; 97 uint64_t mem_reg_property[2]; 98 int off; 99 100 mem_reg_property[0] = cpu_to_be64(start); 101 mem_reg_property[1] = cpu_to_be64(size); 102 103 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 104 off = fdt_add_subnode(fdt, 0, mem_name); 105 g_free(mem_name); 106 107 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 108 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 109 sizeof(mem_reg_property)))); 110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 111 } 112 113 static int get_cpus_node(void *fdt) 114 { 115 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 116 117 if (cpus_offset < 0) { 118 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 119 if (cpus_offset) { 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 122 } 123 } 124 _FDT(cpus_offset); 125 return cpus_offset; 126 } 127 128 /* 129 * The PowerNV cores (and threads) need to use real HW ids and not an 130 * incremental index like it has been done on other platforms. This HW 131 * id is stored in the CPU PIR, it is used to create cpu nodes in the 132 * device tree, used in XSCOM to address cores and in interrupt 133 * servers. 134 */ 135 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 136 { 137 PowerPCCPU *cpu = pc->threads[0]; 138 CPUState *cs = CPU(cpu); 139 DeviceClass *dc = DEVICE_GET_CLASS(cs); 140 int smt_threads = CPU_CORE(pc)->nr_threads; 141 CPUPPCState *env = &cpu->env; 142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 143 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t pir; 147 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 148 0xffffffff, 0xffffffff}; 149 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 150 uint32_t cpufreq = 1000000000; 151 uint32_t page_sizes_prop[64]; 152 size_t page_sizes_prop_size; 153 int offset; 154 char *nodename; 155 int cpus_offset = get_cpus_node(fdt); 156 157 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, NULL); 158 159 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 160 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 161 _FDT(offset); 162 g_free(nodename); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 168 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 169 170 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 172 env->dcache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 176 env->icache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 178 env->icache_line_size))); 179 180 if (pcc->l1_dcache_size) { 181 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 182 pcc->l1_dcache_size))); 183 } else { 184 warn_report("Unknown L1 dcache size for cpu"); 185 } 186 if (pcc->l1_icache_size) { 187 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 188 pcc->l1_icache_size))); 189 } else { 190 warn_report("Unknown L1 icache size for cpu"); 191 } 192 193 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 195 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 196 cpu->hash64_opts->slb_size))); 197 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 198 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 199 200 if (ppc_has_spr(cpu, SPR_PURR)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 202 } 203 204 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 205 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 206 segs, sizeof(segs)))); 207 } 208 209 /* 210 * Advertise VMX/VSX (vector extensions) if available 211 * 0 / no property == no vector extensions 212 * 1 == VMX / Altivec available 213 * 2 == VSX available 214 */ 215 if (env->insns_flags & PPC_ALTIVEC) { 216 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 217 218 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 219 } 220 221 /* 222 * Advertise DFP (Decimal Floating Point) if available 223 * 0 / no property == no DFP 224 * 1 == DFP available 225 */ 226 if (env->insns_flags2 & PPC2_DFP) { 227 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 228 } 229 230 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 231 sizeof(page_sizes_prop)); 232 if (page_sizes_prop_size) { 233 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 234 page_sizes_prop, page_sizes_prop_size))); 235 } 236 237 /* Build interrupt servers properties */ 238 for (i = 0; i < smt_threads; i++) { 239 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 240 servers_prop[i] = cpu_to_be32(pir); 241 } 242 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 243 servers_prop, sizeof(*servers_prop) * smt_threads))); 244 245 return offset; 246 } 247 248 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 249 uint32_t nr_threads) 250 { 251 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 252 uint32_t pir; 253 uint64_t addr; 254 char *name; 255 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 256 uint32_t irange[2], i, rsize; 257 uint64_t *reg; 258 int offset; 259 260 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); 261 addr = PNV_ICP_BASE(chip) | (pir << 12); 262 263 irange[0] = cpu_to_be32(pir); 264 irange[1] = cpu_to_be32(nr_threads); 265 266 rsize = sizeof(uint64_t) * 2 * nr_threads; 267 reg = g_malloc(rsize); 268 for (i = 0; i < nr_threads; i++) { 269 /* We know P8 PIR is linear with thread id */ 270 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 271 reg[i * 2 + 1] = cpu_to_be64(0x1000); 272 } 273 274 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 275 offset = fdt_add_subnode(fdt, 0, name); 276 _FDT(offset); 277 g_free(name); 278 279 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 280 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 281 _FDT((fdt_setprop_string(fdt, offset, "device_type", 282 "PowerPC-External-Interrupt-Presentation"))); 283 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 284 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 285 irange, sizeof(irange)))); 286 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 287 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 288 g_free(reg); 289 } 290 291 /* 292 * Adds a PnvPHB to the chip on P8. 293 * Implemented here, like for defaults PHBs 294 */ 295 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 296 { 297 Pnv8Chip *chip8 = PNV8_CHIP(chip); 298 299 phb->chip = chip; 300 301 chip8->phbs[chip8->num_phbs] = phb; 302 chip8->num_phbs++; 303 return chip; 304 } 305 306 /* 307 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 308 * HTM is always enabled because TCG does implement HTM, it's just a 309 * degenerate implementation. 310 */ 311 static const uint8_t pa_features_207[] = { 24, 0, 312 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 313 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 314 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 315 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 316 317 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 318 { 319 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 320 int i; 321 322 pnv_dt_xscom(chip, fdt, 0, 323 cpu_to_be64(PNV_XSCOM_BASE(chip)), 324 cpu_to_be64(PNV_XSCOM_SIZE), 325 compat, sizeof(compat)); 326 327 for (i = 0; i < chip->nr_cores; i++) { 328 PnvCore *pnv_core = chip->cores[i]; 329 int offset; 330 331 offset = pnv_dt_core(chip, pnv_core, fdt); 332 333 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 334 pa_features_207, sizeof(pa_features_207)))); 335 336 /* Interrupt Control Presenters (ICP). One per core. */ 337 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 338 } 339 340 if (chip->ram_size) { 341 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 342 } 343 } 344 345 /* 346 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 347 */ 348 static const uint8_t pa_features_300[] = { 66, 0, 349 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 350 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 351 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 352 /* 6: DS207 */ 353 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 354 /* 16: Vector */ 355 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 356 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 357 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 358 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 359 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 360 /* 32: LE atomic, 34: EBB + ext EBB */ 361 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 362 /* 40: Radix MMU */ 363 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 364 /* 42: PM, 44: PC RA, 46: SC vec'd */ 365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 366 /* 48: SIMD, 50: QP BFP, 52: String */ 367 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 368 /* 54: DecFP, 56: DecI, 58: SHA */ 369 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 370 /* 60: NM atomic, 62: RNG */ 371 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 372 }; 373 374 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 375 { 376 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 377 int i; 378 379 pnv_dt_xscom(chip, fdt, 0, 380 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 381 cpu_to_be64(PNV9_XSCOM_SIZE), 382 compat, sizeof(compat)); 383 384 for (i = 0; i < chip->nr_cores; i++) { 385 PnvCore *pnv_core = chip->cores[i]; 386 int offset; 387 388 offset = pnv_dt_core(chip, pnv_core, fdt); 389 390 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 391 pa_features_300, sizeof(pa_features_300)))); 392 } 393 394 if (chip->ram_size) { 395 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 396 } 397 398 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 399 } 400 401 /* 402 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 403 * always disables copy/paste. 404 */ 405 static const uint8_t pa_features_31[] = { 74, 0, 406 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 407 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 408 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 409 /* 6: DS207 */ 410 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 411 /* 16: Vector */ 412 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 413 /* 18: Vec. Scalar, 20: Vec. XOR */ 414 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 415 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 416 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 417 /* 32: LE atomic, 34: EBB + ext EBB */ 418 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 419 /* 40: Radix MMU */ 420 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 421 /* 42: PM, 44: PC RA, 46: SC vec'd */ 422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 423 /* 48: SIMD, 50: QP BFP, 52: String */ 424 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 425 /* 54: DecFP, 56: DecI, 58: SHA */ 426 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 427 /* 60: NM atomic, 62: RNG */ 428 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 429 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 430 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 431 /* 72: [P]HASHST/[P]HASHCHK */ 432 0x80, 0x00, /* 72 - 73 */ 433 }; 434 435 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 436 { 437 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 438 int i; 439 440 pnv_dt_xscom(chip, fdt, 0, 441 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 442 cpu_to_be64(PNV10_XSCOM_SIZE), 443 compat, sizeof(compat)); 444 445 for (i = 0; i < chip->nr_cores; i++) { 446 PnvCore *pnv_core = chip->cores[i]; 447 int offset; 448 449 offset = pnv_dt_core(chip, pnv_core, fdt); 450 451 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 452 pa_features_31, sizeof(pa_features_31)))); 453 } 454 455 if (chip->ram_size) { 456 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 457 } 458 459 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 460 } 461 462 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 463 { 464 uint32_t io_base = d->ioport_id; 465 uint32_t io_regs[] = { 466 cpu_to_be32(1), 467 cpu_to_be32(io_base), 468 cpu_to_be32(2) 469 }; 470 char *name; 471 int node; 472 473 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 474 node = fdt_add_subnode(fdt, lpc_off, name); 475 _FDT(node); 476 g_free(name); 477 478 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 479 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 480 } 481 482 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 483 { 484 const char compatible[] = "ns16550\0pnpPNP,501"; 485 uint32_t io_base = d->ioport_id; 486 uint32_t io_regs[] = { 487 cpu_to_be32(1), 488 cpu_to_be32(io_base), 489 cpu_to_be32(8) 490 }; 491 uint32_t irq; 492 char *name; 493 int node; 494 495 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 496 497 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 498 node = fdt_add_subnode(fdt, lpc_off, name); 499 _FDT(node); 500 g_free(name); 501 502 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 503 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 504 sizeof(compatible)))); 505 506 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 507 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 508 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 509 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 510 fdt_get_phandle(fdt, lpc_off)))); 511 512 /* This is needed by Linux */ 513 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 514 } 515 516 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 517 { 518 const char compatible[] = "bt\0ipmi-bt"; 519 uint32_t io_base; 520 uint32_t io_regs[] = { 521 cpu_to_be32(1), 522 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 523 cpu_to_be32(3) 524 }; 525 uint32_t irq; 526 char *name; 527 int node; 528 529 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 530 io_regs[1] = cpu_to_be32(io_base); 531 532 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 533 534 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 535 node = fdt_add_subnode(fdt, lpc_off, name); 536 _FDT(node); 537 g_free(name); 538 539 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 540 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 541 sizeof(compatible)))); 542 543 /* Mark it as reserved to avoid Linux trying to claim it */ 544 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 545 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 546 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 547 fdt_get_phandle(fdt, lpc_off)))); 548 } 549 550 typedef struct ForeachPopulateArgs { 551 void *fdt; 552 int offset; 553 } ForeachPopulateArgs; 554 555 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 556 { 557 ForeachPopulateArgs *args = opaque; 558 ISADevice *d = ISA_DEVICE(dev); 559 560 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 561 pnv_dt_rtc(d, args->fdt, args->offset); 562 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 563 pnv_dt_serial(d, args->fdt, args->offset); 564 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 565 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 566 } else { 567 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 568 d->ioport_id); 569 } 570 571 return 0; 572 } 573 574 /* 575 * The default LPC bus of a multichip system is on chip 0. It's 576 * recognized by the firmware (skiboot) using a "primary" property. 577 */ 578 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 579 { 580 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 581 ForeachPopulateArgs args = { 582 .fdt = fdt, 583 .offset = isa_offset, 584 }; 585 uint32_t phandle; 586 587 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 588 589 phandle = qemu_fdt_alloc_phandle(fdt); 590 assert(phandle > 0); 591 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 592 593 /* 594 * ISA devices are not necessarily parented to the ISA bus so we 595 * can not use object_child_foreach() 596 */ 597 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 598 &args); 599 } 600 601 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 602 { 603 int off; 604 605 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 606 off = fdt_add_subnode(fdt, off, "power-mgt"); 607 608 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 609 } 610 611 static void *pnv_dt_create(MachineState *machine) 612 { 613 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 614 PnvMachineState *pnv = PNV_MACHINE(machine); 615 void *fdt; 616 char *buf; 617 int off; 618 int i; 619 620 fdt = g_malloc0(FDT_MAX_SIZE); 621 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 622 623 /* /qemu node */ 624 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 625 626 /* Root node */ 627 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 628 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 629 _FDT((fdt_setprop_string(fdt, 0, "model", 630 "IBM PowerNV (emulated by qemu)"))); 631 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 632 633 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 634 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 635 if (qemu_uuid_set) { 636 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 637 } 638 g_free(buf); 639 640 off = fdt_add_subnode(fdt, 0, "chosen"); 641 if (machine->kernel_cmdline) { 642 _FDT((fdt_setprop_string(fdt, off, "bootargs", 643 machine->kernel_cmdline))); 644 } 645 646 if (pnv->initrd_size) { 647 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 648 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 649 650 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 651 &start_prop, sizeof(start_prop)))); 652 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 653 &end_prop, sizeof(end_prop)))); 654 } 655 656 /* Populate device tree for each chip */ 657 for (i = 0; i < pnv->num_chips; i++) { 658 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 659 } 660 661 /* Populate ISA devices on chip 0 */ 662 pnv_dt_isa(pnv, fdt); 663 664 if (pnv->bmc) { 665 pnv_dt_bmc_sensors(pnv->bmc, fdt); 666 } 667 668 /* Create an extra node for power management on machines that support it */ 669 if (pmc->dt_power_mgt) { 670 pmc->dt_power_mgt(pnv, fdt); 671 } 672 673 return fdt; 674 } 675 676 static void pnv_powerdown_notify(Notifier *n, void *opaque) 677 { 678 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 679 680 if (pnv->bmc) { 681 pnv_bmc_powerdown(pnv->bmc); 682 } 683 } 684 685 static void pnv_reset(MachineState *machine, ShutdownCause reason) 686 { 687 PnvMachineState *pnv = PNV_MACHINE(machine); 688 IPMIBmc *bmc; 689 void *fdt; 690 691 qemu_devices_reset(reason); 692 693 /* 694 * The machine should provide by default an internal BMC simulator. 695 * If not, try to use the BMC device that was provided on the command 696 * line. 697 */ 698 bmc = pnv_bmc_find(&error_fatal); 699 if (!pnv->bmc) { 700 if (!bmc) { 701 if (!qtest_enabled()) { 702 warn_report("machine has no BMC device. Use '-device " 703 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 704 "to define one"); 705 } 706 } else { 707 pnv_bmc_set_pnor(bmc, pnv->pnor); 708 pnv->bmc = bmc; 709 } 710 } 711 712 fdt = pnv_dt_create(machine); 713 714 /* Pack resulting tree */ 715 _FDT((fdt_pack(fdt))); 716 717 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 718 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 719 720 /* 721 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 722 * the existing machine->fdt to avoid leaking it during 723 * a reset. 724 */ 725 g_free(machine->fdt); 726 machine->fdt = fdt; 727 } 728 729 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 730 { 731 Pnv8Chip *chip8 = PNV8_CHIP(chip); 732 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 733 734 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 735 736 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 737 } 738 739 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 740 { 741 Pnv8Chip *chip8 = PNV8_CHIP(chip); 742 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 743 744 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 745 746 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 747 } 748 749 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 750 { 751 Pnv9Chip *chip9 = PNV9_CHIP(chip); 752 qemu_irq irq; 753 754 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 755 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 756 757 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 758 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 759 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 760 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 761 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 762 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 763 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 764 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 765 766 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 767 } 768 769 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 770 { 771 Pnv10Chip *chip10 = PNV10_CHIP(chip); 772 qemu_irq irq; 773 774 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 775 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 776 777 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 778 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 779 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 780 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 781 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 782 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 783 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 784 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 785 786 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 787 } 788 789 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 790 { 791 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 792 } 793 794 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 795 { 796 Pnv8Chip *chip8 = PNV8_CHIP(chip); 797 int i; 798 799 ics_pic_print_info(&chip8->psi.ics, buf); 800 801 for (i = 0; i < chip8->num_phbs; i++) { 802 PnvPHB *phb = chip8->phbs[i]; 803 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 804 805 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 806 ics_pic_print_info(&phb3->lsis, buf); 807 } 808 } 809 810 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 811 { 812 GString *buf = opaque; 813 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 814 815 if (!phb) { 816 return 0; 817 } 818 819 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 820 821 return 0; 822 } 823 824 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 825 { 826 Pnv9Chip *chip9 = PNV9_CHIP(chip); 827 828 pnv_xive_pic_print_info(&chip9->xive, buf); 829 pnv_psi_pic_print_info(&chip9->psi, buf); 830 object_child_foreach_recursive(OBJECT(chip), 831 pnv_chip_power9_pic_print_info_child, buf); 832 } 833 834 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 835 uint32_t core_id) 836 { 837 return PNV_XSCOM_EX_BASE(core_id); 838 } 839 840 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 841 uint32_t core_id) 842 { 843 return PNV9_XSCOM_EC_BASE(core_id); 844 } 845 846 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 847 uint32_t core_id) 848 { 849 return PNV10_XSCOM_EC_BASE(core_id); 850 } 851 852 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 853 { 854 PowerPCCPUClass *ppc_default = 855 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 856 PowerPCCPUClass *ppc = 857 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 858 859 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 860 } 861 862 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 863 { 864 ISADevice *dev = isa_new("isa-ipmi-bt"); 865 866 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 867 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 868 isa_realize_and_unref(dev, bus, &error_fatal); 869 } 870 871 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 872 { 873 Pnv10Chip *chip10 = PNV10_CHIP(chip); 874 875 pnv_xive2_pic_print_info(&chip10->xive, buf); 876 pnv_psi_pic_print_info(&chip10->psi, buf); 877 object_child_foreach_recursive(OBJECT(chip), 878 pnv_chip_power9_pic_print_info_child, buf); 879 } 880 881 /* Always give the first 1GB to chip 0 else we won't boot */ 882 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 883 { 884 MachineState *machine = MACHINE(pnv); 885 uint64_t ram_per_chip; 886 887 assert(machine->ram_size >= 1 * GiB); 888 889 ram_per_chip = machine->ram_size / pnv->num_chips; 890 if (ram_per_chip >= 1 * GiB) { 891 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 892 } 893 894 assert(pnv->num_chips > 1); 895 896 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 897 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 898 } 899 900 static void pnv_init(MachineState *machine) 901 { 902 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 903 PnvMachineState *pnv = PNV_MACHINE(machine); 904 MachineClass *mc = MACHINE_GET_CLASS(machine); 905 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 906 int max_smt_threads = pmc->max_smt_threads; 907 char *fw_filename; 908 long fw_size; 909 uint64_t chip_ram_start = 0; 910 int i; 911 char *chip_typename; 912 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 913 DeviceState *dev; 914 915 if (kvm_enabled()) { 916 error_report("machine %s does not support the KVM accelerator", 917 mc->name); 918 exit(EXIT_FAILURE); 919 } 920 921 /* allocate RAM */ 922 if (machine->ram_size < mc->default_ram_size) { 923 char *sz = size_to_str(mc->default_ram_size); 924 error_report("Invalid RAM size, should be bigger than %s", sz); 925 g_free(sz); 926 exit(EXIT_FAILURE); 927 } 928 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 929 930 /* 931 * Create our simple PNOR device 932 */ 933 dev = qdev_new(TYPE_PNV_PNOR); 934 if (pnor) { 935 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 936 } 937 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 938 pnv->pnor = PNV_PNOR(dev); 939 940 /* load skiboot firmware */ 941 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 942 if (!fw_filename) { 943 error_report("Could not find OPAL firmware '%s'", bios_name); 944 exit(1); 945 } 946 947 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 948 if (fw_size < 0) { 949 error_report("Could not load OPAL firmware '%s'", fw_filename); 950 exit(1); 951 } 952 g_free(fw_filename); 953 954 /* load kernel */ 955 if (machine->kernel_filename) { 956 long kernel_size; 957 958 kernel_size = load_image_targphys(machine->kernel_filename, 959 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 960 if (kernel_size < 0) { 961 error_report("Could not load kernel '%s'", 962 machine->kernel_filename); 963 exit(1); 964 } 965 } 966 967 /* load initrd */ 968 if (machine->initrd_filename) { 969 pnv->initrd_base = INITRD_LOAD_ADDR; 970 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 971 pnv->initrd_base, INITRD_MAX_SIZE); 972 if (pnv->initrd_size < 0) { 973 error_report("Could not load initial ram disk '%s'", 974 machine->initrd_filename); 975 exit(1); 976 } 977 } 978 979 /* MSIs are supported on this platform */ 980 msi_nonbroken = true; 981 982 /* 983 * Check compatibility of the specified CPU with the machine 984 * default. 985 */ 986 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 987 error_report("invalid CPU model '%s' for %s machine", 988 machine->cpu_type, mc->name); 989 exit(1); 990 } 991 992 /* Create the processor chips */ 993 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 994 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 995 i, machine->cpu_type); 996 if (!object_class_by_name(chip_typename)) { 997 error_report("invalid chip model '%.*s' for %s machine", 998 i, machine->cpu_type, mc->name); 999 exit(1); 1000 } 1001 1002 pnv->num_chips = 1003 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 1004 1005 if (pnv->big_core) { 1006 if (machine->smp.threads % 2 == 1) { 1007 error_report("Cannot support %d threads with big-core option " 1008 "because it must be an even number", 1009 machine->smp.threads); 1010 exit(1); 1011 } 1012 max_smt_threads *= 2; 1013 } 1014 1015 if (machine->smp.threads > max_smt_threads) { 1016 error_report("Cannot support more than %d threads/core " 1017 "on %s machine", max_smt_threads, mc->desc); 1018 if (pmc->max_smt_threads == 4) { 1019 error_report("(use big-core=on for 8 threads per core)"); 1020 } 1021 exit(1); 1022 } 1023 1024 if (pnv->big_core) { 1025 /* 1026 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore 1027 * per core, so adjust topology here. pnv_dt_core() processor 1028 * device-tree and TCG SMT code make the 2 cores appear as one big core 1029 * from software point of view. pnv pervasive models and xscoms tend to 1030 * see the big core as 2 small core halves. 1031 */ 1032 machine->smp.cores *= 2; 1033 machine->smp.threads /= 2; 1034 } 1035 1036 if (!is_power_of_2(machine->smp.threads)) { 1037 error_report("Cannot support %d threads/core on a powernv " 1038 "machine because it must be a power of 2", 1039 machine->smp.threads); 1040 exit(1); 1041 } 1042 1043 /* 1044 * TODO: should we decide on how many chips we can create based 1045 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1046 */ 1047 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1048 error_report("invalid number of chips: '%d'", pnv->num_chips); 1049 error_printf( 1050 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1051 exit(1); 1052 } 1053 1054 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1055 for (i = 0; i < pnv->num_chips; i++) { 1056 char chip_name[32]; 1057 Object *chip = OBJECT(qdev_new(chip_typename)); 1058 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1059 1060 pnv->chips[i] = PNV_CHIP(chip); 1061 1062 /* Distribute RAM among the chips */ 1063 object_property_set_int(chip, "ram-start", chip_ram_start, 1064 &error_fatal); 1065 object_property_set_int(chip, "ram-size", chip_ram_size, 1066 &error_fatal); 1067 chip_ram_start += chip_ram_size; 1068 1069 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1070 object_property_add_child(OBJECT(pnv), chip_name, chip); 1071 object_property_set_int(chip, "chip-id", i, &error_fatal); 1072 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1073 &error_fatal); 1074 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1075 &error_fatal); 1076 object_property_set_bool(chip, "big-core", pnv->big_core, 1077 &error_fatal); 1078 /* 1079 * The POWER8 machine use the XICS interrupt interface. 1080 * Propagate the XICS fabric to the chip and its controllers. 1081 */ 1082 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1083 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1084 } 1085 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1086 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1087 &error_abort); 1088 } 1089 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1090 } 1091 g_free(chip_typename); 1092 1093 /* Instantiate ISA bus on chip 0 */ 1094 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1095 1096 /* Create serial port */ 1097 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1098 1099 /* Create an RTC ISA device too */ 1100 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1101 1102 /* 1103 * Create the machine BMC simulator and the IPMI BT device for 1104 * communication with the BMC 1105 */ 1106 if (defaults_enabled()) { 1107 pnv->bmc = pnv_bmc_create(pnv->pnor); 1108 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1109 } 1110 1111 /* 1112 * The PNOR is mapped on the LPC FW address space by the BMC. 1113 * Since we can not reach the remote BMC machine with LPC memops, 1114 * map it always for now. 1115 */ 1116 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1117 &pnv->pnor->mmio); 1118 1119 /* 1120 * OpenPOWER systems use a IPMI SEL Event message to notify the 1121 * host to powerdown 1122 */ 1123 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1124 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1125 1126 /* 1127 * Create/Connect any machine-specific I2C devices 1128 */ 1129 if (pmc->i2c_init) { 1130 pmc->i2c_init(pnv); 1131 } 1132 } 1133 1134 /* 1135 * 0:21 Reserved - Read as zeros 1136 * 22:24 Chip ID 1137 * 25:28 Core number 1138 * 29:31 Thread ID 1139 */ 1140 static void pnv_get_pir_tir_p8(PnvChip *chip, 1141 uint32_t core_id, uint32_t thread_id, 1142 uint32_t *pir, uint32_t *tir) 1143 { 1144 if (pir) { 1145 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; 1146 } 1147 if (tir) { 1148 *tir = thread_id; 1149 } 1150 } 1151 1152 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1153 Error **errp) 1154 { 1155 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1156 Error *local_err = NULL; 1157 Object *obj; 1158 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1159 1160 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1161 if (local_err) { 1162 error_propagate(errp, local_err); 1163 return; 1164 } 1165 1166 pnv_cpu->intc = obj; 1167 } 1168 1169 1170 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1171 { 1172 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1173 1174 icp_reset(ICP(pnv_cpu->intc)); 1175 } 1176 1177 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1178 { 1179 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1180 1181 icp_destroy(ICP(pnv_cpu->intc)); 1182 pnv_cpu->intc = NULL; 1183 } 1184 1185 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1186 GString *buf) 1187 { 1188 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1189 } 1190 1191 /* 1192 * 0:48 Reserved - Read as zeroes 1193 * 49:52 Node ID 1194 * 53:55 Chip ID 1195 * 56 Reserved - Read as zero 1196 * 57:61 Core number 1197 * 62:63 Thread ID 1198 * 1199 * We only care about the lower bits. uint32_t is fine for the moment. 1200 */ 1201 static void pnv_get_pir_tir_p9(PnvChip *chip, 1202 uint32_t core_id, uint32_t thread_id, 1203 uint32_t *pir, uint32_t *tir) 1204 { 1205 if (chip->big_core) { 1206 /* Big-core interleaves thread ID between small-cores */ 1207 thread_id <<= 1; 1208 thread_id |= core_id & 1; 1209 core_id >>= 1; 1210 1211 if (pir) { 1212 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1213 } 1214 } else { 1215 if (pir) { 1216 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1217 } 1218 } 1219 if (tir) { 1220 *tir = thread_id; 1221 } 1222 } 1223 1224 /* 1225 * 0:48 Reserved - Read as zeroes 1226 * 49:52 Node ID 1227 * 53:55 Chip ID 1228 * 56 Reserved - Read as zero 1229 * 57:59 Quad ID 1230 * 60 Core Chiplet Pair ID 1231 * 61:63 Thread/Core Chiplet ID t0-t2 1232 * 1233 * We only care about the lower bits. uint32_t is fine for the moment. 1234 */ 1235 static void pnv_get_pir_tir_p10(PnvChip *chip, 1236 uint32_t core_id, uint32_t thread_id, 1237 uint32_t *pir, uint32_t *tir) 1238 { 1239 if (chip->big_core) { 1240 /* Big-core interleaves thread ID between small-cores */ 1241 thread_id <<= 1; 1242 thread_id |= core_id & 1; 1243 core_id >>= 1; 1244 1245 if (pir) { 1246 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1247 } 1248 } else { 1249 if (pir) { 1250 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1251 } 1252 } 1253 if (tir) { 1254 *tir = thread_id; 1255 } 1256 } 1257 1258 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1259 Error **errp) 1260 { 1261 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1262 Error *local_err = NULL; 1263 Object *obj; 1264 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1265 1266 /* 1267 * The core creates its interrupt presenter but the XIVE interrupt 1268 * controller object is initialized afterwards. Hopefully, it's 1269 * only used at runtime. 1270 */ 1271 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1272 &local_err); 1273 if (local_err) { 1274 error_propagate(errp, local_err); 1275 return; 1276 } 1277 1278 pnv_cpu->intc = obj; 1279 } 1280 1281 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1282 { 1283 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1284 1285 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1286 } 1287 1288 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1289 { 1290 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1291 1292 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1293 pnv_cpu->intc = NULL; 1294 } 1295 1296 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1297 GString *buf) 1298 { 1299 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1300 } 1301 1302 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1303 Error **errp) 1304 { 1305 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1306 Error *local_err = NULL; 1307 Object *obj; 1308 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1309 1310 /* 1311 * The core creates its interrupt presenter but the XIVE2 interrupt 1312 * controller object is initialized afterwards. Hopefully, it's 1313 * only used at runtime. 1314 */ 1315 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1316 &local_err); 1317 if (local_err) { 1318 error_propagate(errp, local_err); 1319 return; 1320 } 1321 1322 pnv_cpu->intc = obj; 1323 } 1324 1325 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1326 { 1327 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1328 1329 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1330 } 1331 1332 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1333 { 1334 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1335 1336 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1337 pnv_cpu->intc = NULL; 1338 } 1339 1340 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1341 GString *buf) 1342 { 1343 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1344 } 1345 1346 /* 1347 * Allowed core identifiers on a POWER8 Processor Chip : 1348 * 1349 * <EX0 reserved> 1350 * EX1 - Venice only 1351 * EX2 - Venice only 1352 * EX3 - Venice only 1353 * EX4 1354 * EX5 1355 * EX6 1356 * <EX7,8 reserved> <reserved> 1357 * EX9 - Venice only 1358 * EX10 - Venice only 1359 * EX11 - Venice only 1360 * EX12 1361 * EX13 1362 * EX14 1363 * <EX15 reserved> 1364 */ 1365 #define POWER8E_CORE_MASK (0x7070ull) 1366 #define POWER8_CORE_MASK (0x7e7eull) 1367 1368 /* 1369 * POWER9 has 24 cores, ids starting at 0x0 1370 */ 1371 #define POWER9_CORE_MASK (0xffffffffffffffull) 1372 1373 1374 #define POWER10_CORE_MASK (0xffffffffffffffull) 1375 1376 static void pnv_chip_power8_instance_init(Object *obj) 1377 { 1378 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1379 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1380 int i; 1381 1382 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1383 (Object **)&chip8->xics, 1384 object_property_allow_set_link, 1385 OBJ_PROP_LINK_STRONG); 1386 1387 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1388 1389 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1390 1391 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1392 1393 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1394 1395 if (defaults_enabled()) { 1396 chip8->num_phbs = pcc->num_phbs; 1397 1398 for (i = 0; i < chip8->num_phbs; i++) { 1399 Object *phb = object_new(TYPE_PNV_PHB); 1400 1401 /* 1402 * We need the chip to parent the PHB to allow the DT 1403 * to build correctly (via pnv_xscom_dt()). 1404 * 1405 * TODO: the PHB should be parented by a PEC device that, at 1406 * this moment, is not modelled powernv8/phb3. 1407 */ 1408 object_property_add_child(obj, "phb[*]", phb); 1409 chip8->phbs[i] = PNV_PHB(phb); 1410 } 1411 } 1412 1413 } 1414 1415 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1416 { 1417 PnvChip *chip = PNV_CHIP(chip8); 1418 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1419 int i, j; 1420 char *name; 1421 1422 name = g_strdup_printf("icp-%x", chip->chip_id); 1423 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1424 g_free(name); 1425 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1426 &chip8->icp_mmio); 1427 1428 /* Map the ICP registers for each thread */ 1429 for (i = 0; i < chip->nr_cores; i++) { 1430 PnvCore *pnv_core = chip->cores[i]; 1431 int core_hwid = CPU_CORE(pnv_core)->core_id; 1432 1433 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1434 uint32_t pir; 1435 PnvICPState *icp; 1436 1437 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); 1438 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1439 1440 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1441 &icp->mmio); 1442 } 1443 } 1444 } 1445 1446 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1447 { 1448 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1449 PnvChip *chip = PNV_CHIP(dev); 1450 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1451 Pnv8Psi *psi8 = &chip8->psi; 1452 Error *local_err = NULL; 1453 int i; 1454 1455 assert(chip8->xics); 1456 1457 /* XSCOM bridge is first */ 1458 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1459 1460 pcc->parent_realize(dev, &local_err); 1461 if (local_err) { 1462 error_propagate(errp, local_err); 1463 return; 1464 } 1465 1466 /* Processor Service Interface (PSI) Host Bridge */ 1467 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1468 &error_fatal); 1469 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1470 OBJECT(chip8->xics), &error_abort); 1471 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1472 return; 1473 } 1474 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1475 &PNV_PSI(psi8)->xscom_regs); 1476 1477 /* Create LPC controller */ 1478 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1479 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1480 1481 chip->fw_mr = &chip8->lpc.isa_fw; 1482 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1483 (uint64_t) PNV_XSCOM_BASE(chip), 1484 PNV_XSCOM_LPC_BASE); 1485 1486 /* 1487 * Interrupt Management Area. This is the memory region holding 1488 * all the Interrupt Control Presenter (ICP) registers 1489 */ 1490 pnv_chip_icp_realize(chip8, &local_err); 1491 if (local_err) { 1492 error_propagate(errp, local_err); 1493 return; 1494 } 1495 1496 /* Create the simplified OCC model */ 1497 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1498 return; 1499 } 1500 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1501 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1502 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1503 1504 /* OCC SRAM model */ 1505 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1506 &chip8->occ.sram_regs); 1507 1508 /* HOMER */ 1509 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1510 &error_abort); 1511 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1512 return; 1513 } 1514 /* Homer Xscom region */ 1515 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1516 1517 /* Homer mmio region */ 1518 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1519 &chip8->homer.regs); 1520 1521 /* PHB controllers */ 1522 for (i = 0; i < chip8->num_phbs; i++) { 1523 PnvPHB *phb = chip8->phbs[i]; 1524 1525 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1526 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1527 &error_fatal); 1528 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1529 &error_fatal); 1530 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1531 return; 1532 } 1533 } 1534 } 1535 1536 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1537 { 1538 addr &= (PNV_XSCOM_SIZE - 1); 1539 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1540 } 1541 1542 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1543 { 1544 DeviceClass *dc = DEVICE_CLASS(klass); 1545 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1546 1547 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1548 k->cores_mask = POWER8E_CORE_MASK; 1549 k->num_phbs = 3; 1550 k->get_pir_tir = pnv_get_pir_tir_p8; 1551 k->intc_create = pnv_chip_power8_intc_create; 1552 k->intc_reset = pnv_chip_power8_intc_reset; 1553 k->intc_destroy = pnv_chip_power8_intc_destroy; 1554 k->intc_print_info = pnv_chip_power8_intc_print_info; 1555 k->isa_create = pnv_chip_power8_isa_create; 1556 k->dt_populate = pnv_chip_power8_dt_populate; 1557 k->pic_print_info = pnv_chip_power8_pic_print_info; 1558 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1559 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1560 dc->desc = "PowerNV Chip POWER8E"; 1561 1562 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1563 &k->parent_realize); 1564 } 1565 1566 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1567 { 1568 DeviceClass *dc = DEVICE_CLASS(klass); 1569 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1570 1571 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1572 k->cores_mask = POWER8_CORE_MASK; 1573 k->num_phbs = 3; 1574 k->get_pir_tir = pnv_get_pir_tir_p8; 1575 k->intc_create = pnv_chip_power8_intc_create; 1576 k->intc_reset = pnv_chip_power8_intc_reset; 1577 k->intc_destroy = pnv_chip_power8_intc_destroy; 1578 k->intc_print_info = pnv_chip_power8_intc_print_info; 1579 k->isa_create = pnv_chip_power8_isa_create; 1580 k->dt_populate = pnv_chip_power8_dt_populate; 1581 k->pic_print_info = pnv_chip_power8_pic_print_info; 1582 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1583 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1584 dc->desc = "PowerNV Chip POWER8"; 1585 1586 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1587 &k->parent_realize); 1588 } 1589 1590 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1591 { 1592 DeviceClass *dc = DEVICE_CLASS(klass); 1593 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1594 1595 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1596 k->cores_mask = POWER8_CORE_MASK; 1597 k->num_phbs = 4; 1598 k->get_pir_tir = pnv_get_pir_tir_p8; 1599 k->intc_create = pnv_chip_power8_intc_create; 1600 k->intc_reset = pnv_chip_power8_intc_reset; 1601 k->intc_destroy = pnv_chip_power8_intc_destroy; 1602 k->intc_print_info = pnv_chip_power8_intc_print_info; 1603 k->isa_create = pnv_chip_power8nvl_isa_create; 1604 k->dt_populate = pnv_chip_power8_dt_populate; 1605 k->pic_print_info = pnv_chip_power8_pic_print_info; 1606 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1607 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1608 dc->desc = "PowerNV Chip POWER8NVL"; 1609 1610 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1611 &k->parent_realize); 1612 } 1613 1614 static void pnv_chip_power9_instance_init(Object *obj) 1615 { 1616 PnvChip *chip = PNV_CHIP(obj); 1617 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1618 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1619 int i; 1620 1621 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1622 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1623 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1624 "xive-fabric"); 1625 1626 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1627 1628 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1629 1630 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1631 1632 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1633 1634 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1635 1636 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1637 1638 /* Number of PECs is the chip default */ 1639 chip->num_pecs = pcc->num_pecs; 1640 1641 for (i = 0; i < chip->num_pecs; i++) { 1642 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1643 TYPE_PNV_PHB4_PEC); 1644 } 1645 1646 for (i = 0; i < pcc->i2c_num_engines; i++) { 1647 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1648 } 1649 } 1650 1651 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1652 PnvCore *pnv_core, 1653 const char *type) 1654 { 1655 char eq_name[32]; 1656 int core_id = CPU_CORE(pnv_core)->core_id; 1657 1658 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1659 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1660 sizeof(*eq), type, 1661 &error_fatal, NULL); 1662 1663 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1664 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1665 } 1666 1667 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1668 { 1669 PnvChip *chip = PNV_CHIP(chip9); 1670 int i; 1671 1672 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1673 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1674 1675 for (i = 0; i < chip9->nr_quads; i++) { 1676 PnvQuad *eq = &chip9->quads[i]; 1677 1678 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1679 PNV_QUAD_TYPE_NAME("power9")); 1680 1681 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1682 &eq->xscom_regs); 1683 } 1684 } 1685 1686 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1687 { 1688 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1689 int i; 1690 1691 for (i = 0; i < chip->num_pecs; i++) { 1692 PnvPhb4PecState *pec = &chip9->pecs[i]; 1693 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1694 uint32_t pec_nest_base; 1695 uint32_t pec_pci_base; 1696 1697 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1698 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1699 &error_fatal); 1700 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1701 &error_fatal); 1702 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1703 return; 1704 } 1705 1706 pec_nest_base = pecc->xscom_nest_base(pec); 1707 pec_pci_base = pecc->xscom_pci_base(pec); 1708 1709 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1710 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1711 } 1712 } 1713 1714 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1715 { 1716 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1717 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1718 PnvChip *chip = PNV_CHIP(dev); 1719 Pnv9Psi *psi9 = &chip9->psi; 1720 Error *local_err = NULL; 1721 int i; 1722 1723 /* XSCOM bridge is first */ 1724 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1725 1726 pcc->parent_realize(dev, &local_err); 1727 if (local_err) { 1728 error_propagate(errp, local_err); 1729 return; 1730 } 1731 1732 /* ADU */ 1733 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), 1734 &error_abort); 1735 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1736 return; 1737 } 1738 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 1739 &chip9->adu.xscom_regs); 1740 1741 pnv_chip_quad_realize(chip9, &local_err); 1742 if (local_err) { 1743 error_propagate(errp, local_err); 1744 return; 1745 } 1746 1747 /* XIVE interrupt controller (POWER9) */ 1748 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1749 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1750 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1751 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1752 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1753 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1754 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1755 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1756 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1757 &error_abort); 1758 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1759 return; 1760 } 1761 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1762 &chip9->xive.xscom_regs); 1763 1764 /* Processor Service Interface (PSI) Host Bridge */ 1765 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1766 &error_fatal); 1767 /* This is the only device with 4k ESB pages */ 1768 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1769 &error_fatal); 1770 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1771 return; 1772 } 1773 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1774 &PNV_PSI(psi9)->xscom_regs); 1775 1776 /* LPC */ 1777 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1778 return; 1779 } 1780 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1781 &chip9->lpc.xscom_regs); 1782 1783 chip->fw_mr = &chip9->lpc.isa_fw; 1784 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1785 (uint64_t) PNV9_LPCM_BASE(chip)); 1786 1787 /* ChipTOD */ 1788 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1789 chip->chip_id == 0, &error_abort); 1790 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1791 chip->chip_id == 1, &error_abort); 1792 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1793 &error_abort); 1794 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1795 return; 1796 } 1797 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1798 &chip9->chiptod.xscom_regs); 1799 1800 /* Create the simplified OCC model */ 1801 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1802 return; 1803 } 1804 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1805 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1806 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1807 1808 /* OCC SRAM model */ 1809 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1810 &chip9->occ.sram_regs); 1811 1812 /* SBE */ 1813 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1814 return; 1815 } 1816 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1817 &chip9->sbe.xscom_ctrl_regs); 1818 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1819 &chip9->sbe.xscom_mbox_regs); 1820 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1821 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1822 1823 /* HOMER */ 1824 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1825 &error_abort); 1826 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1827 return; 1828 } 1829 /* Homer Xscom region */ 1830 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1831 1832 /* Homer mmio region */ 1833 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1834 &chip9->homer.regs); 1835 1836 /* PEC PHBs */ 1837 pnv_chip_power9_pec_realize(chip, &local_err); 1838 if (local_err) { 1839 error_propagate(errp, local_err); 1840 return; 1841 } 1842 1843 /* 1844 * I2C 1845 */ 1846 for (i = 0; i < pcc->i2c_num_engines; i++) { 1847 Object *obj = OBJECT(&chip9->i2c[i]); 1848 1849 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1850 object_property_set_int(obj, "num-busses", 1851 pcc->i2c_ports_per_engine[i], 1852 &error_fatal); 1853 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1854 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1855 return; 1856 } 1857 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1858 (chip9->i2c[i].engine - 1) * 1859 PNV9_XSCOM_I2CM_SIZE, 1860 &chip9->i2c[i].xscom_regs); 1861 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1862 qdev_get_gpio_in(DEVICE(psi9), 1863 PSIHB9_IRQ_SBE_I2C)); 1864 } 1865 } 1866 1867 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1868 { 1869 addr &= (PNV9_XSCOM_SIZE - 1); 1870 return addr >> 3; 1871 } 1872 1873 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1874 { 1875 DeviceClass *dc = DEVICE_CLASS(klass); 1876 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1877 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1878 1879 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1880 k->cores_mask = POWER9_CORE_MASK; 1881 k->get_pir_tir = pnv_get_pir_tir_p9; 1882 k->intc_create = pnv_chip_power9_intc_create; 1883 k->intc_reset = pnv_chip_power9_intc_reset; 1884 k->intc_destroy = pnv_chip_power9_intc_destroy; 1885 k->intc_print_info = pnv_chip_power9_intc_print_info; 1886 k->isa_create = pnv_chip_power9_isa_create; 1887 k->dt_populate = pnv_chip_power9_dt_populate; 1888 k->pic_print_info = pnv_chip_power9_pic_print_info; 1889 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1890 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1891 dc->desc = "PowerNV Chip POWER9"; 1892 k->num_pecs = PNV9_CHIP_MAX_PEC; 1893 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1894 k->i2c_ports_per_engine = i2c_ports_per_engine; 1895 1896 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1897 &k->parent_realize); 1898 } 1899 1900 static void pnv_chip_power10_instance_init(Object *obj) 1901 { 1902 PnvChip *chip = PNV_CHIP(obj); 1903 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1904 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1905 int i; 1906 1907 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 1908 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1909 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1910 "xive-fabric"); 1911 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1912 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1913 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1914 TYPE_PNV10_CHIPTOD); 1915 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1916 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1917 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1918 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1919 TYPE_PNV_N1_CHIPLET); 1920 1921 chip->num_pecs = pcc->num_pecs; 1922 1923 for (i = 0; i < chip->num_pecs; i++) { 1924 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1925 TYPE_PNV_PHB5_PEC); 1926 } 1927 1928 for (i = 0; i < pcc->i2c_num_engines; i++) { 1929 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1930 } 1931 } 1932 1933 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1934 { 1935 PnvChip *chip = PNV_CHIP(chip10); 1936 int i; 1937 1938 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1939 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1940 1941 for (i = 0; i < chip10->nr_quads; i++) { 1942 PnvQuad *eq = &chip10->quads[i]; 1943 1944 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1945 PNV_QUAD_TYPE_NAME("power10")); 1946 1947 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1948 &eq->xscom_regs); 1949 1950 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1951 &eq->xscom_qme_regs); 1952 } 1953 } 1954 1955 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1956 { 1957 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1958 int i; 1959 1960 for (i = 0; i < chip->num_pecs; i++) { 1961 PnvPhb4PecState *pec = &chip10->pecs[i]; 1962 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1963 uint32_t pec_nest_base; 1964 uint32_t pec_pci_base; 1965 1966 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1967 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1968 &error_fatal); 1969 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1970 &error_fatal); 1971 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1972 return; 1973 } 1974 1975 pec_nest_base = pecc->xscom_nest_base(pec); 1976 pec_pci_base = pecc->xscom_pci_base(pec); 1977 1978 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1979 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1980 } 1981 } 1982 1983 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1984 { 1985 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1986 PnvChip *chip = PNV_CHIP(dev); 1987 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1988 Error *local_err = NULL; 1989 int i; 1990 1991 /* XSCOM bridge is first */ 1992 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1993 1994 pcc->parent_realize(dev, &local_err); 1995 if (local_err) { 1996 error_propagate(errp, local_err); 1997 return; 1998 } 1999 2000 /* ADU */ 2001 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), 2002 &error_abort); 2003 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 2004 return; 2005 } 2006 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 2007 &chip10->adu.xscom_regs); 2008 2009 pnv_chip_power10_quad_realize(chip10, &local_err); 2010 if (local_err) { 2011 error_propagate(errp, local_err); 2012 return; 2013 } 2014 2015 /* XIVE2 interrupt controller (POWER10) */ 2016 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 2017 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 2018 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 2019 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 2020 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 2021 PNV10_XIVE2_END_BASE(chip), &error_fatal); 2022 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 2023 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 2024 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 2025 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 2026 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 2027 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 2028 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 2029 &error_abort); 2030 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 2031 return; 2032 } 2033 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 2034 &chip10->xive.xscom_regs); 2035 2036 /* Processor Service Interface (PSI) Host Bridge */ 2037 object_property_set_int(OBJECT(&chip10->psi), "bar", 2038 PNV10_PSIHB_BASE(chip), &error_fatal); 2039 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 2040 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 2041 &error_fatal); 2042 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 2043 return; 2044 } 2045 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 2046 &PNV_PSI(&chip10->psi)->xscom_regs); 2047 2048 /* LPC */ 2049 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 2050 return; 2051 } 2052 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 2053 &chip10->lpc.xscom_regs); 2054 2055 chip->fw_mr = &chip10->lpc.isa_fw; 2056 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2057 (uint64_t) PNV10_LPCM_BASE(chip)); 2058 2059 /* ChipTOD */ 2060 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 2061 chip->chip_id == 0, &error_abort); 2062 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 2063 chip->chip_id == 1, &error_abort); 2064 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 2065 &error_abort); 2066 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 2067 return; 2068 } 2069 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 2070 &chip10->chiptod.xscom_regs); 2071 2072 /* Create the simplified OCC model */ 2073 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2074 return; 2075 } 2076 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2077 &chip10->occ.xscom_regs); 2078 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2079 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2080 2081 /* OCC SRAM model */ 2082 memory_region_add_subregion(get_system_memory(), 2083 PNV10_OCC_SENSOR_BASE(chip), 2084 &chip10->occ.sram_regs); 2085 2086 /* SBE */ 2087 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2088 return; 2089 } 2090 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2091 &chip10->sbe.xscom_ctrl_regs); 2092 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2093 &chip10->sbe.xscom_mbox_regs); 2094 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2095 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2096 2097 /* HOMER */ 2098 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2099 &error_abort); 2100 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2101 return; 2102 } 2103 /* Homer Xscom region */ 2104 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2105 &chip10->homer.pba_regs); 2106 2107 /* Homer mmio region */ 2108 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2109 &chip10->homer.regs); 2110 2111 /* N1 chiplet */ 2112 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2113 return; 2114 } 2115 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2116 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2117 2118 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2119 &chip10->n1_chiplet.xscom_pb_eq_mr); 2120 2121 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2122 &chip10->n1_chiplet.xscom_pb_es_mr); 2123 2124 /* PHBs */ 2125 pnv_chip_power10_phb_realize(chip, &local_err); 2126 if (local_err) { 2127 error_propagate(errp, local_err); 2128 return; 2129 } 2130 2131 2132 /* 2133 * I2C 2134 */ 2135 for (i = 0; i < pcc->i2c_num_engines; i++) { 2136 Object *obj = OBJECT(&chip10->i2c[i]); 2137 2138 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2139 object_property_set_int(obj, "num-busses", 2140 pcc->i2c_ports_per_engine[i], 2141 &error_fatal); 2142 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2143 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2144 return; 2145 } 2146 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2147 (chip10->i2c[i].engine - 1) * 2148 PNV10_XSCOM_I2CM_SIZE, 2149 &chip10->i2c[i].xscom_regs); 2150 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2151 qdev_get_gpio_in(DEVICE(&chip10->psi), 2152 PSIHB9_IRQ_SBE_I2C)); 2153 } 2154 2155 } 2156 2157 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2158 { 2159 int i; 2160 for (i = 0; i < pnv->num_chips; i++) { 2161 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2162 2163 /* 2164 * Add a PCA9552 I2C device for PCIe hotplug control 2165 * to engine 2, bus 1, address 0x63 2166 */ 2167 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2168 "pca9552", 0x63); 2169 2170 /* 2171 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2172 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2173 * after hypervisor code sets a SLOTx_EN pin high. 2174 */ 2175 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2176 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2177 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2178 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2179 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2180 2181 /* 2182 * Add a PCA9554 I2C device for cable card presence detection 2183 * to engine 2, bus 1, address 0x25 2184 */ 2185 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2186 } 2187 } 2188 2189 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2190 { 2191 addr &= (PNV10_XSCOM_SIZE - 1); 2192 return addr >> 3; 2193 } 2194 2195 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2196 { 2197 DeviceClass *dc = DEVICE_CLASS(klass); 2198 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2199 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2200 2201 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2202 k->cores_mask = POWER10_CORE_MASK; 2203 k->get_pir_tir = pnv_get_pir_tir_p10; 2204 k->intc_create = pnv_chip_power10_intc_create; 2205 k->intc_reset = pnv_chip_power10_intc_reset; 2206 k->intc_destroy = pnv_chip_power10_intc_destroy; 2207 k->intc_print_info = pnv_chip_power10_intc_print_info; 2208 k->isa_create = pnv_chip_power10_isa_create; 2209 k->dt_populate = pnv_chip_power10_dt_populate; 2210 k->pic_print_info = pnv_chip_power10_pic_print_info; 2211 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2212 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2213 dc->desc = "PowerNV Chip POWER10"; 2214 k->num_pecs = PNV10_CHIP_MAX_PEC; 2215 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2216 k->i2c_ports_per_engine = i2c_ports_per_engine; 2217 2218 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2219 &k->parent_realize); 2220 } 2221 2222 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, 2223 Error **errp) 2224 { 2225 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2226 int cores_max; 2227 2228 /* 2229 * No custom mask for this chip, let's use the default one from * 2230 * the chip class 2231 */ 2232 if (!chip->cores_mask) { 2233 chip->cores_mask = pcc->cores_mask; 2234 } 2235 2236 /* filter alien core ids ! some are reserved */ 2237 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2238 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2239 chip->cores_mask); 2240 return; 2241 } 2242 chip->cores_mask &= pcc->cores_mask; 2243 2244 /* Ensure small-cores a paired up in big-core mode */ 2245 if (pnv->big_core) { 2246 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; 2247 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; 2248 2249 if (even_cores ^ (odd_cores >> 1)) { 2250 error_setg(errp, "warning: unpaired cores in big-core mode !"); 2251 return; 2252 } 2253 } 2254 2255 /* now that we have a sane layout, let check the number of cores */ 2256 cores_max = ctpop64(chip->cores_mask); 2257 if (chip->nr_cores > cores_max) { 2258 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2259 cores_max); 2260 return; 2261 } 2262 } 2263 2264 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2265 { 2266 Error *error = NULL; 2267 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2268 const char *typename = pnv_chip_core_typename(chip); 2269 int i, core_hwid; 2270 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2271 2272 if (!object_class_by_name(typename)) { 2273 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2274 return; 2275 } 2276 2277 /* Cores */ 2278 pnv_chip_core_sanitize(pnv, chip, &error); 2279 if (error) { 2280 error_propagate(errp, error); 2281 return; 2282 } 2283 2284 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2285 2286 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2287 && (i < chip->nr_cores); core_hwid++) { 2288 char core_name[32]; 2289 PnvCore *pnv_core; 2290 uint64_t xscom_core_base; 2291 2292 if (!(chip->cores_mask & (1ull << core_hwid))) { 2293 continue; 2294 } 2295 2296 pnv_core = PNV_CORE(object_new(typename)); 2297 2298 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2299 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2300 chip->cores[i] = pnv_core; 2301 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2302 chip->nr_threads, &error_fatal); 2303 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2304 core_hwid, &error_fatal); 2305 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2306 &error_fatal); 2307 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2308 &error_fatal); 2309 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, 2310 &error_fatal); 2311 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2312 &error_abort); 2313 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2314 2315 /* Each core has an XSCOM MMIO region */ 2316 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2317 2318 pnv_xscom_add_subregion(chip, xscom_core_base, 2319 &pnv_core->xscom_regs); 2320 i++; 2321 } 2322 } 2323 2324 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2325 { 2326 PnvChip *chip = PNV_CHIP(dev); 2327 Error *error = NULL; 2328 2329 /* Cores */ 2330 pnv_chip_core_realize(chip, &error); 2331 if (error) { 2332 error_propagate(errp, error); 2333 return; 2334 } 2335 } 2336 2337 static Property pnv_chip_properties[] = { 2338 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2339 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2340 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2341 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2342 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2343 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2344 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false), 2345 DEFINE_PROP_END_OF_LIST(), 2346 }; 2347 2348 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2349 { 2350 DeviceClass *dc = DEVICE_CLASS(klass); 2351 2352 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2353 dc->realize = pnv_chip_realize; 2354 device_class_set_props(dc, pnv_chip_properties); 2355 dc->desc = "PowerNV Chip"; 2356 } 2357 2358 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2359 { 2360 int i; 2361 2362 for (i = 0; i < chip->nr_cores; i++) { 2363 PnvCore *pc = chip->cores[i]; 2364 CPUCore *cc = CPU_CORE(pc); 2365 2366 if (cc->core_id == core_id) { 2367 return pc; 2368 } 2369 } 2370 return NULL; 2371 } 2372 2373 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2374 { 2375 int i, j; 2376 2377 for (i = 0; i < chip->nr_cores; i++) { 2378 PnvCore *pc = chip->cores[i]; 2379 CPUCore *cc = CPU_CORE(pc); 2380 2381 for (j = 0; j < cc->nr_threads; j++) { 2382 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2383 return pc->threads[j]; 2384 } 2385 } 2386 } 2387 return NULL; 2388 } 2389 2390 static void pnv_chip_foreach_cpu(PnvChip *chip, 2391 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 2392 void *opaque) 2393 { 2394 int i, j; 2395 2396 for (i = 0; i < chip->nr_cores; i++) { 2397 PnvCore *pc = chip->cores[i]; 2398 2399 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 2400 fn(chip, pc->threads[j], opaque); 2401 } 2402 } 2403 } 2404 2405 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2406 { 2407 PnvMachineState *pnv = PNV_MACHINE(xi); 2408 int i, j; 2409 2410 for (i = 0; i < pnv->num_chips; i++) { 2411 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2412 2413 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2414 return &chip8->psi.ics; 2415 } 2416 2417 for (j = 0; j < chip8->num_phbs; j++) { 2418 PnvPHB *phb = chip8->phbs[j]; 2419 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2420 2421 if (ics_valid_irq(&phb3->lsis, irq)) { 2422 return &phb3->lsis; 2423 } 2424 2425 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2426 return ICS(&phb3->msis); 2427 } 2428 } 2429 } 2430 return NULL; 2431 } 2432 2433 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2434 { 2435 int i; 2436 2437 for (i = 0; i < pnv->num_chips; i++) { 2438 PnvChip *chip = pnv->chips[i]; 2439 if (chip->chip_id == chip_id) { 2440 return chip; 2441 } 2442 } 2443 return NULL; 2444 } 2445 2446 static void pnv_ics_resend(XICSFabric *xi) 2447 { 2448 PnvMachineState *pnv = PNV_MACHINE(xi); 2449 int i, j; 2450 2451 for (i = 0; i < pnv->num_chips; i++) { 2452 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2453 2454 ics_resend(&chip8->psi.ics); 2455 2456 for (j = 0; j < chip8->num_phbs; j++) { 2457 PnvPHB *phb = chip8->phbs[j]; 2458 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2459 2460 ics_resend(&phb3->lsis); 2461 ics_resend(ICS(&phb3->msis)); 2462 } 2463 } 2464 } 2465 2466 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2467 { 2468 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2469 2470 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2471 } 2472 2473 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 2474 void *opaque) 2475 { 2476 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 2477 } 2478 2479 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 2480 { 2481 PnvMachineState *pnv = PNV_MACHINE(obj); 2482 int i; 2483 2484 for (i = 0; i < pnv->num_chips; i++) { 2485 PnvChip *chip = pnv->chips[i]; 2486 2487 /* First CPU presenters */ 2488 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 2489 2490 /* Then other devices, PHB, PSI, XIVE */ 2491 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 2492 } 2493 } 2494 2495 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2496 uint8_t nvt_blk, uint32_t nvt_idx, 2497 bool cam_ignore, uint8_t priority, 2498 uint32_t logic_serv, 2499 XiveTCTXMatch *match) 2500 { 2501 PnvMachineState *pnv = PNV_MACHINE(xfb); 2502 int total_count = 0; 2503 int i; 2504 2505 for (i = 0; i < pnv->num_chips; i++) { 2506 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2507 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2508 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2509 int count; 2510 2511 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2512 priority, logic_serv, match); 2513 2514 if (count < 0) { 2515 return count; 2516 } 2517 2518 total_count += count; 2519 } 2520 2521 return total_count; 2522 } 2523 2524 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2525 uint8_t nvt_blk, uint32_t nvt_idx, 2526 bool cam_ignore, uint8_t priority, 2527 uint32_t logic_serv, 2528 XiveTCTXMatch *match) 2529 { 2530 PnvMachineState *pnv = PNV_MACHINE(xfb); 2531 int total_count = 0; 2532 int i; 2533 2534 for (i = 0; i < pnv->num_chips; i++) { 2535 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2536 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2537 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2538 int count; 2539 2540 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2541 priority, logic_serv, match); 2542 2543 if (count < 0) { 2544 return count; 2545 } 2546 2547 total_count += count; 2548 } 2549 2550 return total_count; 2551 } 2552 2553 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2554 { 2555 MachineClass *mc = MACHINE_CLASS(oc); 2556 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2557 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2558 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2559 2560 static GlobalProperty phb_compat[] = { 2561 { TYPE_PNV_PHB, "version", "3" }, 2562 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2563 }; 2564 2565 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2566 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2567 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2568 2569 xic->icp_get = pnv_icp_get; 2570 xic->ics_get = pnv_ics_get; 2571 xic->ics_resend = pnv_ics_resend; 2572 2573 pmc->compat = compat; 2574 pmc->compat_size = sizeof(compat); 2575 pmc->max_smt_threads = 8; 2576 2577 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2578 } 2579 2580 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2581 { 2582 MachineClass *mc = MACHINE_CLASS(oc); 2583 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2584 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2585 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2586 2587 static GlobalProperty phb_compat[] = { 2588 { TYPE_PNV_PHB, "version", "4" }, 2589 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2590 }; 2591 2592 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2593 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2594 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2595 2596 xfc->match_nvt = pnv_match_nvt; 2597 2598 pmc->compat = compat; 2599 pmc->compat_size = sizeof(compat); 2600 pmc->max_smt_threads = 4; 2601 pmc->dt_power_mgt = pnv_dt_power_mgt; 2602 2603 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2604 } 2605 2606 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2607 { 2608 MachineClass *mc = MACHINE_CLASS(oc); 2609 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2610 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2611 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2612 2613 static GlobalProperty phb_compat[] = { 2614 { TYPE_PNV_PHB, "version", "5" }, 2615 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2616 }; 2617 2618 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2619 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2620 2621 mc->alias = "powernv"; 2622 2623 pmc->compat = compat; 2624 pmc->compat_size = sizeof(compat); 2625 pmc->max_smt_threads = 4; 2626 pmc->dt_power_mgt = pnv_dt_power_mgt; 2627 2628 xfc->match_nvt = pnv10_xive_match_nvt; 2629 2630 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2631 } 2632 2633 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2634 { 2635 MachineClass *mc = MACHINE_CLASS(oc); 2636 2637 pnv_machine_p10_common_class_init(oc, data); 2638 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2639 } 2640 2641 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2642 { 2643 MachineClass *mc = MACHINE_CLASS(oc); 2644 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2645 2646 pnv_machine_p10_common_class_init(oc, data); 2647 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2648 pmc->i2c_init = pnv_rainier_i2c_init; 2649 } 2650 2651 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2652 { 2653 PnvMachineState *pnv = PNV_MACHINE(obj); 2654 2655 return !!pnv->fw_load_addr; 2656 } 2657 2658 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2659 { 2660 PnvMachineState *pnv = PNV_MACHINE(obj); 2661 2662 if (value) { 2663 pnv->fw_load_addr = 0x8000000; 2664 } 2665 } 2666 2667 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2668 { 2669 CPUPPCState *env = cpu_env(cs); 2670 2671 cpu_synchronize_state(cs); 2672 ppc_cpu_do_system_reset(cs); 2673 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2674 /* 2675 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2676 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2677 * (PPC_BIT(43)). 2678 */ 2679 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2680 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2681 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2682 } 2683 } else { 2684 /* 2685 * For non-powersave system resets, SRR1[42:45] are defined to be 2686 * implementation-dependent. The POWER9 User Manual specifies that 2687 * an external (SCOM driven, which may come from a BMC nmi command or 2688 * another CPU requesting a NMI IPI) system reset exception should be 2689 * 0b0010 (PPC_BIT(44)). 2690 */ 2691 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2692 } 2693 } 2694 2695 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 2696 { 2697 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2698 } 2699 2700 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2701 { 2702 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2703 int i; 2704 2705 for (i = 0; i < pnv->num_chips; i++) { 2706 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 2707 } 2708 } 2709 2710 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2711 { 2712 MachineClass *mc = MACHINE_CLASS(oc); 2713 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2714 NMIClass *nc = NMI_CLASS(oc); 2715 2716 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2717 mc->init = pnv_init; 2718 mc->reset = pnv_reset; 2719 mc->max_cpus = MAX_CPUS; 2720 /* Pnv provides a AHCI device for storage */ 2721 mc->block_default_type = IF_IDE; 2722 mc->no_parallel = 1; 2723 mc->default_boot_order = NULL; 2724 /* 2725 * RAM defaults to less than 2048 for 32-bit hosts, and large 2726 * enough to fit the maximum initrd size at it's load address 2727 */ 2728 mc->default_ram_size = 1 * GiB; 2729 mc->default_ram_id = "pnv.ram"; 2730 ispc->print_info = pnv_pic_print_info; 2731 nc->nmi_monitor_handler = pnv_nmi; 2732 2733 object_class_property_add_bool(oc, "hb-mode", 2734 pnv_machine_get_hb, pnv_machine_set_hb); 2735 object_class_property_set_description(oc, "hb-mode", 2736 "Use a hostboot like boot loader"); 2737 } 2738 2739 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2740 { \ 2741 .name = type, \ 2742 .class_init = class_initfn, \ 2743 .parent = TYPE_PNV8_CHIP, \ 2744 } 2745 2746 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2747 { \ 2748 .name = type, \ 2749 .class_init = class_initfn, \ 2750 .parent = TYPE_PNV9_CHIP, \ 2751 } 2752 2753 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2754 { \ 2755 .name = type, \ 2756 .class_init = class_initfn, \ 2757 .parent = TYPE_PNV10_CHIP, \ 2758 } 2759 2760 static const TypeInfo types[] = { 2761 { 2762 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2763 .parent = MACHINE_TYPE_NAME("powernv10"), 2764 .class_init = pnv_machine_p10_rainier_class_init, 2765 }, 2766 { 2767 .name = MACHINE_TYPE_NAME("powernv10"), 2768 .parent = TYPE_PNV_MACHINE, 2769 .class_init = pnv_machine_power10_class_init, 2770 .interfaces = (InterfaceInfo[]) { 2771 { TYPE_XIVE_FABRIC }, 2772 { }, 2773 }, 2774 }, 2775 { 2776 .name = MACHINE_TYPE_NAME("powernv9"), 2777 .parent = TYPE_PNV_MACHINE, 2778 .class_init = pnv_machine_power9_class_init, 2779 .interfaces = (InterfaceInfo[]) { 2780 { TYPE_XIVE_FABRIC }, 2781 { }, 2782 }, 2783 }, 2784 { 2785 .name = MACHINE_TYPE_NAME("powernv8"), 2786 .parent = TYPE_PNV_MACHINE, 2787 .class_init = pnv_machine_power8_class_init, 2788 .interfaces = (InterfaceInfo[]) { 2789 { TYPE_XICS_FABRIC }, 2790 { }, 2791 }, 2792 }, 2793 { 2794 .name = TYPE_PNV_MACHINE, 2795 .parent = TYPE_MACHINE, 2796 .abstract = true, 2797 .instance_size = sizeof(PnvMachineState), 2798 .class_init = pnv_machine_class_init, 2799 .class_size = sizeof(PnvMachineClass), 2800 .interfaces = (InterfaceInfo[]) { 2801 { TYPE_INTERRUPT_STATS_PROVIDER }, 2802 { TYPE_NMI }, 2803 { }, 2804 }, 2805 }, 2806 { 2807 .name = TYPE_PNV_CHIP, 2808 .parent = TYPE_SYS_BUS_DEVICE, 2809 .class_init = pnv_chip_class_init, 2810 .instance_size = sizeof(PnvChip), 2811 .class_size = sizeof(PnvChipClass), 2812 .abstract = true, 2813 }, 2814 2815 /* 2816 * P10 chip and variants 2817 */ 2818 { 2819 .name = TYPE_PNV10_CHIP, 2820 .parent = TYPE_PNV_CHIP, 2821 .instance_init = pnv_chip_power10_instance_init, 2822 .instance_size = sizeof(Pnv10Chip), 2823 }, 2824 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2825 2826 /* 2827 * P9 chip and variants 2828 */ 2829 { 2830 .name = TYPE_PNV9_CHIP, 2831 .parent = TYPE_PNV_CHIP, 2832 .instance_init = pnv_chip_power9_instance_init, 2833 .instance_size = sizeof(Pnv9Chip), 2834 }, 2835 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2836 2837 /* 2838 * P8 chip and variants 2839 */ 2840 { 2841 .name = TYPE_PNV8_CHIP, 2842 .parent = TYPE_PNV_CHIP, 2843 .instance_init = pnv_chip_power8_instance_init, 2844 .instance_size = sizeof(Pnv8Chip), 2845 }, 2846 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2847 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2848 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2849 pnv_chip_power8nvl_class_init), 2850 }; 2851 2852 DEFINE_TYPES(types) 2853