1 /* 2 * QEMU PowerPC CHRP (Genesi/bPlan Pegasos II) hardware System Emulator 3 * 4 * Copyright (c) 2018-2021 BALATON Zoltan 5 * 6 * This work is licensed under the GNU GPL license version 2 or later. 7 * 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu-common.h" 12 #include "qemu/units.h" 13 #include "qapi/error.h" 14 #include "hw/hw.h" 15 #include "hw/ppc/ppc.h" 16 #include "hw/sysbus.h" 17 #include "hw/pci/pci_host.h" 18 #include "hw/irq.h" 19 #include "hw/pci-host/mv64361.h" 20 #include "hw/isa/vt82c686.h" 21 #include "hw/ide/pci.h" 22 #include "hw/i2c/smbus_eeprom.h" 23 #include "hw/qdev-properties.h" 24 #include "sysemu/reset.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/fw-path-provider.h" 28 #include "elf.h" 29 #include "qemu/log.h" 30 #include "qemu/error-report.h" 31 #include "sysemu/kvm.h" 32 #include "kvm_ppc.h" 33 #include "exec/address-spaces.h" 34 #include "qom/qom-qobject.h" 35 #include "qapi/qmp/qdict.h" 36 #include "trace.h" 37 #include "qemu/datadir.h" 38 #include "sysemu/device_tree.h" 39 #include "hw/ppc/vof.h" 40 41 #include <libfdt.h> 42 43 #define PROM_FILENAME "vof.bin" 44 #define PROM_ADDR 0xfff00000 45 #define PROM_SIZE 0x80000 46 47 #define KVMPPC_HCALL_BASE 0xf000 48 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 49 #define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 50 51 #define H_SUCCESS 0 52 #define H_PRIVILEGE -3 /* Caller not privileged */ 53 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 54 55 #define BUS_FREQ_HZ 133333333 56 57 #define PCI0_CFG_ADDR 0xcf8 58 #define PCI0_MEM_BASE 0xc0000000 59 #define PCI0_MEM_SIZE 0x20000000 60 #define PCI0_IO_BASE 0xf8000000 61 #define PCI0_IO_SIZE 0x10000 62 63 #define PCI1_CFG_ADDR 0xc78 64 #define PCI1_MEM_BASE 0x80000000 65 #define PCI1_MEM_SIZE 0x40000000 66 #define PCI1_IO_BASE 0xfe000000 67 #define PCI1_IO_SIZE 0x10000 68 69 #define TYPE_PEGASOS2_MACHINE MACHINE_TYPE_NAME("pegasos2") 70 OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE) 71 72 struct Pegasos2MachineState { 73 MachineState parent_obj; 74 PowerPCCPU *cpu; 75 DeviceState *mv; 76 Vof *vof; 77 void *fdt_blob; 78 uint64_t kernel_addr; 79 uint64_t kernel_entry; 80 uint64_t kernel_size; 81 }; 82 83 static void *build_fdt(MachineState *machine, int *fdt_size); 84 85 static void pegasos2_cpu_reset(void *opaque) 86 { 87 PowerPCCPU *cpu = opaque; 88 Pegasos2MachineState *pm = PEGASOS2_MACHINE(current_machine); 89 90 cpu_reset(CPU(cpu)); 91 cpu->env.spr[SPR_HID1] = 7ULL << 28; 92 if (pm->vof) { 93 cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20; 94 cpu->env.nip = 0x100; 95 } 96 } 97 98 static void pegasos2_init(MachineState *machine) 99 { 100 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 101 CPUPPCState *env; 102 MemoryRegion *rom = g_new(MemoryRegion, 1); 103 PCIBus *pci_bus; 104 PCIDevice *dev; 105 I2CBus *i2c_bus; 106 const char *fwname = machine->firmware ?: PROM_FILENAME; 107 char *filename; 108 int sz; 109 uint8_t *spd_data; 110 111 /* init CPU */ 112 pm->cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 113 env = &pm->cpu->env; 114 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 115 error_report("Incompatible CPU, only 6xx bus supported"); 116 exit(1); 117 } 118 119 /* Set time-base frequency */ 120 cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4); 121 qemu_register_reset(pegasos2_cpu_reset, pm->cpu); 122 123 /* RAM */ 124 if (machine->ram_size > 2 * GiB) { 125 error_report("RAM size more than 2 GiB is not supported"); 126 exit(1); 127 } 128 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 129 130 /* allocate and load firmware */ 131 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname); 132 if (!filename) { 133 error_report("Could not find firmware '%s'", fwname); 134 exit(1); 135 } 136 if (!machine->firmware && !pm->vof) { 137 pm->vof = g_malloc0(sizeof(*pm->vof)); 138 } 139 memory_region_init_rom(rom, NULL, "pegasos2.rom", PROM_SIZE, &error_fatal); 140 memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom); 141 sz = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL, 1, 142 PPC_ELF_MACHINE, 0, 0); 143 if (sz <= 0) { 144 sz = load_image_targphys(filename, pm->vof ? 0 : PROM_ADDR, PROM_SIZE); 145 } 146 if (sz <= 0 || sz > PROM_SIZE) { 147 error_report("Could not load firmware '%s'", filename); 148 exit(1); 149 } 150 g_free(filename); 151 if (pm->vof) { 152 pm->vof->fw_size = sz; 153 } 154 155 /* Marvell Discovery II system controller */ 156 pm->mv = DEVICE(sysbus_create_simple(TYPE_MV64361, -1, 157 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT])); 158 pci_bus = mv64361_get_pci_bus(pm->mv, 1); 159 160 /* VIA VT8231 South Bridge (multifunction PCI device) */ 161 /* VT8231 function 0: PCI-to-ISA Bridge */ 162 dev = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, 0), true, 163 TYPE_VT8231_ISA); 164 qdev_connect_gpio_out(DEVICE(dev), 0, 165 qdev_get_gpio_in_named(pm->mv, "gpp", 31)); 166 167 /* VT8231 function 1: IDE Controller */ 168 dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 1), "via-ide"); 169 pci_ide_create_devs(dev); 170 171 /* VT8231 function 2-3: USB Ports */ 172 pci_create_simple(pci_bus, PCI_DEVFN(12, 2), "vt82c686b-usb-uhci"); 173 pci_create_simple(pci_bus, PCI_DEVFN(12, 3), "vt82c686b-usb-uhci"); 174 175 /* VT8231 function 4: Power Management Controller */ 176 dev = pci_create_simple(pci_bus, PCI_DEVFN(12, 4), TYPE_VT8231_PM); 177 i2c_bus = I2C_BUS(qdev_get_child_bus(DEVICE(dev), "i2c")); 178 spd_data = spd_data_generate(DDR, machine->ram_size); 179 smbus_eeprom_init_one(i2c_bus, 0x57, spd_data); 180 181 /* VT8231 function 5-6: AC97 Audio & Modem */ 182 pci_create_simple(pci_bus, PCI_DEVFN(12, 5), TYPE_VIA_AC97); 183 pci_create_simple(pci_bus, PCI_DEVFN(12, 6), TYPE_VIA_MC97); 184 185 /* other PC hardware */ 186 pci_vga_init(pci_bus); 187 188 if (machine->kernel_filename) { 189 sz = load_elf(machine->kernel_filename, NULL, NULL, NULL, 190 &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1, 191 PPC_ELF_MACHINE, 0, 0); 192 if (sz <= 0) { 193 error_report("Could not load kernel '%s'", 194 machine->kernel_filename); 195 exit(1); 196 } 197 pm->kernel_size = sz; 198 if (!pm->vof) { 199 warn_report("Option -kernel may be ineffective with -bios."); 200 } 201 } else if (pm->vof) { 202 warn_report("Using Virtual OpenFirmware but no -kernel option."); 203 } 204 205 if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) { 206 warn_report("Option -append may be ineffective with -bios."); 207 } 208 } 209 210 static uint32_t pegasos2_mv_reg_read(Pegasos2MachineState *pm, 211 uint32_t addr, uint32_t len) 212 { 213 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); 214 uint64_t val = 0xffffffffULL; 215 memory_region_dispatch_read(r, addr, &val, size_memop(len) | MO_LE, 216 MEMTXATTRS_UNSPECIFIED); 217 return val; 218 } 219 220 static void pegasos2_mv_reg_write(Pegasos2MachineState *pm, uint32_t addr, 221 uint32_t len, uint32_t val) 222 { 223 MemoryRegion *r = sysbus_mmio_get_region(SYS_BUS_DEVICE(pm->mv), 0); 224 memory_region_dispatch_write(r, addr, val, size_memop(len) | MO_LE, 225 MEMTXATTRS_UNSPECIFIED); 226 } 227 228 static uint32_t pegasos2_pci_config_read(Pegasos2MachineState *pm, int bus, 229 uint32_t addr, uint32_t len) 230 { 231 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; 232 uint64_t val = 0xffffffffULL; 233 234 if (len <= 4) { 235 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); 236 val = pegasos2_mv_reg_read(pm, pcicfg + 4, len); 237 } 238 return val; 239 } 240 241 static void pegasos2_pci_config_write(Pegasos2MachineState *pm, int bus, 242 uint32_t addr, uint32_t len, uint32_t val) 243 { 244 hwaddr pcicfg = bus ? PCI1_CFG_ADDR : PCI0_CFG_ADDR; 245 246 pegasos2_mv_reg_write(pm, pcicfg, 4, addr | BIT(31)); 247 pegasos2_mv_reg_write(pm, pcicfg + 4, len, val); 248 } 249 250 static void pegasos2_machine_reset(MachineState *machine) 251 { 252 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 253 void *fdt; 254 uint64_t d[2]; 255 int sz; 256 257 qemu_devices_reset(); 258 if (!pm->vof) { 259 return; /* Firmware should set up machine so nothing to do */ 260 } 261 262 /* Otherwise, set up devices that board firmware would normally do */ 263 pegasos2_mv_reg_write(pm, 0, 4, 0x28020ff); 264 pegasos2_mv_reg_write(pm, 0x278, 4, 0xa31fc); 265 pegasos2_mv_reg_write(pm, 0xf300, 4, 0x11ff0400); 266 pegasos2_mv_reg_write(pm, 0xf10c, 4, 0x80000000); 267 pegasos2_mv_reg_write(pm, 0x1c, 4, 0x8000000); 268 pegasos2_pci_config_write(pm, 0, PCI_COMMAND, 2, PCI_COMMAND_IO | 269 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 270 pegasos2_pci_config_write(pm, 1, PCI_COMMAND, 2, PCI_COMMAND_IO | 271 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 272 273 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 274 PCI_INTERRUPT_LINE, 2, 0x9); 275 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 276 0x50, 1, 0x2); 277 278 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 279 PCI_INTERRUPT_LINE, 2, 0x109); 280 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 281 PCI_CLASS_PROG, 1, 0xf); 282 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 283 0x40, 1, 0xb); 284 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 285 0x50, 4, 0x17171717); 286 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | 287 PCI_COMMAND, 2, 0x87); 288 289 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 2) << 8) | 290 PCI_INTERRUPT_LINE, 2, 0x409); 291 292 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 3) << 8) | 293 PCI_INTERRUPT_LINE, 2, 0x409); 294 295 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 296 PCI_INTERRUPT_LINE, 2, 0x9); 297 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 298 0x48, 4, 0xf00); 299 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 300 0x40, 4, 0x558020); 301 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 4) << 8) | 302 0x90, 4, 0xd00); 303 304 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 5) << 8) | 305 PCI_INTERRUPT_LINE, 2, 0x309); 306 307 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 6) << 8) | 308 PCI_INTERRUPT_LINE, 2, 0x309); 309 310 /* Device tree and VOF set up */ 311 vof_init(pm->vof, machine->ram_size, &error_fatal); 312 if (vof_claim(pm->vof, 0, VOF_STACK_SIZE, VOF_STACK_SIZE) == -1) { 313 error_report("Memory allocation for stack failed"); 314 exit(1); 315 } 316 if (pm->kernel_size && 317 vof_claim(pm->vof, pm->kernel_addr, pm->kernel_size, 0) == -1) { 318 error_report("Memory for kernel is in use"); 319 exit(1); 320 } 321 fdt = build_fdt(machine, &sz); 322 /* FIXME: VOF assumes entry is same as load address */ 323 d[0] = cpu_to_be64(pm->kernel_entry); 324 d[1] = cpu_to_be64(pm->kernel_size - (pm->kernel_entry - pm->kernel_addr)); 325 qemu_fdt_setprop(fdt, "/chosen", "qemu,boot-kernel", d, sizeof(d)); 326 327 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 328 g_free(pm->fdt_blob); 329 pm->fdt_blob = fdt; 330 331 vof_build_dt(fdt, pm->vof); 332 vof_client_open_store(fdt, pm->vof, "/chosen", "stdout", "/failsafe"); 333 pm->cpu->vhyp = PPC_VIRTUAL_HYPERVISOR(machine); 334 } 335 336 enum pegasos2_rtas_tokens { 337 RTAS_RESTART_RTAS = 0, 338 RTAS_NVRAM_FETCH = 1, 339 RTAS_NVRAM_STORE = 2, 340 RTAS_GET_TIME_OF_DAY = 3, 341 RTAS_SET_TIME_OF_DAY = 4, 342 RTAS_EVENT_SCAN = 6, 343 RTAS_CHECK_EXCEPTION = 7, 344 RTAS_READ_PCI_CONFIG = 8, 345 RTAS_WRITE_PCI_CONFIG = 9, 346 RTAS_DISPLAY_CHARACTER = 10, 347 RTAS_SET_INDICATOR = 11, 348 RTAS_POWER_OFF = 17, 349 RTAS_SUSPEND = 18, 350 RTAS_HIBERNATE = 19, 351 RTAS_SYSTEM_REBOOT = 20, 352 }; 353 354 static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm, 355 target_ulong args_real) 356 { 357 AddressSpace *as = CPU(cpu)->as; 358 uint32_t token = ldl_be_phys(as, args_real); 359 uint32_t nargs = ldl_be_phys(as, args_real + 4); 360 uint32_t nrets = ldl_be_phys(as, args_real + 8); 361 uint32_t args = args_real + 12; 362 uint32_t rets = args_real + 12 + nargs * 4; 363 364 if (nrets < 1) { 365 qemu_log_mask(LOG_GUEST_ERROR, "Too few return values in RTAS call\n"); 366 return H_PARAMETER; 367 } 368 switch (token) { 369 case RTAS_GET_TIME_OF_DAY: 370 { 371 QObject *qo = object_property_get_qobject(qdev_get_machine(), 372 "rtc-time", &error_fatal); 373 QDict *qd = qobject_to(QDict, qo); 374 375 if (nargs != 0 || nrets != 8 || !qd) { 376 stl_be_phys(as, rets, -1); 377 qobject_unref(qo); 378 return H_PARAMETER; 379 } 380 381 stl_be_phys(as, rets, 0); 382 stl_be_phys(as, rets + 4, qdict_get_int(qd, "tm_year") + 1900); 383 stl_be_phys(as, rets + 8, qdict_get_int(qd, "tm_mon") + 1); 384 stl_be_phys(as, rets + 12, qdict_get_int(qd, "tm_mday")); 385 stl_be_phys(as, rets + 16, qdict_get_int(qd, "tm_hour")); 386 stl_be_phys(as, rets + 20, qdict_get_int(qd, "tm_min")); 387 stl_be_phys(as, rets + 24, qdict_get_int(qd, "tm_sec")); 388 stl_be_phys(as, rets + 28, 0); 389 qobject_unref(qo); 390 return H_SUCCESS; 391 } 392 case RTAS_READ_PCI_CONFIG: 393 { 394 uint32_t addr, len, val; 395 396 if (nargs != 2 || nrets != 2) { 397 stl_be_phys(as, rets, -1); 398 return H_PARAMETER; 399 } 400 addr = ldl_be_phys(as, args); 401 len = ldl_be_phys(as, args + 4); 402 val = pegasos2_pci_config_read(pm, !(addr >> 24), 403 addr & 0x0fffffff, len); 404 stl_be_phys(as, rets, 0); 405 stl_be_phys(as, rets + 4, val); 406 return H_SUCCESS; 407 } 408 case RTAS_WRITE_PCI_CONFIG: 409 { 410 uint32_t addr, len, val; 411 412 if (nargs != 3 || nrets != 1) { 413 stl_be_phys(as, rets, -1); 414 return H_PARAMETER; 415 } 416 addr = ldl_be_phys(as, args); 417 len = ldl_be_phys(as, args + 4); 418 val = ldl_be_phys(as, args + 8); 419 pegasos2_pci_config_write(pm, !(addr >> 24), 420 addr & 0x0fffffff, len, val); 421 stl_be_phys(as, rets, 0); 422 return H_SUCCESS; 423 } 424 case RTAS_DISPLAY_CHARACTER: 425 if (nargs != 1 || nrets != 1) { 426 stl_be_phys(as, rets, -1); 427 return H_PARAMETER; 428 } 429 qemu_log_mask(LOG_UNIMP, "%c", ldl_be_phys(as, args)); 430 stl_be_phys(as, rets, 0); 431 return H_SUCCESS; 432 default: 433 qemu_log_mask(LOG_UNIMP, "Unknown RTAS token %u (args=%u, rets=%u)\n", 434 token, nargs, nrets); 435 stl_be_phys(as, rets, 0); 436 return H_SUCCESS; 437 } 438 } 439 440 static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 441 { 442 Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp); 443 CPUPPCState *env = &cpu->env; 444 445 /* The TCG path should also be holding the BQL at this point */ 446 g_assert(qemu_mutex_iothread_locked()); 447 448 if (msr_pr) { 449 qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n"); 450 env->gpr[3] = H_PRIVILEGE; 451 } else if (env->gpr[3] == KVMPPC_H_RTAS) { 452 env->gpr[3] = pegasos2_rtas(cpu, pm, env->gpr[4]); 453 } else if (env->gpr[3] == KVMPPC_H_VOF_CLIENT) { 454 int ret = vof_client_call(MACHINE(pm), pm->vof, pm->fdt_blob, 455 env->gpr[4]); 456 env->gpr[3] = (ret ? H_PARAMETER : H_SUCCESS); 457 } else { 458 qemu_log_mask(LOG_GUEST_ERROR, "Unsupported hypercall " TARGET_FMT_lx 459 "\n", env->gpr[3]); 460 env->gpr[3] = -1; 461 } 462 } 463 464 static void vhyp_nop(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 465 { 466 } 467 468 static target_ulong vhyp_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 469 { 470 return POWERPC_CPU(current_cpu)->env.spr[SPR_SDR1]; 471 } 472 473 static bool pegasos2_setprop(MachineState *ms, const char *path, 474 const char *propname, void *val, int vallen) 475 { 476 return true; 477 } 478 479 static void pegasos2_machine_class_init(ObjectClass *oc, void *data) 480 { 481 MachineClass *mc = MACHINE_CLASS(oc); 482 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 483 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 484 485 mc->desc = "Genesi/bPlan Pegasos II"; 486 mc->init = pegasos2_init; 487 mc->reset = pegasos2_machine_reset; 488 mc->block_default_type = IF_IDE; 489 mc->default_boot_order = "cd"; 490 mc->default_display = "std"; 491 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 492 mc->default_ram_id = "pegasos2.ram"; 493 mc->default_ram_size = 512 * MiB; 494 495 vhc->hypercall = pegasos2_hypercall; 496 vhc->cpu_exec_enter = vhyp_nop; 497 vhc->cpu_exec_exit = vhyp_nop; 498 vhc->encode_hpt_for_kvm_pr = vhyp_encode_hpt_for_kvm_pr; 499 500 vmc->setprop = pegasos2_setprop; 501 } 502 503 static const TypeInfo pegasos2_machine_info = { 504 .name = TYPE_PEGASOS2_MACHINE, 505 .parent = TYPE_MACHINE, 506 .class_init = pegasos2_machine_class_init, 507 .instance_size = sizeof(Pegasos2MachineState), 508 .interfaces = (InterfaceInfo[]) { 509 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 510 { TYPE_VOF_MACHINE_IF }, 511 { } 512 }, 513 }; 514 515 static void pegasos2_machine_register_types(void) 516 { 517 type_register_static(&pegasos2_machine_info); 518 } 519 520 type_init(pegasos2_machine_register_types) 521 522 /* FDT creation for passing to firmware */ 523 524 typedef struct { 525 void *fdt; 526 const char *path; 527 } FDTInfo; 528 529 /* We do everything in reverse order so it comes out right in the tree */ 530 531 static void dt_ide(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 532 { 533 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "spi"); 534 } 535 536 static void dt_usb(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 537 { 538 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 0); 539 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 1); 540 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "usb"); 541 } 542 543 static void dt_isa(PCIBus *bus, PCIDevice *d, FDTInfo *fi) 544 { 545 GString *name = g_string_sized_new(64); 546 uint32_t cells[3]; 547 548 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#size-cells", 1); 549 qemu_fdt_setprop_cell(fi->fdt, fi->path, "#address-cells", 2); 550 qemu_fdt_setprop_string(fi->fdt, fi->path, "device_type", "isa"); 551 qemu_fdt_setprop_string(fi->fdt, fi->path, "name", "isa"); 552 553 /* addional devices */ 554 g_string_printf(name, "%s/lpt@i3bc", fi->path); 555 qemu_fdt_add_subnode(fi->fdt, name->str); 556 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 557 cells[0] = cpu_to_be32(7); 558 cells[1] = 0; 559 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 560 cells, 2 * sizeof(cells[0])); 561 cells[0] = cpu_to_be32(1); 562 cells[1] = cpu_to_be32(0x3bc); 563 cells[2] = cpu_to_be32(8); 564 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 565 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "lpt"); 566 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "lpt"); 567 568 g_string_printf(name, "%s/fdc@i3f0", fi->path); 569 qemu_fdt_add_subnode(fi->fdt, name->str); 570 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 571 cells[0] = cpu_to_be32(6); 572 cells[1] = 0; 573 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 574 cells, 2 * sizeof(cells[0])); 575 cells[0] = cpu_to_be32(1); 576 cells[1] = cpu_to_be32(0x3f0); 577 cells[2] = cpu_to_be32(8); 578 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 579 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "fdc"); 580 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "fdc"); 581 582 g_string_printf(name, "%s/timer@i40", fi->path); 583 qemu_fdt_add_subnode(fi->fdt, name->str); 584 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 585 cells[0] = cpu_to_be32(1); 586 cells[1] = cpu_to_be32(0x40); 587 cells[2] = cpu_to_be32(8); 588 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 589 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "timer"); 590 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "timer"); 591 592 g_string_printf(name, "%s/rtc@i70", fi->path); 593 qemu_fdt_add_subnode(fi->fdt, name->str); 594 qemu_fdt_setprop_string(fi->fdt, name->str, "compatible", "ds1385-rtc"); 595 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 596 cells[0] = cpu_to_be32(8); 597 cells[1] = 0; 598 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 599 cells, 2 * sizeof(cells[0])); 600 cells[0] = cpu_to_be32(1); 601 cells[1] = cpu_to_be32(0x70); 602 cells[2] = cpu_to_be32(2); 603 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 604 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "rtc"); 605 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "rtc"); 606 607 g_string_printf(name, "%s/keyboard@i60", fi->path); 608 qemu_fdt_add_subnode(fi->fdt, name->str); 609 cells[0] = cpu_to_be32(1); 610 cells[1] = 0; 611 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 612 cells, 2 * sizeof(cells[0])); 613 cells[0] = cpu_to_be32(1); 614 cells[1] = cpu_to_be32(0x60); 615 cells[2] = cpu_to_be32(5); 616 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 617 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "keyboard"); 618 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "keyboard"); 619 620 g_string_printf(name, "%s/8042@i60", fi->path); 621 qemu_fdt_add_subnode(fi->fdt, name->str); 622 qemu_fdt_setprop_cell(fi->fdt, name->str, "#interrupt-cells", 2); 623 qemu_fdt_setprop_cell(fi->fdt, name->str, "#size-cells", 0); 624 qemu_fdt_setprop_cell(fi->fdt, name->str, "#address-cells", 1); 625 qemu_fdt_setprop_string(fi->fdt, name->str, "interrupt-controller", ""); 626 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 627 cells[0] = cpu_to_be32(1); 628 cells[1] = cpu_to_be32(0x60); 629 cells[2] = cpu_to_be32(5); 630 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 631 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", ""); 632 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "8042"); 633 634 g_string_printf(name, "%s/serial@i2f8", fi->path); 635 qemu_fdt_add_subnode(fi->fdt, name->str); 636 qemu_fdt_setprop_cell(fi->fdt, name->str, "clock-frequency", 0); 637 cells[0] = cpu_to_be32(3); 638 cells[1] = 0; 639 qemu_fdt_setprop(fi->fdt, name->str, "interrupts", 640 cells, 2 * sizeof(cells[0])); 641 cells[0] = cpu_to_be32(1); 642 cells[1] = cpu_to_be32(0x2f8); 643 cells[2] = cpu_to_be32(8); 644 qemu_fdt_setprop(fi->fdt, name->str, "reg", cells, 3 * sizeof(cells[0])); 645 qemu_fdt_setprop_string(fi->fdt, name->str, "device_type", "serial"); 646 qemu_fdt_setprop_string(fi->fdt, name->str, "name", "serial"); 647 648 g_string_free(name, TRUE); 649 } 650 651 static struct { 652 const char *id; 653 const char *name; 654 void (*dtf)(PCIBus *bus, PCIDevice *d, FDTInfo *fi); 655 } device_map[] = { 656 { "pci11ab,6460", "host", NULL }, 657 { "pci1106,8231", "isa", dt_isa }, 658 { "pci1106,571", "ide", dt_ide }, 659 { "pci1106,3044", "firewire", NULL }, 660 { "pci1106,3038", "usb", dt_usb }, 661 { "pci1106,8235", "other", NULL }, 662 { "pci1106,3058", "sound", NULL }, 663 { NULL, NULL } 664 }; 665 666 static void add_pci_device(PCIBus *bus, PCIDevice *d, void *opaque) 667 { 668 FDTInfo *fi = opaque; 669 GString *node = g_string_new(NULL); 670 uint32_t cells[(PCI_NUM_REGIONS + 1) * 5]; 671 int i, j; 672 const char *name = NULL; 673 g_autofree const gchar *pn = g_strdup_printf("pci%x,%x", 674 pci_get_word(&d->config[PCI_VENDOR_ID]), 675 pci_get_word(&d->config[PCI_DEVICE_ID])); 676 677 for (i = 0; device_map[i].id; i++) { 678 if (!strcmp(pn, device_map[i].id)) { 679 name = device_map[i].name; 680 break; 681 } 682 } 683 g_string_printf(node, "%s/%s@%x", fi->path, (name ?: pn), 684 PCI_SLOT(d->devfn)); 685 if (PCI_FUNC(d->devfn)) { 686 g_string_append_printf(node, ",%x", PCI_FUNC(d->devfn)); 687 } 688 689 qemu_fdt_add_subnode(fi->fdt, node->str); 690 if (device_map[i].dtf) { 691 FDTInfo cfi = { fi->fdt, node->str }; 692 device_map[i].dtf(bus, d, &cfi); 693 } 694 cells[0] = cpu_to_be32(d->devfn << 8); 695 cells[1] = 0; 696 cells[2] = 0; 697 cells[3] = 0; 698 cells[4] = 0; 699 j = 5; 700 for (i = 0; i < PCI_NUM_REGIONS; i++) { 701 if (!d->io_regions[i].size) { 702 continue; 703 } 704 cells[j] = cpu_to_be32(d->devfn << 8 | (PCI_BASE_ADDRESS_0 + i * 4)); 705 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 706 cells[j] |= cpu_to_be32(1 << 24); 707 } else { 708 cells[j] |= cpu_to_be32(2 << 24); 709 if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_PREFETCH) { 710 cells[j] |= cpu_to_be32(4 << 28); 711 } 712 } 713 cells[j + 1] = 0; 714 cells[j + 2] = 0; 715 cells[j + 3] = cpu_to_be32(d->io_regions[i].size >> 32); 716 cells[j + 4] = cpu_to_be32(d->io_regions[i].size); 717 j += 5; 718 } 719 qemu_fdt_setprop(fi->fdt, node->str, "reg", cells, j * sizeof(cells[0])); 720 qemu_fdt_setprop_string(fi->fdt, node->str, "name", name ?: pn); 721 if (pci_get_byte(&d->config[PCI_INTERRUPT_PIN])) { 722 qemu_fdt_setprop_cell(fi->fdt, node->str, "interrupts", 723 pci_get_byte(&d->config[PCI_INTERRUPT_PIN])); 724 } 725 /* Pegasos2 firmware has subsystem-id amd subsystem-vendor-id swapped */ 726 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-vendor-id", 727 pci_get_word(&d->config[PCI_SUBSYSTEM_ID])); 728 qemu_fdt_setprop_cell(fi->fdt, node->str, "subsystem-id", 729 pci_get_word(&d->config[PCI_SUBSYSTEM_VENDOR_ID])); 730 cells[0] = pci_get_long(&d->config[PCI_CLASS_REVISION]); 731 qemu_fdt_setprop_cell(fi->fdt, node->str, "class-code", cells[0] >> 8); 732 qemu_fdt_setprop_cell(fi->fdt, node->str, "revision-id", cells[0] & 0xff); 733 qemu_fdt_setprop_cell(fi->fdt, node->str, "device-id", 734 pci_get_word(&d->config[PCI_DEVICE_ID])); 735 qemu_fdt_setprop_cell(fi->fdt, node->str, "vendor-id", 736 pci_get_word(&d->config[PCI_VENDOR_ID])); 737 738 g_string_free(node, TRUE); 739 } 740 741 static void *build_fdt(MachineState *machine, int *fdt_size) 742 { 743 Pegasos2MachineState *pm = PEGASOS2_MACHINE(machine); 744 PowerPCCPU *cpu = pm->cpu; 745 PCIBus *pci_bus; 746 FDTInfo fi; 747 uint32_t cells[16]; 748 void *fdt = create_device_tree(fdt_size); 749 750 fi.fdt = fdt; 751 752 /* root node */ 753 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,description", 754 "Pegasos CHRP PowerPC System"); 755 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,board", "Pegasos2"); 756 qemu_fdt_setprop_string(fdt, "/", "CODEGEN,vendor", "bplan GmbH"); 757 qemu_fdt_setprop_string(fdt, "/", "revision", "2B"); 758 qemu_fdt_setprop_string(fdt, "/", "model", "Pegasos2"); 759 qemu_fdt_setprop_string(fdt, "/", "device_type", "chrp"); 760 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 1); 761 qemu_fdt_setprop_string(fdt, "/", "name", "bplan,Pegasos2"); 762 763 /* pci@c0000000 */ 764 qemu_fdt_add_subnode(fdt, "/pci@c0000000"); 765 cells[0] = 0; 766 cells[1] = 0; 767 qemu_fdt_setprop(fdt, "/pci@c0000000", "bus-range", 768 cells, 2 * sizeof(cells[0])); 769 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "pci-bridge-number", 1); 770 cells[0] = cpu_to_be32(PCI0_MEM_BASE); 771 cells[1] = cpu_to_be32(PCI0_MEM_SIZE); 772 qemu_fdt_setprop(fdt, "/pci@c0000000", "reg", cells, 2 * sizeof(cells[0])); 773 cells[0] = cpu_to_be32(0x01000000); 774 cells[1] = 0; 775 cells[2] = 0; 776 cells[3] = cpu_to_be32(PCI0_IO_BASE); 777 cells[4] = 0; 778 cells[5] = cpu_to_be32(PCI0_IO_SIZE); 779 cells[6] = cpu_to_be32(0x02000000); 780 cells[7] = 0; 781 cells[8] = cpu_to_be32(PCI0_MEM_BASE); 782 cells[9] = cpu_to_be32(PCI0_MEM_BASE); 783 cells[10] = 0; 784 cells[11] = cpu_to_be32(PCI0_MEM_SIZE); 785 qemu_fdt_setprop(fdt, "/pci@c0000000", "ranges", 786 cells, 12 * sizeof(cells[0])); 787 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#size-cells", 2); 788 qemu_fdt_setprop_cell(fdt, "/pci@c0000000", "#address-cells", 3); 789 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "device_type", "pci"); 790 qemu_fdt_setprop_string(fdt, "/pci@c0000000", "name", "pci"); 791 792 fi.path = "/pci@c0000000"; 793 pci_bus = mv64361_get_pci_bus(pm->mv, 0); 794 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); 795 796 /* pci@80000000 */ 797 qemu_fdt_add_subnode(fdt, "/pci@80000000"); 798 cells[0] = 0; 799 cells[1] = 0; 800 qemu_fdt_setprop(fdt, "/pci@80000000", "bus-range", 801 cells, 2 * sizeof(cells[0])); 802 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "pci-bridge-number", 0); 803 cells[0] = cpu_to_be32(PCI1_MEM_BASE); 804 cells[1] = cpu_to_be32(PCI1_MEM_SIZE); 805 qemu_fdt_setprop(fdt, "/pci@80000000", "reg", cells, 2 * sizeof(cells[0])); 806 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "8259-interrupt-acknowledge", 807 0xf1000cb4); 808 cells[0] = cpu_to_be32(0x01000000); 809 cells[1] = 0; 810 cells[2] = 0; 811 cells[3] = cpu_to_be32(PCI1_IO_BASE); 812 cells[4] = 0; 813 cells[5] = cpu_to_be32(PCI1_IO_SIZE); 814 cells[6] = cpu_to_be32(0x02000000); 815 cells[7] = 0; 816 cells[8] = cpu_to_be32(PCI1_MEM_BASE); 817 cells[9] = cpu_to_be32(PCI1_MEM_BASE); 818 cells[10] = 0; 819 cells[11] = cpu_to_be32(PCI1_MEM_SIZE); 820 qemu_fdt_setprop(fdt, "/pci@80000000", "ranges", 821 cells, 12 * sizeof(cells[0])); 822 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#size-cells", 2); 823 qemu_fdt_setprop_cell(fdt, "/pci@80000000", "#address-cells", 3); 824 qemu_fdt_setprop_string(fdt, "/pci@80000000", "device_type", "pci"); 825 qemu_fdt_setprop_string(fdt, "/pci@80000000", "name", "pci"); 826 827 fi.path = "/pci@80000000"; 828 pci_bus = mv64361_get_pci_bus(pm->mv, 1); 829 pci_for_each_device_reverse(pci_bus, 0, add_pci_device, &fi); 830 831 qemu_fdt_add_subnode(fdt, "/failsafe"); 832 qemu_fdt_setprop_string(fdt, "/failsafe", "device_type", "serial"); 833 qemu_fdt_setprop_string(fdt, "/failsafe", "name", "failsafe"); 834 835 qemu_fdt_add_subnode(fdt, "/rtas"); 836 qemu_fdt_setprop_cell(fdt, "/rtas", "system-reboot", RTAS_SYSTEM_REBOOT); 837 qemu_fdt_setprop_cell(fdt, "/rtas", "hibernate", RTAS_HIBERNATE); 838 qemu_fdt_setprop_cell(fdt, "/rtas", "suspend", RTAS_SUSPEND); 839 qemu_fdt_setprop_cell(fdt, "/rtas", "power-off", RTAS_POWER_OFF); 840 qemu_fdt_setprop_cell(fdt, "/rtas", "set-indicator", RTAS_SET_INDICATOR); 841 qemu_fdt_setprop_cell(fdt, "/rtas", "display-character", 842 RTAS_DISPLAY_CHARACTER); 843 qemu_fdt_setprop_cell(fdt, "/rtas", "write-pci-config", 844 RTAS_WRITE_PCI_CONFIG); 845 qemu_fdt_setprop_cell(fdt, "/rtas", "read-pci-config", 846 RTAS_READ_PCI_CONFIG); 847 /* Pegasos2 firmware misspells check-exception and guests use that */ 848 qemu_fdt_setprop_cell(fdt, "/rtas", "check-execption", 849 RTAS_CHECK_EXCEPTION); 850 qemu_fdt_setprop_cell(fdt, "/rtas", "event-scan", RTAS_EVENT_SCAN); 851 qemu_fdt_setprop_cell(fdt, "/rtas", "set-time-of-day", 852 RTAS_SET_TIME_OF_DAY); 853 qemu_fdt_setprop_cell(fdt, "/rtas", "get-time-of-day", 854 RTAS_GET_TIME_OF_DAY); 855 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-store", RTAS_NVRAM_STORE); 856 qemu_fdt_setprop_cell(fdt, "/rtas", "nvram-fetch", RTAS_NVRAM_FETCH); 857 qemu_fdt_setprop_cell(fdt, "/rtas", "restart-rtas", RTAS_RESTART_RTAS); 858 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-error-log-max", 0); 859 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-event-scan-rate", 0); 860 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-display-device", 0); 861 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size", 20); 862 qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-version", 1); 863 864 /* cpus */ 865 qemu_fdt_add_subnode(fdt, "/cpus"); 866 qemu_fdt_setprop_cell(fdt, "/cpus", "#cpus", 1); 867 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 868 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 869 qemu_fdt_setprop_string(fdt, "/cpus", "name", "cpus"); 870 871 /* FIXME Get CPU name from CPU object */ 872 const char *cp = "/cpus/PowerPC,G4"; 873 qemu_fdt_add_subnode(fdt, cp); 874 qemu_fdt_setprop_cell(fdt, cp, "l2cr", 0); 875 qemu_fdt_setprop_cell(fdt, cp, "d-cache-size", 0x8000); 876 qemu_fdt_setprop_cell(fdt, cp, "d-cache-block-size", 877 cpu->env.dcache_line_size); 878 qemu_fdt_setprop_cell(fdt, cp, "d-cache-line-size", 879 cpu->env.dcache_line_size); 880 qemu_fdt_setprop_cell(fdt, cp, "i-cache-size", 0x8000); 881 qemu_fdt_setprop_cell(fdt, cp, "i-cache-block-size", 882 cpu->env.icache_line_size); 883 qemu_fdt_setprop_cell(fdt, cp, "i-cache-line-size", 884 cpu->env.icache_line_size); 885 if (cpu->env.id_tlbs) { 886 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-sets", cpu->env.nb_ways); 887 qemu_fdt_setprop_cell(fdt, cp, "i-tlb-size", cpu->env.tlb_per_way); 888 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-sets", cpu->env.nb_ways); 889 qemu_fdt_setprop_cell(fdt, cp, "d-tlb-size", cpu->env.tlb_per_way); 890 qemu_fdt_setprop_string(fdt, cp, "tlb-split", ""); 891 } 892 qemu_fdt_setprop_cell(fdt, cp, "tlb-sets", cpu->env.nb_ways); 893 qemu_fdt_setprop_cell(fdt, cp, "tlb-size", cpu->env.nb_tlb); 894 qemu_fdt_setprop_string(fdt, cp, "state", "running"); 895 if (cpu->env.insns_flags & PPC_ALTIVEC) { 896 qemu_fdt_setprop_string(fdt, cp, "altivec", ""); 897 qemu_fdt_setprop_string(fdt, cp, "data-streams", ""); 898 } 899 /* 900 * FIXME What flags do data-streams, external-control and 901 * performance-monitor depend on? 902 */ 903 qemu_fdt_setprop_string(fdt, cp, "external-control", ""); 904 if (cpu->env.insns_flags & PPC_FLOAT_FSQRT) { 905 qemu_fdt_setprop_string(fdt, cp, "general-purpose", ""); 906 } 907 qemu_fdt_setprop_string(fdt, cp, "performance-monitor", ""); 908 if (cpu->env.insns_flags & PPC_FLOAT_FRES) { 909 qemu_fdt_setprop_string(fdt, cp, "graphics", ""); 910 } 911 qemu_fdt_setprop_cell(fdt, cp, "reservation-granule-size", 4); 912 qemu_fdt_setprop_cell(fdt, cp, "timebase-frequency", 913 cpu->env.tb_env->tb_freq); 914 qemu_fdt_setprop_cell(fdt, cp, "bus-frequency", BUS_FREQ_HZ); 915 qemu_fdt_setprop_cell(fdt, cp, "clock-frequency", BUS_FREQ_HZ * 7.5); 916 qemu_fdt_setprop_cell(fdt, cp, "cpu-version", cpu->env.spr[SPR_PVR]); 917 cells[0] = 0; 918 cells[1] = 0; 919 qemu_fdt_setprop(fdt, cp, "reg", cells, 2 * sizeof(cells[0])); 920 qemu_fdt_setprop_string(fdt, cp, "device_type", "cpu"); 921 qemu_fdt_setprop_string(fdt, cp, "name", strrchr(cp, '/') + 1); 922 923 /* memory */ 924 qemu_fdt_add_subnode(fdt, "/memory@0"); 925 cells[0] = 0; 926 cells[1] = cpu_to_be32(machine->ram_size); 927 qemu_fdt_setprop(fdt, "/memory@0", "reg", cells, 2 * sizeof(cells[0])); 928 qemu_fdt_setprop_string(fdt, "/memory@0", "device_type", "memory"); 929 qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory"); 930 931 qemu_fdt_add_subnode(fdt, "/chosen"); 932 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 933 machine->kernel_cmdline ?: ""); 934 qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen"); 935 936 qemu_fdt_add_subnode(fdt, "/openprom"); 937 qemu_fdt_setprop_string(fdt, "/openprom", "model", "Pegasos2,1.1"); 938 939 return fdt; 940 } 941